KR100337455B1 - 반도체패키지 - Google Patents
반도체패키지 Download PDFInfo
- Publication number
- KR100337455B1 KR100337455B1 KR1019980046561A KR19980046561A KR100337455B1 KR 100337455 B1 KR100337455 B1 KR 100337455B1 KR 1019980046561 A KR1019980046561 A KR 1019980046561A KR 19980046561 A KR19980046561 A KR 19980046561A KR 100337455 B1 KR100337455 B1 KR 100337455B1
- Authority
- KR
- South Korea
- Prior art keywords
- circuit board
- semiconductor chip
- board sheet
- input
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (2)
- 상면에 입출력패드가 형성되어 있는 반도체칩과;상기 반도체칩의 상부에 그 반도체칩의 상면 넓이보다 더 넓게 폴리이미드층이 위치되어 있고, 상기 폴리이미드층 상면에는 구리재질의 본드핑거, 연결부 및 솔더볼랜드의 회로패턴이 형성되어 있으며, 상기 폴리이미드층의 최외곽 둘레 부근에 구리재질로 대략 링형태의 링패턴이 형성되어 있으며, 상기 본드핑거 및 솔더볼랜드를 제외한 폴리이미드층 상부에는 커버코오트가 코팅되어 있되, 상기 반도체칩의 입출력패드와 대응되는 부분에는 관통되어 일정크기의 관통부가 형성되어 있는 회로기판시트와;상기 반도체칩의 입출력패드 및 회로기판시트의 관통부와 대응되는 영역이 관통된 채 상기 반도체칩과 회로기판시트 사이 및 반도체칩의 상부 외주연에 위치함으로써 상기 회로기판시트를 반도체칩의 상면에 접착시킴과 동시에 최외곽의 회로기판시트 영역의 휨 현상을 억제하는 접착성 일레스토머와;상기 회로기판시트의 관통부 저면에 위치하는 반도체칩의 입출력패드와 상기 회로기판시트의 본드핑거를 전기적으로 연결하는 전도성와이어와;상기 전도성와이어 등을 외부의 환경으로부터 보호하기 위해 상기 회로기판시트의 관통부에 채워진 봉지재와;상기 회로기판시트의 솔더볼랜드에 융착되어 반도체칩의 신호를 외부로 입출력하는 솔더볼을 포함하여 이루어진 반도체패키지.
- 제1항에 있어서, 상기 반도체칩의 상부 외주연에 위치하는 본드핑거 및 연결부 등의 회로패턴은 반도체칩의 상부 내주연에 위치하는 본드핑거 및 연결부의 폭보다 더 넓게 형성됨으로써 회로기판시트의 둘레 부분에 대한 강성이 증대되도록 한 것을 특징으로 하는 반도체패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980046561A KR100337455B1 (ko) | 1998-10-31 | 1998-10-31 | 반도체패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980046561A KR100337455B1 (ko) | 1998-10-31 | 1998-10-31 | 반도체패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000028356A KR20000028356A (ko) | 2000-05-25 |
KR100337455B1 true KR100337455B1 (ko) | 2002-07-18 |
Family
ID=19556716
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019980046561A KR100337455B1 (ko) | 1998-10-31 | 1998-10-31 | 반도체패키지 |
Country Status (1)
Country | Link |
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KR (1) | KR100337455B1 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100583493B1 (ko) * | 2000-10-25 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
KR100618892B1 (ko) * | 2005-04-13 | 2006-09-01 | 삼성전자주식회사 | 와이어 본딩을 통해 팬 아웃 구조를 달성하는 반도체패키지 |
KR101700955B1 (ko) * | 2015-05-21 | 2017-01-31 | 장성은 | 휴대형 태양전지 패널용 기판 및 그 제조방법 |
-
1998
- 1998-10-31 KR KR1019980046561A patent/KR100337455B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20000028356A (ko) | 2000-05-25 |
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