CN106952880A - Semiconductor device and use its portable set - Google Patents

Semiconductor device and use its portable set Download PDF

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Publication number
CN106952880A
CN106952880A CN201611127563.2A CN201611127563A CN106952880A CN 106952880 A CN106952880 A CN 106952880A CN 201611127563 A CN201611127563 A CN 201611127563A CN 106952880 A CN106952880 A CN 106952880A
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Prior art keywords
encapsulation
transistor
chip
semiconductor chip
source electrode
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CN201611127563.2A
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CN106952880B (en
Inventor
柳田正道
小谷野雅史
松浦伸悌
新井宽己
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UPI Semiconductor Corp
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Ubiq Semiconductor Corp
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  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
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  • Telephone Set Structure (AREA)

Abstract

The present invention provides a kind of achievable package dimension miniaturization or is thinned, while maintaining MOSFET characteristics, and can reduce the semiconductor device of conduction resistance value and use its portable set.The gate electrode 26 and 28 of semiconductor chip 10 is configured near 2 sides 2A and 2B of the long side direction (paper X-direction) of encapsulation 2, and long side direction of the gate terminal 13 and 14 encapsulated with the upside-down mounting of gate electrode 26 and 28 (flip chip) along encapsulation 2 extends, and drawn from 2 sides 2A and 2B toward outside.Constructed by this, die size can be enable to be maximized relative to package dimension, and then it is high performance that can make as the element characteristic of module.

Description

Semiconductor device and use its portable set
Technical field
The present invention is, on a kind of encapsulation (package) of the built-in multiple chips of tool, to be encapsulated using upside-down mounting (flip-chip) To reduce conduction resistance value, while the semiconductor device of miniaturization or the slimming of package dimension can be realized and using the portable of its Formula equipment.
Background technology
Construction shown in well known Fig. 6 is as the semiconductor device for common charge protection device.Yu Rutu In shown resin-encapsulated 101, inside have：It is used as (hereinafter referred to as " the charging FET of FET 102 of charge control switch 102”)；The FET 103 (hereinafter referred to as " electric discharge use FET 103 ") switched as control of discharge；And protection IC 104.With dotted line The object-line of linear system resin-encapsulated 101 shown in 105,1 packaging structure is realized with this.
Charging is fixed on lead frame (lead with FET 102 drain electrode through elargol (silver paste) Frame) on the internal pin 107 of 106 die pad (diepad).And, charging is electric with FET 102 source electrode 108 and grid Pole 109 is electrically connected at the inside pin (Inner lead) 107 of lead frame (frame) 106 through wiring 110.
Electric discharge is also same with charging FET 102 with FET 103 and protection IC 104, is fixed on lead frame 106, and thoroughly Cross wiring 110 and be electrically connected at internal pin 107 (for example referenced patent document 1).
In addition, construction shown in well known Fig. 7 has multiple power metal-oxide semiconductors as in common The semiconductor of field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) Device.2 MOSFET 121 and 122 as depicted are fixed in above the installation portion 123 of lead frame, installation portion 123 from Drawn with 4 drain terminals 125 toward outside on the one side side of encapsulation 124.In addition, lead frame is formed with and 123 points of installation portion From gate terminal 126 and 127 and source terminal 128 and 129, it is from the side for the encapsulation 124 drawn with drain terminal 125 The side of opposite side is out of the ordinary toward outside extraction.
MOSFET 121 source electrode 130 passes through 3 bond wires (bonding wire) 131 with source terminal 128 It is electrically connected with, MOSFET 122 source electrode 132 and source terminal 129 are electrically connected with by 3 bond wires 133, such as schemes It is shown, high current (for example referenced patent is respectively realized using a plurality of bond wire 131 and 133 to source electrode 130 and 132 Document 2).
In addition, construction shown in well known Fig. 8 is used as the semiconductor device that MOSFET is had in common.As schemed Show, on the interarea of silicon 141 for forming power MOSFET, be formed with source electrode pad (source electrode) 142 and grid pad (gate electrode) 143, drain electrode pad (not shown) is formed with the back side.Furthermore, silicon 141 connects and is engaged in through elargol Above die pad (die pad) 144 so that 4 pins 145 of the drain electrode being connected with die pad 144 can be from resin-encapsulated Drawn toward outside 146 side.
The source electrode pad 142 of silicon 141 is electrically connected with the pin 148 of source electrode by aluminium strip (Al ribbon) 147 Connect, and then realize the conduction resistance value of reduction.Furthermore so that 3 pins 148 of source electrode can be from the side drawn with pin 145 Drawn for the side of the resin-encapsulated 146 of opposite side toward outside in face.The grid pad 143 of silicon 141 leads to lead frame The electric connection of wire (Al wire) 149 is crossed, making the pin 150 of grid can draw from the side of resin-encapsulated 146 toward outside (for example referenced patent document 3).
Patent document
Patent document 1：JP 2010-11736 publications
Patent document 2：JP 2009-38138 publications
Patent document 3：JP 2013-16837 publications
The content of the invention
The problem of invention is to be solved
In recent years, with mobile phone or smart mobile phone etc. portable set miniaturization or slimming, portion in the inner The miniaturization or slimming of the electronic unit used are also relative required.Therefore, it is necessary to realize corresponding to electronic unit High current, the miniaturization of the conduction resistance value or package dimension of reduction.
Semiconductor device as shown in Figure 6 is the protection device of the secondary cell for lithium ion battery etc..Also, charging With FET 102, discharge is configured above lead frame 106 side by side with FET 103 and protection IC 104, though 1 encapsulation is formed, But without using the mutual stack structure of chip, the problem of being difficult to reach the miniaturization of more resin-encapsulateds will be produced.
In addition, on semiconductor device as shown in Figure 6, the charging for flowing through high current uses FET 102 source electrode electric Pole 108 or electric discharge are with for FET 103 source electrode 111, due to being connected with the tectonic relationship of wiring 110, so can produce The problem of being difficult to reach reduction conduction resistance value.
In this, on semiconductor device as shown in Figures 7 and 8, though not interior have IC chip, as shown in fig. 7, in order to To correspond to high current, the construction of the well known bond wire 131 and 133 using a plurality of thick line.In addition, in using a plurality of On the construction of the bond wire 131 and 133 of thick line, it is difficult to reduce conduction resistance value, as shown in figure 8, by using aluminium strip 147, High current is may correspond to, while reaching that the construction of reduction conduction resistance value or connection resistance value is also common.
Based on above-mentioned, on the semiconductor device shown in Fig. 6, conducting resistance can be reduced corresponding to high current using aluminium strip Value, but aluminium strip is in order to corresponding to high current etc., it will usually formation, which is covered, is fixed on the almost whole of source electrode 108 and 111 Construction on face.Based on this construction, from the viewpoint of space, protection IC 104 is allowed to be stacked over charging FET 102 and put Electricity is more difficult above with FET 103, the problem of producing the miniaturization for being difficult to reach resin-encapsulated using the construction of aluminium strip.
In addition, with the slimming of above-mentioned portable set, it is incorporated in the circuit substrate in the encapsulation of portable set, For example it is used for carrying out the size of the protection circuit substrate of the battery management of the discharge and recharge of the secondary cell of lithium ion battery etc., will It is restricted due to the thickness of portable set.Therefore, even being packaged in the size of the electronic unit of protection circuit substrate Also it can therewith be restricted, in order in maximizing element characteristic in the limitation of the size, and realize the conducting resistance of above-mentioned reduction Value, also seeks the design of the layout (layout) of the electrode based on semiconductor chip or the layout of framework.
The present invention is to invent it in view of the above, and multiple chip structures are had for interior in 1 encapsulation (package) Make there is provided a kind of semiconductor device and use its portable set, the semiconductor device and made using its portable set Encapsulated with upside-down mounting (flip-chip), it is possible to decrease conduction resistance value, while can also realize the miniaturization or slimming of package dimension.
The technological means solved the problems, such as
The semiconductor device of the present invention, wherein possessing：Framework；One interarea quilt of semiconductor chip, wherein semiconductor chip Flip-chip packaged is on framework；IC chip, IC chip storehouse and be fixed on the interarea of semiconductor chip to another interarea On；Plain conductor, plain conductor is used for being electrically connected with semiconductor chip and IC chip；And encapsulation, potting framework, semiconductor Chip, IC chip and plain conductor, wherein, encapsulation with long side direction to 2 sides, be formed with semiconductor chip The first transistor and transistor seconds, are formed on the gate electrode (GateElectrode) of the first transistor on the interarea side It is configured in the side face edge on wherein one side of encapsulation.
In addition, in the semiconductor device of the present invention, the framework edge of the gate electrode institute flip-chip packaged of the first transistor is long Edge direction extends and exposed from the wherein side side of encapsulation, and the framework of the gate electrode institute flip-chip packaged of transistor seconds is then Extend along long side direction and expose from the opposing party side of encapsulation.
In addition, in the semiconductor device of the present invention, being led for being electrically connected with the metal of gate electrode of the first transistor Line and the framework between the gate electrode of the first transistor and a wherein side side for encapsulation are connected；For being electrically connected with second The plain conductor of the gate electrode of transistor and the frame between the gate electrode of transistor seconds and the opposing party side of encapsulation Frame is connected.
In addition, in the semiconductor device of the present invention, semiconductor chip has：Be formed on one interarea side first is brilliant The source electrode of body pipe；It is formed on the source electrode of the transistor seconds on one interarea side；And it is formed on its another master The first transistor on face side and the common drain electrode (Drain Electrode) of transistor seconds, the source electrode of the first transistor The framework of electrode institute flip-chip packaged exposes from the side in a wherein direction for encapsulation；The source electrode institute upside-down mounting envelope of transistor seconds Expose side of the framework of dress then from the other direction of encapsulation.
In addition, the semiconductor device of the present invention has：This is configured at the gate electrode of the first transistor side by side partly to lead The source electrode of the first transistor of the long side direction of body chip；And be configured at side by side with the gate electrode of transistor seconds The gate electrode of the source electrode of the transistor seconds of the long side direction of semiconductor chip, wherein the first transistor and source electrode electricity The gate electrode of pole and transistor seconds and source electrode be relative to semiconductor chip central point be configured to it is rotationally symmetrical 's.
In addition, in the portable set of the present invention, the encapsulation of semiconductor device is installed in the secondary of portable set On the protection circuit substrate of battery, the long side direction configuration of the long side direction of encapsulation along protection circuit substrate, protection circuit base The short side direction of plate is then configured along the thickness direction of the housing of portable set.
Effect against existing technologies
In the semiconductor device of the present invention, there is semiconductor chip in flip-chip packaged on lead frame, above semiconductor chip Storehouse has the IC chip for controlling semiconductor chip.Semiconductor chip and IC chip are electrically connected with by plain conductor.Again Person, 2 gate electrodes of semiconductor chip be configured in the long side direction of encapsulation to side near, fallen with above-mentioned electrode The lead frame of dress encapsulation exposes from 2 sides of encapsulation.Constructed by this, die size can be made relative to package dimension Maximized, and can high performance as the element characteristic of module.
In addition, on the semiconductor device of the present invention, 2 gate electrodes of semiconductor chip are configured in two sides of encapsulation Face side so that extend with the lead frame of above-mentioned gate electrode flip-chip packaged along the long side direction encapsulated.Furthermore, utilize above-mentioned gold Category wire be connected on the lead frame extended along long side direction so that die size can relative to encapsulation short side direction Reach maximization.
In addition, on the semiconductor device of the present invention, die size can be maximized relative to package dimension.
In addition, on the semiconductor device of the present invention, being formed with 2 MOSFET in semiconductor chip, making each source electrode And gate electrode can be configured to relative to the central point of semiconductor chip it is rotationally symmetrical.Based on this construction, even if in semiconductor Chip relative to lead frame from correct position rotate to 180 degree state and it is packed in the case of also can start, encapsulated The yield of undue influence and then it can be improved.
In addition, in the portable set of the present invention, can be relative to the guarantor for being accommodated in the secondary cell being thinned in housing Protection circuit substrate encapsulates the above-mentioned encapsulation of miniaturization.Constructed by this, power consumption can be suppressed, can also realize to make for a long time Portable set.
Brief description of the drawings
The in-built plan of the semiconductor device of the preferable embodiments of Fig. 1 to illustrate the invention.
The preferable embodiment of Fig. 2 (A) and Fig. 2 (B) to illustrate the invention is built partly leading in semiconductor device Body chip, wherein Fig. 2 (A) are plan, and Fig. 2 (B) is profile.
The internal structure of the semiconductor device of the preferable embodiment of Fig. 3 (A) and Fig. 3 (B) to illustrate the invention, wherein Fig. 3 (A) is profile, and Fig. 3 (B) is profile.
Fig. 4 (A) of the preferable embodiments of Fig. 4 (A) to Fig. 4 (C) to illustrate the invention is the inside of semiconductor device Construction plan view, Fig. 4 (B) is is built in the plan of the semiconductor chip of semiconductor device, and Fig. 4 (C) is for semiconductor The plan of the lead frame of device.
Fig. 5 (A) to Fig. 5 (D) is that the portable of semiconductor device for illustrating the preferable embodiment using the present invention sets Standby schematic diagram, wherein Fig. 5 (A) are the oblique view for the housing for illustrating portable set, and Fig. 5 (B) is circuit diagram, and Fig. 5 (C) is to say The plan of the protection circuit substrate of the secondary cell of bright portable set, Fig. 5 (D) is the secondary cell for illustrating portable set Protection circuit substrate plan.
Fig. 6 is the in-built plan for illustrating common semiconductor device.
Fig. 7 is the in-built plan for illustrating common semiconductor device.
Fig. 8 is the in-built plan for illustrating common semiconductor device.
Main element symbol description：
1st, 51 semiconductor device
2nd, 52,124 encapsulation
3rd, 4,5,6,7,8,145,148,150 pin
9th, 59 lead frame
10th, 60 semiconductor chip
11st, 12,53,55,75,76,128,129 source terminal
13rd, 14,57,58,73,74,126,127 gate terminal
15th, 61 IC chip
16th, 56 VDD terminal
17th, 54 VM terminals
18th, 19,20,21,22,62,63,64,65,66 plain conductor
2A, 2B, 52A, 52B, 10A, 10B, 10C are sideways
23、24、67、68、121、122 MOSFET
25th, 27,69,71,108,111,130,132 source electrode
26th, 28,34,70,72,109 gate electrode
31 drain electrodes
29 semiconductor substrates
A, b, c, d distance
E, f width
30 epitaxial layers
32 back gate regions
33 source regions
35 grid oxidation films
36 TEOS films
37 SiN films
38 PI films
39 UBM layers
40 insulating barriers
41st, 42 opening portion
43rd, 44 solder
45 insulating properties adhering films
60A central points
81 portable sets
82 secondary cells
83 protection circuit substrates
84 housings
85 2 pecked lines
101st, 146 resin-encapsulated
FET is used in 102 chargings
FET is used in 103 electric discharges
104 protection IC
105 dotted lines
106 lead frames
107 inside pins
110 wirings
123 installation portions
125 drain terminals
131st, 133 bond wire
141 silicons
142 source electrode pads
143 grid pads
144 die pads
147 aluminium strips
149 wires
P+, P-, B+, B- electrode
Embodiment
Hereinafter, it is the semiconductor device of the embodiment based on the drawing detailed description present invention.Also, implementing shape in explanation When state, identical component will use identical symbol in principle, and omit the part of repeat specification.
Fig. 1 is the in-built plan of encapsulation for illustrating semiconductor device.Fig. 2 (A) is illustrates to be built in semiconductor The plan of the semiconductor chip of device, Fig. 2 (B) is the section of the part in the line B-B direction of semiconductor chip shown in Fig. 2 (A) Figure.Fig. 3 (A) is the profile of the section in the line A-A direction for illustrating semiconductor device shown in Fig. 1, and Fig. 3 (B) is illustrates Fig. 1 institutes The profile of the change case of the section in the line A-A direction of the semiconductor device shown.
As shown in figure 1, in the semiconductor device 1 of this embodiment, it is from 2 sides of the encapsulation 2 shown in pecked line The construction of 2A, 2B toward 6 pins (pin) 3,4,5,6,7,8 of outside extraction.And, the size of encapsulation 2, for example paper X-direction The width of (long side direction of encapsulation) is 5mm, and the width of paper Y direction (short side direction of encapsulation) is 2mm.In addition, in this Embodiment, though semiconductor device 1 is illustrated with 6 pins, is not limited to this construction, or 8 pins or can fit Work as design for change.In addition, package dimension also can appropriate design for change.
Lead frame (or framework) 9 is to be made up of the metal of Cu or Fe-Ni alloy/C etc. and carry out Ni-Pd-Au etc. in surface Plating.Lead frame 9 has：With the source electrode of source electrode 25 and 27 (with reference to Fig. 2 (A)) institute's flip-chip packaged of semiconductor chip 10 Terminal 11 and 12；With the gate terminal 13 of the gate electrode 26 and 28 of semiconductor chip 10 (with reference to Fig. 2 (A)) institute's flip-chip packaged and 14；And through the VDD as power supply terminal that plain conductor 21 and 22 is connected with the electrode pads (not shown) of IC chip 15 Terminal 16 and VM terminals 17.
Source terminal 11 and 12 is divided in the middle section of encapsulation 2 along paper Y direction and each toward paper X-axis side To extension.Source terminal 11 and 12 and (with reference to Fig. 2 (the A)) flip-chip packaged of source electrode 25 and 27 of semiconductor chip 10 and fixation Most semiconductor chip 10, also plays the effect as die pad.
Then, it is used as source from source terminal 11 and 12 in the past outside part drawn of 2 sides 2A and 2B of encapsulation 2 The pin 4 and 7 of pole electrode.As illustrated, being formed as relatively wide using by the width of pin 4 and 7, to be reduced to distribution part Conduction resistance value, can also correspond to high current.
Gate terminal 13 and 14 is each toward the extension of paper X-direction from the paper upper left of encapsulation 2 or paper upper right.Gate terminal 13 and 14 with gate electrode 26,28 (referring now to Fig. 2 (A)) flip-chip packaged of semiconductor chip 10.In addition, from gate terminal 13 and 14 are used as the pin 3 and 6 of gate electrode in 2 sides 2A and 2B of encapsulation 2 toward the outside part drawn.
As illustrated, gate terminal 13 and 14 is extended and from 2 side 2A of encapsulation 2 along paper X-direction with linear And 2B is drawn.Then, plain conductor 18 and 19 extends from the electrode pads of IC chip 15 toward rough paper X-direction, and electrical Connect the gate terminal 13 and 14 between the end of semiconductor chip 10 and side 2A and 2B.
Based on this construction, just it is not required to consider the court of pin 3 and 6 of gate terminal 13 and 14 and gate electrode compared to partly leading The space that the end of body chip 10 extends closer to the outside of paper Y direction.Then, in paper Y direction, semiconductor The width of chip 10 can be made to maximize relative to the width of encapsulation 2 expands wide, and can prevent from resulting from the downsizing of chip size The deterioration of the element characteristic of semiconductor chip 10.In other words, the element characteristic of semiconductor chip 10 can be relative to the size for encapsulating 2 High performance to greatest extent.
In addition, the construction drawn using the formation of pin 3 to 8 from 2 side 2A and 2B of encapsulation 2, also make plain conductor 20, 21 and 22 can also extend from the electrode pads of IC chip 15 toward slightly paper X-direction.As illustrated, being electrically connected with IC chip 15 The summary X fonts of European characters are configured to the plain conductor 18 to 22 of semiconductor chip 10.In addition, between plain conductor 18 to 22 It can't intersect, the slimming of encapsulation 2 can be achieved.
As shown in Fig. 2 (A), 2 for example N channel type MOSFET 23 and 24 MOSFET is formed with semiconductor chip 10 23 and 24, respectively it is formed with source electrode 25 and 27 and gate electrode 26 and 28 in the interarea.For example MOSFET 23,24 is in paper Left and right directions is distinguished and configure, and the paper right side upper end that MOSFET 23 gate electrode 26 is configured in semiconductor chip 10 is attached Closely, MOSFET 24 gate electrode 28 is configured on the left of the paper of semiconductor chip 10 near upper end.
Sayed as described above using Fig. 1, though semiconductor chip 10 passes through to lead frame 9 (referring now to Fig. 1) flip-chip packaged Gate electrode 26 and 28 is configured near the both ends of paper X-direction of semiconductor chip 10, can be achieved to allow gate electrode to use Pin 3 and 6 (referring to Fig. 1) from 2 side 2A and 2B (referring now to Fig. 1) of 2 (referring to Fig. 1) of encapsulation toward the outside structure drawn Make.
Configured by above-mentioned pin, among paper Y direction, using allowing, the width formation of semiconductor chip 10 is relatively wide, Also so that the width of source electrode 25 and 27 may be alternatively formed to it is wider, in unit number (cell) the also shape of the formation of semiconductor chip 10 Into more.In addition, although the protection circuit substrate of secondary cell is configured in narrow in the portable set of smart mobile phone etc. Size is restricted in narrow space, but relative to protection circuit substrate, utilizes the MOSFET 23 and 24 increased as far as possible chi It is very little, the characteristic high performance of module can be made.
In addition, among each MOSFET 23 and 24, the side 10A and 10B of gate electrode 26 and 28 and semiconductor chip 10 Standoff distance a be shorter than the standoff distance b of gate electrode 26 and 28 and source electrode 25 and 27.
Constructed by this, as when semiconductor chip 10 by flip-chip packaged when lead frame 9, be difficult because welding allows grid Pole electrode 26,28 and source electrode 25,27 produce the construction of short circuit.Furthermore, half is configured at as far as possible using gate electrode 26,28 is allowed Near side 10A, 10B of conductor chip 10, source electrode 25,27, the conducting resistance that can be decreased on distribution are extensively configured Value, and then may correspond to high current.
It is identical it, the side 10C of gate electrode 26,28 and semiconductor chip 10 standoff distance c is shorter than source electrode 25th, the standoff distance d between 27.By the construction, in paper X-direction, formation is difficult because welding makes source electrode 25,27 Between produce short circuit construction.In addition, in paper Y direction, extensively configuring source electrode 25,27, can decreasing on distribution Conduction resistance value, and then may correspond to high current.
Also, as illustrated, the corner portion of source electrode 25,27 and gate electrode 26,28 is formed as curved.Institute as described above Speech, though semiconductor chip 10 by flip-chip packaged in lead frame 9, be created as making stress be difficult to concentrate on above-mentioned electricity in welding The construction in the corner portion of pole 25~28, and then realize and be difficult because scolding tin produces cracking etc. or the bad construction of encapsulation.
As shown in Fig. 2 (B), semiconductor chip 10 for example has the extension of N-type in storehouse on the semiconductor substrate 29 of N-type (epitaxial) layer 30,2 MOSFET23,24 are formed with semiconductor substrate 29 and epitaxial layer 30.MOSFET 23,24 is in half The middle section of conductor chip 10 forms certain standoff distance to electrically isolate, and is formed in the rear side of semiconductor substrate 29 There is common drain electrode 31.
Metal level of the drain electrode 31 based on aluminum or aluminum alloy is formed as stack structure, for example, with 10 μm To 20 μm of thickness, using the film thickness is increased, to be reduced to the conduction resistance value on distribution, and then high current may correspond to. In addition, current path can be shortened using common drain electrode 31, it can also increase start region based on highly integrated.
Back gate (back gate) region 32 of multiple p-types is formed with epitaxial layer 30, to the shape of back gate region 32 Into the source region 33 of N-type, the gate electrode 34 of intermediary's groove (trench), grid oxidation film 35.It is formed with epitaxial layer 30 Multiple units (cell) region of above-mentioned construction.In addition, for example forming TEOS films 36, SiN film 37, PI films above epitaxial layer 30 38 are used as insulating barrier.
In addition, above epitaxial layer 30, formed the source electrode 25,27 that is formed by the metal level of aluminum or aluminum alloy etc. and Gate electrode 26,28 (not shown).As shown in Fig. 2 (A), above-mentioned insulation layer segment is opening, allows source electrode 25,27 and grid Electrode 26,28 (not shown) can expose in the interarea side of semiconductor chip 10.Then, the source electrode 25,27 exposed with covering And the mode of gate electrode 26,28 (not shown) forms UBM layer 39.For example can be nickel-palladium-gold (Ni-Pd- as UBM layer 39 Au) layer.
As shown in Fig. 3 (A), insulating barrier 40 is allowed to be coated with the way of covering lead frame 9, opening portion 41,42 passes through etching It is formed on insulating barrier 40.The correspondence of opening portion 41,42 is configured at the source electrode 25,27 of semiconductor chip 10, opening portion 41,42 Shape it is similar to the shape of source electrode 25,27.Specifically, as shown in Fig. 2 (A), the shape of source electrode 25,27 is slightly The L fonts of European characters, the shape of opening portion 41,42 is also the L fonts of slightly European characters.
As illustrated, width f somewhat wide shape of the A/F e formation of opening portion 41,42 than source electrode 25,27 Shape.And, screen painting (screen printing) soldering paste, flip-chip packaged above the source terminal 11,12 of opening portion 41,42 Semiconductor chip 10, and (reflow) step that flowed back.In addition, it is possible to use elargol (silver paste) replaces weldering Cream.
By making above-mentioned A/F e wider than electrode width f, it may be such that the width in the side of lead frame 9 becomes larger, Semiconductor chip 10 is allowed to fix the hardening shape of solder 43,44 in the state of being stable on lead frame 9.And, using solder 43, 44 harden under stable shape, can suppress to produce due to the cracking produced by stress concentration in solder 43,44, and then prevent The phenomenon of bad connection.
Also, although not shown, but also form the opening portion corresponding to gate electrode 26,28, the opening shape in insulating barrier 40 Also it is similar to the shape of gate electrode 26,28, the shape as slightly larger than gate electrode 26,28.
IC chip 15 is fixed above the drain electrode 31 of semiconductor chip 10 through insulating properties adhering film 45.IC Chip 15 and semiconductor chip 10 are electrically insulated by insulating properties adhering film 45.In addition, the electrode pads of IC chip 15 are (not Diagram) and source terminal 11 be electrically connected with through plain conductor 20.Though also, the drain electrode 31 of semiconductor chip 10 exposes State, but plain conductor 20 is formed as not contacting with drain electrode 31.
Encapsulation 2, for example by sealing resin of epoxy series etc. come sealed guide frame 9, semiconductor chip 10, IC chip 15th, plain conductor 20 etc..As illustrated, source terminal 11,12 exposes from the rear side of encapsulation 2, the pin 4,7 of source electrode Drawn from side 2A, 2B of encapsulation 2 toward outside.
Sayed as described above, in semiconductor chip 10, the source electrode 25,27 for flowing through principal current is sealed for the upside-down mounting of lead frame 9 Dress, in the same manner, the drain electrode 31 for flowing through principal current each realizes reduction conducting resistance using the film thickness of metal level is increased Value.In addition, the control IC of the semiconductor chip 10 of IC chip 15, there is low current circulation between semiconductor chip 10 and IC chip 15. Therefore, the plain conductor 18-22 for the necessity for especially considering conduction resistance value using reducing.
Constructed by this, on semiconductor device 1, without using metal tape and conduction resistance value can be reduced, also can be because of drop Lower calorific value and realize high current or the consumption electric power of reduction.In addition, by the construction without using metal tape, can also realize envelope Fill the miniaturization of size.
Fig. 3 (B) represents the change case of the construction shown in Fig. 3 (A).As illustrated, insulating properties adhering film 45 is covered and partly led The whole face of drain electrode 31 of body chip 10, IC chip 15 is fixed in insulating properties adhering film 45.And, the electricity of IC chip 15 Polar cushion piece (not shown) and source terminal 11 are electrically connected with through plain conductor 20.
Now, after plain conductor 20 is connected to the electrode pads of IC chip 15 by ball bonding, once, sticked together in insulating properties Bent on film 45, and by stitch bond (stitch bonding) above source terminal 11.Constructed by this, it is possible to decrease Wire loop (wire loop) height of plain conductor 20, and then realize the filming of encapsulation 2.Also, no matter plain conductor 20 whether Be connected to insulating properties adhering film 45, under near insulating properties adhering film 45, can't allow source electrode 25 and drain electrode Electrode 31 produces short circuit.
Especially, as the encapsulation 2 on the protection circuit substrate for being packaged in secondary cell, paper is formed in wide cut In the encapsulation 2 of face X-direction, in order to avoid allowing plain conductor 20 to touch the end of drain electrode 31, shown in such as Fig. 3 (A), allow Tendency is to uprise at the top of the ring of plain conductor 20.So, utilize the shape shape of plain conductor 20 being made shown in Fig. 3 (B) Shape, you can at the top of the ring of reduction plain conductor 20, can be easily achieved the slimming of encapsulation 2.In addition, in response in the length of encapsulation 2 Degree, plain conductor 20 also can form annular ring shape above insulating properties adhering film 45 in multiple-contact mode.
Secondly, the construction of other inscapes shown in Fig. 3 (B) is identical with the construction that Fig. 3 (A) illustrated, in this, will save Omit its explanation.
In addition, in Fig. 3 (A) and Fig. 3 (B) explanation, although it is stated that being provided with opening portion 41,42 in insulating barrier 40 Situation, but this case is not limited to this situation.For example, without using insulating barrier 40, and the shape with opening portion 41,42 is formed Shape for same shape groove in lead frame 9, and then can prevent solder flow construction be also applicable.
In addition, though it is stated that situation wider than source electrode 25,27 width f the A/F e of opening portion 41,42, But this case is not limited to this situation.For example in the case that A/F e and width f are same widths, solder 43,44 is allowed Hardening be shaped as bucket shape, such a situation, which can also be realized, is difficult concentrated stress in the construction of solder.
Secondly, the lead frame of the change case as above-mentioned semiconductor device is described in detail based on Fig. 4 (A)-Fig. 4 (C) Other embodiments of shape and semiconductor chip.
Fig. 4 (A) illustrates the in-built plan in semiconductor device, and Fig. 4 (B) is illustrates to be built in Fig. 4 (A) institute The plan of the semiconductor chip of the semiconductor device shown.
As shown in Fig. 4 (A), the construction of semiconductor device 51 is formed as having from 2 of the encapsulation 52 shown in pecked line The source terminal 53,55 that side 52A, 52B expose；And expose VM terminals 54 as power supply terminal, VDD terminal 56.Secondly, Though 2 sides 52A, the 52B of gate terminal 57,58 not from encapsulation 52 expose, the back side dew (not shown) from encapsulation 52 is formed The construction gone out.
In addition, an each terminal 53-56 part is from the exposed surface exposed of encapsulation 52, be substantially formed as with side 52A, 52B is the same face, as the external pins being connected with external print and to be operated.In the same manner, the one of gate terminal 57,58 Part is from the exposed surface exposed of encapsulation 52, and the back side be substantially formed as with encapsulation 52 is the same face, using as with exterior view The external pins of case connection are simultaneously operated.
Encapsulation 52 size, for example in paper X-direction (long side direction of encapsulation) width be 5mm, in paper Y The width of direction of principal axis (short side direction of encapsulation) is 2mm.In addition, in this embodiment, though illustrated with 6 pins, This case is not limited to this construction, and it also can be 8 pins construction etc., and can appropriate design for change.
Lead frame 59 is made up of the metal of copper (Cu) or iron-nickel (Fe-Ni) alloy etc., and carries out nickel-palladium-in the surface The plating of golden (Ni-Pd-Au) etc..Lead frame 59 has：Fallen with the source electrode 69,71 (with reference to Fig. 4 (B)) of semiconductor chip 60 Fill the source terminal 53,55 of encapsulation；With the grid of gate electrode 70,72 (with reference to Fig. 4 (B)) flip-chip packaged of semiconductor chip 60 Terminal 57,58；And the VM terminals 54 that are connected with the electrode pads (not shown) of IC chip 16 through plain conductor 62,63 and VDD terminal 56.
Source terminal 53,55 is divided and past each paper X-direction in the middle section of encapsulation 52 along paper X-direction Extension.Source terminal 53,55 and the source electrode 69 of semiconductor chip 60,71 flip-chip packageds and fixed most semiconductor core Piece 60, also plays the effect as die pad.
Gate terminal 57,58 is configured at the paper upper left corner portion of encapsulation 52 nearby or near the corner portion of paper bottom right.Grid Gate electrode 70,72 flip-chip packageds of extreme son 57,58 and semiconductor chip 60.
Gate terminal 57,58, is for example the summary L fonts of European characters, and wherein to be configured at 2 sides 52A, 52B attached for one end Closely, a portion extends toward paper X-direction.Gate terminal 57,58 has than 60 closer 2 sides of semiconductor chip The region that 52A, 52B side are configured, and be electrically connected with for the region with plain conductor 64,65.
Constructed by this, in paper Y direction, the width of semiconductor chip 60 can be maximized to the width of encapsulation 52 Extension, and can prevent from resulting from the deterioration of the element characteristic of semiconductor chip 60 caused by the downsizing of chip size.Change speech It, the element characteristic of semiconductor chip 60, the size relative to encapsulation 52 can high performance to greatest extent.
In addition, as illustrated, the plain conductor 62-66 for being electrically connected with IC chip 61 and semiconductor chip 60 is configured to Europe The summary X fonts of character.And, it can't intersect between plain conductor 62-66, and the slimming of encapsulation 62 can be realized.
As shown in Fig. 4 (B), 2 for example N channel type MOSFET 67,68 MOSFET is formed with semiconductor chip 60 67th, 68, respectively it is formed with source electrode 69,71 and gate electrode 70,72 in its interarea.For example, MOSFET67,68 are above and below paper Direction is distinguished and configured, and MOSFET 67 gate electrode 70 is configured on the right side of the paper of semiconductor chip 60 near upper end, MOSFET 68 gate electrode 72 is configured on the left of the paper of semiconductor chip 60 near bottom.
As illustrated, on an interarea of semiconductor chip 60, source electrode 69,71 and gate electrode 70,72 relative to The central point 60A of semiconductor chip 60 is configured to rotationally symmetrical.Based on construction, when semiconductor chip 60 is in being packaged in lead frame When 59, rotated to even if from correct position 180 degree state and it is packed in the case of also can be in having in semiconductor chip 60 There is the MOSFET 67,68 of 2 N channel types, without breaking down, and then improve by improper the influenceed yield of encapsulation.
In addition, source electrode 69,71 can in extensively being formed in paper X-direction, between MOSFET67,68 to region Also can extensively it be formed.Constructed by this, the current path in semiconductor chip 60 can be shortened, can also increase connecing for current flowing Area is closed, and then improves the on-resistance characteristics of semiconductor chip 60.
In addition, the protection circuit substrate of secondary cell, although in order to be configured in the portable set of smart mobile phone etc. Interior narrow space and size has been limited, but relative to the protection circuit substrate, increase MOSFET as far as possible can be passed through 67th, 68 size, enables the characteristic high performance of module.
Other, make each electrode 69-72 corner portion be formed as curved construction or based on the phase between each electrode 69-72 Gauge is identical with the semiconductor chip 10 described in above-listed use Fig. 1 and Fig. 2 from produced effect, referring now to its explanation, in this Then the description thereof will be omitted.
In addition, lead frame shape that also can be as shown in Fig. 4 (C), makes gate terminal 73,74 and the formation of source terminal 75,76 The situation for revoking (Hanger pin) shape is also applicable.
Secondly, Fig. 5 (A) be the secondary cell and secondary cell for the housing for illustrate to be incorporated in portable set protection it is electric The oblique view of base board, Fig. 5 (B) is the protection circuit figure for illustrating to be formed on protection circuit substrate, and Fig. 5 (C) and Fig. 5 (D) are used To illustrate the general view of the protection circuit substrate shown in Fig. 5 (A).Also, in Fig. 5 (C) and Fig. 5 (D), protection circuit pattern Simplify diagram.
The secondary electricity that the portable set 18 of mobile phone or smart mobile phone as shown in Fig. 5 (A) etc. passes through lithium battery etc. Power supply is supplied in pond 82, and secondary cell 82 charges through protection circuit substrate 83 from external power source.Protection circuit substrate 83 is A kind of substrate for being used for carrying out the battery management of the discharge and recharge of secondary cell 82.
In recent years, with the miniaturization or slimming of portable set 81, secondary cell 82 or protection circuit substrate 83 Minimize or be thinned therewith.As illustrated, for example, the housing 84 of portable set 81 is formed as in paper Z-direction The length of (long side direction of lead frame) is 150mm degree, is in the length of paper X-direction (short side direction of lead frame) 80mm degree, in the relatively thin cuboid shape that the thickness of paper Y direction (thickness direction of lead frame) is 7mm degree.In addition, If when the thickness of housing 84 is in the case of 7mm degree, being incorporated in its internal electronic unit in paper Y direction Width must be formed as the width of 4mm degree.
Shown in protection circuit shown in Fig. 5 (B), such as Fig. 5 (C) and Fig. 5 (D), the positive and negative of protection circuit substrate 83 is used To be formed.And, P+ and P- be be arranged at the housing 84 of portable set 81+electrode that is connected of electrode and-electrode, and B+ and B- represent with secondary cell 82+electrode that is connected of electrode and-electrode.It is formed at the circuit shown in two pecked lines 85 using figure The circuit in encapsulation 2,52 that 1- Fig. 4 (C) illustrated.
As Fig. 5 (C) and Fig. 5 (D) protection circuit substrate 83, in order to by side by side in paper X/Y plane in the way of be configured at shell In body 84, the width in paper Y direction is 3mm degree, forms the substrate of the wide cut in paper X-direction.In addition, although In Fig. 5 (C) displays from plane seen by the side of secondary cell 82, said in being packaged with the distribution of the protection circuit using Fig. 1-Fig. 4 Bright encapsulation 2,52.Also, Fig. 5 (D) represents the plane of the rear side of the protection circuit substrate 83 shown in Fig. 5 (C).
Sayed as described above using Fig. 1 and Fig. 4, encapsulation 2,52 is formed as shorter and in paper X-direction in paper Y direction Longer shape.As shown in Fig. 5 (C), width of the encapsulation 2,52 relative to the thickness direction (paper Y direction) due to housing 84 And limited protection circuit substrate 83 is packaged.And, sayed as described above using Fig. 2 (A) and Fig. 4 (B), semiconductor chip 10, The width of 60 paper Y direction, can largo be configured as far as possible relative to the width of the paper Y direction of encapsulation 2,52.
In other words, though encapsulation 2,52 especially limits the width in paper Y direction, lead frame 9,59 is utilized The design of layout or the layout of electrode of MOSFET23,24,67,68 etc., can maximize the size of semiconductor chip 10,60, And then realization is used as the high performance of module.
Furthermore, sayed as described above using Fig. 1, MOSFET 23 pin 3,4 and the pin 5 of VDD terminal 16 are from encapsulation 2 Side 2A sides are drawn, and MOSFET 24 pin 6,7 and the pin 8 of VM terminals 17 are drawn from the side 2B sides of encapsulation 2.Based on this Packaging structure, although non-schema is configured in paper in all distributions on protection circuit substrate 83 with the pin 3-8 distributions being connected Face X-direction, and the distribution that is connected with pin 3-8 need not be set in the upper and lower sides of encapsulation 2 of paper Y direction.In addition, encapsulation 2 Can be relative to protection circuit substrate 83 in paper Y direction shorter and efficiently encapsulated in longer in paper X-direction. In addition, also identical for the encapsulation 52 illustrated using Fig. 4 (A).
Also, in this embodiment, although illustrate side 2A, 2B from encapsulation 2 toward the outside situation for drawing pin 3-8, But it is not limited to such a situation.For example, it is also possible to be that pin 3-8 is formed as with 2 sides of encapsulation being phase the same face, and it is not past The encapsulation situation for the non-connection pin type that outside is drawn.
In addition, though explanation just tossing about and expose the source terminal 11,12 of lead frame 9 from encapsulation 2, gate terminal 13,14, The situation of VDD terminal 16 and VM terminals 17, but it is not limited to this situation.For example, being covered by sealing resin until upper Untill the rear side for stating terminal, and the pin 3-8 of side 2A, 2B extraction from encapsulation 2 is allowed for example to be processed into the gull wing (Gull- Wing) shape, the situation for being packaged in the distribution of protection circuit substrate is also applicable.In addition, without departing from the ancestor of the present invention In the range of purport, various changes can be also carried out.

Claims (7)

1. a kind of semiconductor device, it is characterised in that include：
One framework；
Semiconductor chip, one interarea is by flip-chip packaged on the framework；
One IC chip, storehouse and is fixed on another interarea relative with the interarea of the semiconductor chip；
Plain conductor, for being electrically connected with the semiconductor chip and the IC chip；And
One encapsulation, seals the framework, the semiconductor chip, the IC chip and the plain conductor,
Wherein, the encapsulation has in two relative sides of the long side direction,
In the semiconductor chip one the first transistor of formation and a transistor seconds, first crystalline substance of the interarea side is formed on The gate electrode of body pipe is configured in the side side on wherein one side of the encapsulation, and be formed on the interarea side this The gate electrode of two-transistor is configured in the side side of the another side of the encapsulation.
2. semiconductor device as claimed in claim 1, it is characterised in that the gate electrode institute flip-chip packaged of the first transistor The framework extend in the long side direction, and this from wherein one side of the encapsulation exposes sideways, and the grid of the transistor seconds The framework of pole electrode institute flip-chip packaged extends in the long side direction, and this from the another side of the encapsulation exposes sideways.
3. semiconductor device as claimed in claim 1 or 2, it is characterised in that the gate electrode with the first transistor is electrical The plain conductor of connection, the frame between the side on the gate electrode of the first transistor and wherein one side of the encapsulation Frame is connected；
The plain conductor being electrically connected with the gate electrode of the transistor seconds, be with the gate electrode of the transistor seconds and Framework connection between the side of the another side of the encapsulation.
4. semiconductor device as claimed in claim 1 or 2, it is characterised in that the semiconductor chip has：It is formed at the interarea The source electrode of the first transistor of side；It is formed at the source electrode of the transistor seconds of the interarea side；And shape Into the first transistor and the common drain electrode of the transistor seconds in another interarea side,
The framework of the source electrode institute flip-chip packaged of the first transistor exposes sideways from this of wherein one side of the encapsulation；Should The framework of the source electrode institute flip-chip packaged of transistor seconds exposes sideways from this of the another side of the encapsulation.
5. semiconductor device as claimed in claim 3, it is characterised in that the semiconductor chip has：It is formed at the interarea one The source electrode of the first transistor of side；It is formed at the source electrode of the transistor seconds of the interarea side；And formed The first transistor and the common drain electrode of the transistor seconds in another interarea side,
The framework of the source electrode institute flip-chip packaged of the first transistor exposes sideways from this of wherein one side of the encapsulation；Should The framework of the source electrode institute flip-chip packaged of transistor seconds exposes sideways from this of the another side of the encapsulation.
6. semiconductor device as claimed in claim 1, it is characterised in that include：With the gate electrode of the first transistor simultaneously The source electrode for the first transistor arranged and be configured on the long side direction of the semiconductor chip；And with second crystal The gate electrode of pipe is configured at the source electrode of the transistor seconds on the long side direction of the semiconductor chip side by side,
The gate electrode of the first transistor is relative with source electrode with the gate electrode of source electrode and the transistor seconds It is configured in a central point of the semiconductor chip rotationally symmetrical.
7. a kind of portable set, is installed just like right on a protection circuit substrate of a secondary cell of the portable set It is required that the encapsulation of the semiconductor device described in 1 to 6 any one, it is characterised in that
Long side direction configuration of the long side direction of the encapsulation along the protection circuit substrate,
Thickness direction configuration of one short side direction of the protection circuit substrate along a housing of the portable set.
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