CN106252320B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN106252320B
CN106252320B CN201610404477.5A CN201610404477A CN106252320B CN 106252320 B CN106252320 B CN 106252320B CN 201610404477 A CN201610404477 A CN 201610404477A CN 106252320 B CN106252320 B CN 106252320B
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lead frame
terminal
electrode
main surface
disposed
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CN106252320A (zh
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渡边莊太
降旗博明
今井诚
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

本发明提供一种即使将二极管与MOSFET或IGBT搭载于同一封装件，也可以提高散热性的半导体装置。配置于MOSFET芯片(2)的背面的漏电极(2c)通过焊料连接在第二引线框(4)的上表面，配置于二极管芯片(1)的背面的阴极电极(1c)通过焊料连接在第一引线框(3)的上表面。将第一引线框(3)和第二引线框(4)的未连接二极管芯片(1)和MOSFET芯片(2)的背面配置为从密封树脂(9)露出。

Description

半导体装置
技术领域
本发明涉及一种组装于电力电路的半导体装置。
背景技术
组装于电力电路的如图15所示的在PFC(Power Factor Correction/PowerFactor Controller：功率因数校正/功率因素控制器)电路和/或斩波电路使用的二极管与MOSFET(Metal Oxide Semiconductor Field Effect Transistor：绝缘栅型场效应晶体管)或IGBT(Insulated Gate Bipolar Transistor：绝缘栅型双极晶体管)分别以单独的封装件安装于基板。
在二极管与MOSFET或IGBT为分立式封装件的情况下，冷却片被分别安装在各自封装件的背面侧进行散热。另外，在二极管与MOSFET或IGBT为表面安装件(SMD：SurfaceMount Device)的情况下，将各自的背面安装于基板进行散热。
如图16所示，在二极管元件301和MOSFET元件401为分立式封装件的情况下，需要安装各封装件的空间，还需要安装冷却片。另外，因为由形成于基板的布线图案500连接二极管元件301的阳极端子303和MOSFET元件401的漏极端子403(在IGBT元件的情况下为集电极端子)，因此产生由布线图案500引起的电感(以下称为布线电感)，在进行开关动作时，由布线电感导致产生尖峰电压。因此，需要选择额定电压为尖峰电压以上的二极管与MOSFET或IGBT。
作为减小安装空间的方法，具有将二极管与MOSFET或IGBT搭载于同一封装件的半导体装置(例如，专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开第2007-294669号
发明内容
技术问题
然而，仅将二极管与MOSFET或IGBT搭载于同一封装件，导致散热不充分，半导体装置可能因热而损坏。
本发明提供一种即使将二极管与MOSFET或IGBT搭载于同一封装件，也能够提高散热性的半导体装置。
技术方案
本发明的实施方式中的半导体装置，其特征在于，在具有第一引线框和第二引线框的半导体装置中，在上述第一引线框具备第一端子，在上述第二引线框具备第二端子，在上述第一引线框的一侧的主面上具备第一半导体芯片，在上述第二引线框的一侧的主面上具备第二半导体芯片，配置于上述第一半导体芯片的正面的第一电极通过键合线电连接于上述第二引线框的上述一侧的主面上，在上述第二半导体芯片的正面具有第二电极和第三电极，上述第二电极通过键合线与第三端子以及第四端子电连接，上述第三电极通过键合线与第五端子电连接，将上述第一引线框的另一侧的主面与上述第二引线框的另一侧的主面配置为从密封树脂露出。
另外，也可以为上述第一电极通过键合线与第三引线框的一侧的主面连接，上述第三引线框的上述一侧的主面通过键合线与上述第一引线框的上述一侧的主面连接，上述第三引线框的另一侧的主面从上述密封树脂露出。
另外，本发明的实施方式中的半导体装置还可以为具有以下特征，在具有第四引线框和第五引线框的半导体装置中，在上述第四引线框具有第六端子，在上述第五引线框具有第七端子，在上述第四引线框的一侧的主面上具有第三半导体芯片，在上述第五引线框的一侧的主面上具有第四半导体芯片和第五半导体芯片，配置于上述第三半导体芯片的正面的第四电极通过键合线电连接在上述第五引线框的上述一侧的主面上，在上述第四半导体芯片的正面具有第五电极和第六电极，在上述第五半导体芯片的正面具有第七电极，上述第五电极通过键合线与第八端子和第九端子电连接，上述第六电极通过键合线与第十端子电连接，上述第七电极通过键合线与上述第五电极电连接，将上述第四引线框的另一侧的主面和上述第五引线框的另一侧的主面配置为从密封树脂露出。
另外，上述第四电极通过键合线与第六引线框的一侧的主面连接，上述第六引线框的上述一侧的主面通过键合线与上述第五引线框的上述一侧的主面连接，上述第六引线框的另一侧的主面从上述密封树脂露出。
发明效果
本发明提供一种即使将二极管与MOSFET或IGBT搭载于同一封装件，也能够使散热性提高的半导体装置。
附图说明
图1是示出本发明的实施方式一的图。
图2是示出本发明的实施方式二的图。
图3是示出本发明的实施方式三的图。
图4是示出本发明的实施方式四的图。
图5是示出本发明的实施方式五的图。
图6是示出本发明的实施方式六的图。
图7是示出本发明的实施方式七的图。
图8是示出本发明的实施方式八的图。
图9是示出本发明的实施方式九的图。
图10是示出本发明的实施方式十的图。
图11是示出本发明的实施方式十一的图。
图12是示出本发明的实施方式十二的图。
图13是示出本发明的实施方式十三的图。
图14是示出本发明的实施方式十四的图。
图15是示出PFC电路的一例的图。
图16是示出现有技术的图。
符号说明
1、1-1、1-2：二极管芯片
1a、1a-1、1a-2：阳极电极
1b、1b-1、1b-2：阴极电极
2：MOSFET芯片
2a：栅电极
2b：源电极
2c：漏电极
3、23、25、33、43、53、63、73：第一引线框
4、24、26、34、44、54、64、74：第二引线框
5、45、55：第三引线框
6：键合线
7：IGBT芯片
7a：栅电极
7b：发射电极
7c：集电极
8：FWD芯片
8a：阳极电极
8b：阴极电极
9：密封树脂
11、11-1、11-2：阴极端子
12、12-1、12-2：阳极端子
13、13-1：漏极端子
14、14a、14b、14a-1、14b-1：源极端子
15、15-1：栅极端子
16、16-1：集电极端子
17、17a、17b、17a-1、17b-1：发射极端子
18：贯穿孔
20：基板
21：布线图案
201：二极管
202：MOSFET
301：二极管元件
302：阴极端子
303：阳极端子
401：MOSFET元件
402：栅极端子
403：漏极端子
404：源极端子
500：布线图案
具体实施方式
以下，通过发明的实施方式对本发明进行说明，但以下的实施方式并不对权利要求书的发明进行限定。另外，在实施方式中所说明的全部的特征组合对于发明的技术方案来说并非必须。
实施方式一
图1示出实施方式一。图1的(a)示出俯视图(上表面的密封树脂未图示)，图1的(b)示出图1的(a)的A-A’线位置的剖面图，图1的(c)示出后视图。
配置于二极管芯片1的背面的阴极电极1b通过焊料(未图示)连接在第一引线框3的上表面。
配置于MOSFET芯片2的背面的漏电极2c通过焊料(未图示)连接在第二引线框4的上表面。
在第一引线框3配置有阴极端子11，在第二引线框4配置有漏极端子13。
配置于二极管芯片1的正面的阳极电极1a通过键合线6与第二引线框4连接，并与MOSFET芯片2的漏电极2c电连接。
配置于MOSFET芯片2的正面的栅电极2a通过键合线6与栅极端子15电连接。
配置于MOSFET芯片2的正面的源电极2b通过键合线6与源极端子14a、14b电连接。
将未配置二极管芯片1和MOSFET芯片2的第一引线框3的背面和第二引线框4的背面配置为从密封树脂9露出。
阴极端子11、漏极端子13、源极端子14a、源极端子14b和栅极端子15以相邻的方式配置，并从密封树脂9露出。
通过将二极管芯片1和MOSFET芯片2搭载于同一封装件，从而能够在封装件内部将二极管芯片1的阳极电极1a与MOSFET芯片2的漏电极2c电连接。由此，能够降低由布线图案引起的电感(以下称为布线电感)，抑制在进行开关动作时由布线电感引起的尖峰电压。
另外，通过将第一引线框3的背面和第二引线框4的背面配置为从密封树脂9露出而成为分立式封装件，能够提高散热性。
在实施方式一中示出了将二极管芯片1和MOSFET芯片2搭载于同一封装件的例子，但也可以将MOSFET芯片2替换为IGBT芯片7。
实施方式二
图2示出实施方式二。图2的(a)示出俯视图(上表面的密封树脂未图示)，图2的(b)示出图2的(a)的B-B’线位置的剖面图，图2的(c)示出后视图。
配置于二极管芯片1的背面的阴极电极1b通过焊料(未图示)连接在第一引线框3的上表面。
配置于IGBT芯片7的背面的集电极7c和配置于FWD(Free Wheeling Diode：续流二极管)芯片8的背面的阴极电极8b通过焊料(未图示)连接在第二引线框4的上表面，集电极7c和阴极电极8b电连接。
在第一引线框3配置有阴极端子11，在第二引线框4配置有集电极端子16。
配置于二极管芯片1的正面的阳极电极1a通过键合线6与第二引线框4连接，并与IGBT芯片7的集电极7c电连接。
配置于FWD芯片8的正面的阳极电极8a通过键合线6与配置于IGBT芯片7的表面的发射电极7b电连接。
配置于IGBT芯片7的正面的栅电极7a通过键合线6与栅极端子15电连接。
配置于IGBT芯片7的正面的发射电极7b通过键合线6与发射极端子17a、17b电连接。
将未配置二极管芯片1和IGBT芯片7的第一引线框3的背面和第二引线框4的背面配置为从密封树脂9露出。
阴极端子11、集电极端子16、发射极端子17a、发射极端子17b和栅极端子15以相邻的方式配置，并从密封树脂9露出。
通过将二极管芯片1、IGBT芯片7和FWD芯片8搭载于同一封装件，从而能够在封装件内部将二极管芯片1的阳极电极1a与IGBT芯片7的集电极7c电连接。由此，能够降低由布线图案引起的电感(以下称为布线电感)，抑制在进行开关动作时由布线电感引起的尖峰电压。
另外，通过将FWD芯片8搭载于相同的封装件，能够省去基板内的布线图案，能够实现节约空间。
另外，通过将第一引线框3的背面和第二引线框4的背面配置为从密封树脂9露出而成为分立式封装件，能够提高散热性。
实施方式三
图3示出实施方式三。图3的(a)示出俯视图(上表面的密封树脂未图示)，图3的(b)示出图3的(a)的C-C’线位置的剖面图，图3的(c)示出后视图。
实施方式三是在实施方式一中，在第一引线框23和第二引线框24之间具备用于固定冷却片的贯穿孔18。
由于能够通过具备贯穿孔18来安装冷却片，因此能够进一步提高冷却効率。
实施方式四
图4示出实施方式四。图4的(a)示出俯视图(上表面的密封树脂未图示)，图4的(b)示出图4的(a)的D-D’线位置的剖面图，图4的(c)示出后视图。
本实施方式与实施方式一的不同之处在于具备第三引线框5。
配置于二极管芯片1的背面的阴极电极1b通过焊料(未图示)连接在第一引线框25的上表面。
配置于MOSFET芯片2的背面的漏电极2c通过焊料(未图示)连接在第二引线框26的上表面。
在第一引线框25配置有阴极端子11，在第二引线框26配置有漏极端子13。
配置于二极管芯片1的正面的阳极电极1a通过键合线6与第三引线框5连接。另外，第三引线框5和第二引线框26通过键合线6连接。因此，配置于二极管芯片1的正面的阳极电极1a通过第三引线框5与MOSFET芯片2的漏电极2c电连接。
配置于MOSFET芯片2的正面的栅电极2a通过键合线6与栅极端子15电连接。
配置于MOSFET芯片2的正面的源电极2b通过键合线6与源极端子14a、14b电连接。
将未配置二极管芯片1和MOSFET芯片2的第一引线框25的背面、第二引线框26的背面以及第三引线框5的背面配置为从密封树脂9露出。
通过露出第三引线框5的背面，与实施方式一相比，能够提高散热性。
在实施方式四中，示出了将二极管芯片1和MOSFET芯片2搭载于同一封装件的例子，但也可以与实施方式一相同地，将MOSFET芯片2替换为IGBT芯片7。
实施方式五
图5示出实施方式五。图5的(a)示出俯视图(上表面的密封树脂未图示)，图5的(b)示出图5的(a)的E-E’线位置的剖面图，图5的(c)示出后视图。
本实施方式与实施方式二的不同之处在于具备第三引线框5。
配置于二极管芯片1的背面的阴极电极1b通过焊料(未图示)连接在第一引线框25的上表面。
配置于IGBT芯片7的背面的集电极7c和配置于FWD(Free Wheeling Diode：续流二极管)芯片8的背面的阴极电极8b通过焊料(未图示)连接，集电极7c与阴极电极8b电连接。
在第一引线框25配置有阴极端子11，在第二引线框26配置有集电极端子16。
配置于二极管芯片1的正面的阳极电极1a通过键合线6与第三引线框5连接。另外，第三引线框5与第二引线框26通过键合线6连接。因此，配置于二极管芯片1的正面的阳极电极1a通过第三引线框5与IGBT芯片7的集电极7c电连接。
配置于FWD芯片8的正面的阳极电极8a通过键合线6与配置于IGBT芯片7的正面的发射电极7b电连接。
配置于IGBT芯片7的正面的栅电极7a通过键合线6与栅极端子15电连接。
配置于IGBT芯片7的正面的发射电极7b通过键合线6与发射极端子17a、17b电连接。
将未配置二极管芯片1和IGBT芯片7的第一引线框25的背面、第二引线框26的背面以及第三引线框5的背面配置为从密封树脂9露出。
通过露出第三引线框5的背面，与实施方式二相比，能够提高散热性。
实施方式六
图6示出实施方式六。图6的(a)示出俯视图(上表面的密封树脂未图示)，图6的(b)示出图6的(a)的F-F’线位置的剖面图，图6的(c)示出后视图，图6的(d)示出与基板的连接图。
配置于二极管芯片1的背面的阴极电极1b通过焊料(未图示)连接在第一引线框33的上表面。
配置于MOSFET芯片2的背面的漏电极2c通过焊料(未图示)连接在第二引线框34的上表面。
在第二引线框34配置有漏极端子13。
配置于二极管芯片1的正面的阳极电极1a通过键合线6与第二引线框34连接，而与MOSFET芯片2的漏电极2c电连接。
配置于MOSFET芯片2的正面的栅电极2a通过键合线6与栅极端子15电连接。
配置于MOSFET芯片2的正面的源电极2b通过键合线6与源极端子14a、14b电连接。
将未配置二极管芯片1和MOSFET芯片2的第一引线框33的背面和第二引线框34的背面配置为从密封树脂9露出。
漏极端子13、源极端子14a、源极端子14b和栅极端子15以相邻的方式配置，成为表面安装件(SMD：Surface Mount Device)的形状。
通过将二极管芯片1和MOSFET芯片2搭载于同一封装件，能够使二极管芯片1的阳极电极1a与MOSFET芯片2的漏电极2c在封装件内部电连接。由此，能够降低由布线图案引起的电感(以下称为布线电感)，抑制在进行开关动作时由布线电感引起的尖峰电压。
上述封装件(半导体装置)通过焊料(未图示)与配置于基板20上的布线图案21电连接。
通过使第一引线框33的背面与布线图案21连接，从而由二极管芯片1的阴极电极1b构成PFC电路等电力电路。
由此，将未配置二极管芯片1和MOSFET芯片2的第一引线框33的背面和第二引线框34的背面与基板连接，能够提高散热性。
在实施方式六中，示出了将二极管芯片1和MOSFET芯片2搭载于同一封装件的例子，但也可以将MOSFET芯片2替换为IGBT芯片7。
实施方式七
在图7示出实施方式七。图7的(a)示出俯视图(上表面的密封树脂未图示)，图7的(b)示出图7的(a)的G-G’线位置的剖面图，图7的(c)示出后视图，图7的(d)示出与基板的连接图。
配置于二极管芯片1的背面的阴极电极1b通过焊料(未图示)连接在第一引线框33的上表面。
配置于IGBT芯片7的背面的集电极7c与配置于FWD(Free Wheeling Diode：续流二极管)芯片8的背面的阴极电极8b通过焊料(未图示)连接在第二引线框34的上表面，集电极7c与阴极电极8b电连接。
在第二引线框34配置有集电极端子16。
配置于二极管芯片1的正面的阳极电极1a通过键合线6与第二引线框34连接，而与IGBT芯片7的集电极7c电连接。
配置于FWD芯片8的正面的阳极电极8a通过键合线6与配置于IGBT芯片7的正面的发射电极7b电连接。
配置于IGBT芯片7的正面的栅电极7a通过键合线6与栅极端子15电连接。
配置于IGBT芯片7的正面的发射电极7b通过键合线6与发射极端子17a、17b电连接。
将未配置二极管芯片1和IGBT芯片7的第一引线框33的背面和第二引线框34的背面配置为从密封树脂9露出。
集电极端子16、发射极端子17a、发射极端子17b和栅极端子15以相邻的方式配置，设置为表面安装件(SMD：Surface Mount Device)的形状。
通过将二极管芯片1、IGBT芯片7以及FWD芯片8搭载于同一封装件，从而能够使二极管芯片1的阳极电极1a与IGBT芯片7的集电极7c在封装件内部电连接。由此，能够降低由布线图案引起的电感(以下称为布线电感)，抑制在进行开关动作时由布线电感引起的尖峰电压。
另外，通过将FWD芯片8搭载于相同的封装件，从而能够省去基板内的布线图案，能够实现节约空间。
上述封装件(半导体装置)通过焊料(未图示)与配置于基板20上的布线图案21电连接。
通过使第一引线框33的背面与布线图案21连接，从而由二极管芯片1的阴极电极1b构成PFC电路等电力电路。
由此，将未配置二极管芯片1和MOSFET芯片的第一引线框33的背面和第二引线框34的背面与基板20连接，能够提高散热性。
实施方式八
在图8示出实施方式八。图8的(a)示出俯视图(上表面的密封树脂未图示)，图8的(b)示出图8的(a)的H-H’线位置的剖面图，图8的(c)示出后视图，图8的(d)示出与基板的连接图。
配置于二极管芯片1-1的背面的阴极电极1b-1通过焊料(未图示)连接在第一引线框33的上表面。
配置于二极管芯片1-2的背面的阴极电极1b-2通过焊料(未图示)连接在第二引线框34的上表面。
在第二引线框34配置有阴极端子11。
配置于二极管芯片1-1的正面的阳极电极1a-1通过键合线6与第二引线框34连接，而与二极管芯片1-2的阴极电极1b-2电连接。
配置于二极管芯片1-2的表面的阳极电极1a-2通过键合线6与阳极端子12电连接。
将未配置二极管芯片1-1、1-2的第一引线框33的背面和第二引线框34的背面配置为从密封树脂9露出。
阴极端子11和阳极端子12以相邻的方式配置，设置为表面安装件(SMD：SurfaceMount Device)的形状。
通过将二极管芯片1-1、1-2配置于同一封装件，从而能够使二极管芯片1-1的阳极电极1a-1与二极管芯片1-2的阴极电极1b-2在封装件内部电连接。
上述封装件(半导体装置)通过焊料(未图示)与配置于基板20上的布线图案21电连接。由此，能够省去基板内的布线图案，能够实现节约空间。
通过使第一引线框33的背面与布线图案21连接，从而由二极管芯片1的阴极电极1b构成PFC电路等电力电路。
由此，将未配置二极管芯片1-1、1-2的第一引线框33的背面和第二引线框34的背面与基板连接，能够提高散热性。
实施方式九
在图9示出实施方式九。图9的(a)示出俯视图(上表面的密封树脂未图示)，图9的(b)示出图9的(a)的I-I’线位置的剖面图，图9的(c)示出后视图，图9的(d)示出与基板的连接图。
本实施方式与实施方式六的不同之处在于具备第三引线框45。
配置于二极管芯片1的背面的阴极电极1b通过焊料(未图示)连接在第一引线框43的上表面。
配置于MOSFET芯片2的背面的漏电极2c通过焊料(未图示)连接在第二引线框44的上表面。
在第二引线框44配置有漏极端子13。
配置于二极管芯片1的正面的阳极电极1a通过键合线6与第三引线框45连接。另外，第三引线框45与第二引线框44通过键合线6连接。由此，配置于二极管芯片1的正面的阳极电极1a通过第三引线框45与MOSFET芯片2的漏电极2c电连接。
配置于MOSFET芯片2的正面的栅电极2a通过键合线6与栅极端子15电连接。
配置于MOSFET芯片2的正面的源电极2b通过键合线6与源极端子14a、14b电连接。
将未配置二极管芯片1和MOSFET芯片2的第一引线框43的背面、第二引线框44的背面以及第三引线框45的背面配置为从密封树脂9露出。
漏极端子13、源极端子14a、源极端子14b和栅极端子15以相邻的方式配置，设置为表面安装件(SMD：Surface Mount Device)的形状。
通过露出第三引线框45的背面，与实施方式六相比，能够提高散热性。
在实施方式九中，示出了将二极管芯片1和MOSFET芯片2搭载于同一封装件的例子，但也可以将MOSFET芯片2替换为IGBT芯片7。
实施方式十
在图10示出实施方式十。图10的(a)示出俯视图(上表面的密封树脂未图示)，图10的(b)示出图10的(a)的J-J’线位置的剖面图，图10的(c)示出后视图，图10的(d)示出与基板的连接图。
本实施方式与实施方式七的不同之处在于具备第三引线框45。
配置于二极管芯片1的背面的阴极电极1b通过焊料(未图示)连接在第一引线框43的上表面。
配置于IGBT芯片7的背面的集电极7c和配置于FWD(Free Wheeling Diode：续流二极管)芯片8的背面的阴极电极8b通过焊料(未图示)连接在第二引线框44的上表面，集电极7c与阴极电极8b电连接。
在第二引线框44配置有集电极端子16。
配置于二极管芯片1的正面的阳极电极1a通过键合线6与第三引线框45连接。另外，第三引线框45与第二引线框44通过键合线6连接。由此，配置于二极管芯片1的正面的阳极电极1a通过第三引线框45与IGBT芯片7的集电极7c电连接。
配置于FWD芯片8的正面的阳极电极8a通过键合线6与配置于IGBT芯片7的正面的发射电极7b电连接。
配置于IGBT芯片7的正面的栅电极7a通过键合线6与栅极端子15电连接。
配置于IGBT芯片7的正面的发射电极7b通过键合线6与发射极端子17a、17b电连接。
将未配置二极管芯片1和IGBT芯片7的第一引线框43的背面、第二引线框44的背面以及第三引线框45的背面配置为从密封树脂9露出。
集电极端子16、发射极端子17a、发射极端子17b和栅极端子15以相邻的方式配置，设置为表面安装件(SMD：Surface Mount Device)的形状。
通过露出第三引线框45的背面，与实施方式六相比，能够提高散热性。
实施方式十一
在图11示出实施方式十一。图11的(a)示出俯视图(上表面的密封树脂未图示)，图11的(b)示出图11的(a)的K-K’线位置的剖面图，图11的(c)示出后视图，图11的(d)示出与基板的连接图。
本实施方式与实施方式六的不同之处在于，漏极端子13-1、源极端子14a-1、源极端子14b-1、栅极端子15-1的各端子从密封树脂9以与第一引线框53的背面和第二引线框54的背面露出于同一平面。
实施方式十一能够获得与实施方式六相同的效果。
另外，同样地，也可以使实施方式七的集电极端子16、发射极端子17a、发射极端子17b、栅极端子15从密封树脂9以与第一引线框33的背面和第二引线框34的背面露出于同一平面。
实施方式十二
在图12示出实施方式十二。图12的(a)示出俯视图(上表面的密封树脂未图示)，图12的(b)示出图12的(a)的L-L’线位置的剖面图，图12的(c)示出后视图，图12的(d)示出与基板的连接图。
本实施方式与实施方式十的不同之处在于，集电极端子16-1、发射极端子17a-1、发射极端子17b-1、栅极端子15-1的各端子从密封树脂9以与第一引线框53的背面和第二引线框54的背面露出于同一平面。
实施方式十二能够获得与实施方式十相同的效果。
另外，同样地，也可以使实施方式九的漏极端子13、源极端子14a、源极端子14b、栅极端子15从密封树脂9以与第一引线框43的背面和第二引线框44的背面露出于同一平面。
实施方式十三
在图13示出实施方式十三。图13的(a)示出俯视图(上表面的密封树脂未图示)，图13的(b)示出图13的(a)的M-M’线位置的剖面图，图13的(c)示出后视图，图13的(d)示出与基板的连接图。
配置于二极管芯片1-1的背面的阴极电极1b-1通过焊料(未图示)连接在第一引线框63的上表面。
配置于二极管芯片1-2的背面的阴极电极1b-2通过焊料(未图示)连接在第二引线框64的上表面。
在第二引线框64配置有阴极端子11-1。
配置于二极管芯片1-1的正面的阳极电极1a-1通过键合线6与第一引线框63连接，并与二极管芯片1-2的阴极电极1b-2电连接。
配置于二极管芯片1-2的正面的阳极电极1a-2通过键合线6分别与以隔着阴极端子11-1而配置的两个阳极端子12-1电连接。
将未配置二极管芯片1-1、1-2的第一引线框63的背面和第二引线框64的背面配置为从密封树脂9露出。
将阴极端子11-1和阳极端子12-1以相邻的方式配置。
通过将二极管芯片1-1、1-2搭载于同一封装件，能够使二极管芯片1-1的阳极电极1a-1与二极管芯片1-2的阴极电极1b-2在封装件内部电连接。
上述封装件(半导体装置)通过焊料(未图示)与配置于基板20上的布线图案21电连接。由此，能够省去基板内的布线图案，能够实现节约空间。
通过使第一引线框63的背面与布线图案21连接，从而由二极管芯片1-1的阴极电极1b-1构成PFC电路等电力电路。
由此，将未配置二极管芯片1-1、1-2的第一引线框63的背面和第二引线框64的背面与基板连接，能够提高散热性。
实施方式十四
在图14示出实施方式十四。图14的(a)示出俯视图(上表面的密封树脂未图示)，图14的(b)示出图14的(a)的N-N’线位置的剖面图，图14的(c)示出后视图，图14的(d)示出与基板的连接图。
本实施方式与实施方式十三的不同之处在于，阴极端子11-2和阳极端子12-2的各端子从密封树脂9以与第一引线框73的背面和第二引线框74的背面露出于同一平面。
实施方式十四能够获得与实施方式十三相同的效果。
以上，利用实施方式对本发明进行了说明，但本发明的技术范围并不限定于上述实施方式所记载的范围。本领域技术人员应知晓，对上述实施方式能够进行各种改变或改良。从权利要求书可知，这样进行改变或改良了的方式也应该包含于本发明的技术范围。

Claims (11)

1.一种半导体装置，其特征在于，
在具有第一引线框和第二引线框的半导体装置中，
在所述第一引线框具备第一端子，
在所述第二引线框具备第二端子，
在所述第一引线框的一侧的主面上具备第一半导体芯片，
在所述第二引线框的一侧的主面上具备第二半导体芯片，
在所述第二半导体芯片的正面具有第二电极和第三电极，
所述第二电极通过键合线与第三端子和第四端子电连接，
所述第三电极通过键合线与第五端子电连接，
将所述第一引线框的另一侧的主面与所述第二引线框的另一侧的主面配置为从密封树脂露出，
配置于所述第一半导体芯片的正面的第一电极通过键合线与第三引线框的一侧的主面连接，
所述第三引线框的所述一侧的主面通过键合线与所述第二引线框的所述一侧的主面连接，
所述第三引线框的另一侧的主面从所述密封树脂露出。
2.根据权利要求1所述的半导体装置，其特征在于，
将所述第一端子、所述第二端子、所述第三端子、所述第四端子和所述第五端子配置为从所述密封树脂露出。
3.根据权利要求1所述的半导体装置，其特征在于，
在所述第一引线框和所述第二引线框之间具备贯穿孔。
4.一种半导体装置，其特征在于，
在具有第四引线框和第五引线框的半导体装置中，
在所述第四引线框具备第六端子，
在所述第五引线框具备第七端子，
在所述第四引线框的一侧的主面上具备第三半导体芯片，
在所述第五引线框的一侧的主面上具备第四半导体芯片和第五半导体芯片，
在所述第四半导体芯片的正面具有第五电极和第六电极，
在所述第五半导体芯片的正面具有第七电极，
所述第五电极通过键合线与第八端子和第九端子电连接，
所述第六电极通过键合线与第十端子电连接，
所述第七电极通过键合线与所述第五电极电连接，
将所述第四引线框的另一侧的主面与所述第五引线框的另一侧的主面配置为从密封树脂露出，
配置于所述第三半导体芯片的正面的第四电极通过键合线与第六引线框的一侧的主面连接，
所述第六引线框的所述一侧的主面通过键合线与所述第五引线框的所述一侧的主面连接，
所述第六引线框的另一侧的主面从所述密封树脂露出。
5.根据权利要求4所述的半导体装置，其特征在于，
将所述第六端子、所述第七端子、所述第八端子、所述第九端子和所述第十端子配置为从所述密封树脂露出。
6.一种半导体装置，其特征在于，在具有
第七引线框，和
第八引线框的半导体装置中，
在所述第八引线框具备第十一端子，
在所述第七引线框的一侧的主面上具备第六半导体芯片，
在所述第八引线框的一侧的主面上具备第七半导体芯片，
在所述第七半导体芯片的正面具有第九电极和第十电极，
所述第九电极通过键合线与第十二端子和第十三端子电连接，
所述第十电极通过键合线与第十四端子电连接，
将所述第七引线框的另一侧的主面与所述第八引线框的另一侧的主面设置为从密封树脂露出，
配置于所述第六半导体芯片的正面的第八电极通过键合线与第九引线框的一侧的主面连接，
所述第九引线框的所述一侧的主面通过键合线与所述第八引线框的所述一侧的主面连接，
所述第九引线框的另一侧的主面从所述密封树脂露出。
7.根据权利要求6所述的半导体装置，其特征在于，
将所述第十一端子、所述第十二端子、所述第十三端子和所述第十四端子配置为从所述密封树脂露出。
8.根据权利要求6所述的半导体装置，其特征在于，
所述第七引线框的所述另一侧的主面与配置于基板上的布线图案电连接。
9.一种半导体装置，其特征在于，
在具有第十引线框和第十一引线框的半导体装置中，
在所述第十一引线框具备第十五端子，
在所述第十引线框的一侧的主面上具备第八半导体芯片，
在所述第十一引线框的一侧的主面上具备第九半导体芯片和第十半导体芯片，
在所述第九半导体芯片的正面具有第十二电极和第十三电极，
在所述第十半导体芯片的正面具有第十四电极，
所述第十二电极通过键合线与第十六端子和第十七端子电连接，
所述第十三电极通过键合线与第十八端子电连接，
所述第十四电极通过键合线与所述第十二电极电连接，
将所述第十引线框的另一侧的主面与所述第十一引线框的另一侧的主面设置为从密封树脂露出，
配置于所述第八半导体芯片的正面的第十一电极通过键合线与第十二引线框的一侧的主面连接，
所述第十二引线框的所述一侧的主面通过键合线与所述第十一引线框的所述一侧的主面连接，
所述第十二引线框的另一侧的主面从所述密封树脂露出。
10.根据权利要求9所述的半导体装置，其特征在于，
将所述第十五端子、所述第十六端子、所述第十七端子和所述第十八端子配置为从所述密封树脂露出。
11.根据权利要求9所述的半导体装置，其特征在于，
所述第十引线框的所述另一侧的主面与配置于基板上的布线图案电连接。
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