JP6729474B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP6729474B2
JP6729474B2 JP2017085648A JP2017085648A JP6729474B2 JP 6729474 B2 JP6729474 B2 JP 6729474B2 JP 2017085648 A JP2017085648 A JP 2017085648A JP 2017085648 A JP2017085648 A JP 2017085648A JP 6729474 B2 JP6729474 B2 JP 6729474B2
Authority
JP
Japan
Prior art keywords
sense
wire
output electrode
terminal
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017085648A
Other languages
English (en)
Other versions
JP2018186600A (ja
Inventor
白石　卓也
卓也 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2017085648A priority Critical patent/JP6729474B2/ja
Priority to US15/796,878 priority patent/US10122358B1/en
Priority to DE102017223060.6A priority patent/DE102017223060B4/de
Priority to CN201810373782.1A priority patent/CN108736740B/zh
Publication of JP2018186600A publication Critical patent/JP2018186600A/ja
Application granted granted Critical
Publication of JP6729474B2 publication Critical patent/JP6729474B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1425—Converter
    • H01L2924/14252—Voltage converter
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

Description

本発明は、メイン端子とセンス端子を有するトランジスタを備える半導体装置に関する。
トランスファーモールド型インバータモジュールなどのＩＰＭの短絡保護のために、エミッタ電流検出方式が用いられている。この方式では、Ｎ側ＩＧＢＴのエミッタ部に外部シャント抵抗を接続し、短絡電流が発生した場合にシャント抵抗間電圧を検出して制御ＩＣにフィードバックし回路遮断を行う。
また、ＩＰＭの大容量品種にエミッタ電流検出方式を用いる場合、外部シャント抵抗の許容電力を大きくする必要がある。このため、オンチップカレントセンス内蔵ＩＧＢＴを用いて主電流から分流された微少電流を検出し短絡電流を検出するカレントセンス電流検出方式が用いられる。
なお、互いに並列接続された複数のスイッチング素子間の電流アンバランスを低減するために、各素子のインダクタンスを同一にするようにＡｌワイヤ本数を調整することが提案されている（例えば、特許文献１参照）。
特開２０１３−１０６３８４号公報
カレントセンス電流検出方式では、センス端子に短絡電流検出用の抵抗を接続する。このため、メイン部のエミッタのインダクタンスはセンス部より小さくなる。従って、ＩＧＢＴのメイン部とセンス部でＩＧＢＴゲート電圧差が生じ、各々のＩＧＢＴに流れる電流比がばらつく。このため、短絡電流検出の精度が低くなるという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的は短絡電流検出の精度を改善することができる半導体装置を得るものである。
本発明に係る半導体装置は、メイン端子とセンス端子を有するトランジスタと、前記メイン端子と第１のワイヤで接続されたメイン出力電極と、前記センス端子と第２のワイヤで接続されたセンス出力電極と、前記トランジスタ、前記第１及び第２のワイヤ、前記メイン出力電極の一部、及び前記センス出力電極の一部を封止するパッケージと、前記パッケージの内部に設けられた中継電極とを備え、前記メイン端子から前記メイン出力電極までの配線インダクタンスは、前記センス端子から前記センス出力電極までの配線インダクタンスよりも大きく、前記第１のワイヤの長さは前記第２のワイヤの長さより長く、前記第１のワイヤは、前記メイン端子と前記中継電極を接続する第３のワイヤと、前記中継電極と前記メイン出力電極を接続する第４のワイヤとを有し、前記トランジスタ、前記メイン出力電極、前記中継電極、前記第２、第３及び第４のワイヤはそれぞれ複数相に分けられ、各相において、前記第３のワイヤが長いほど前記第４のワイヤの本数が多いことを特徴とする。
本発明では、トランジスタのメイン端子からメイン出力電極までの配線インダクタンスが、センス端子からセンス出力電極までの配線インダクタンスよりも大きい。これにより、センス端子に短絡電流検出用の抵抗を接続するカレントセンス電流検出方式において、トランジスタのメイン部とセンス部のゲート電圧差が小さくなるため、両者の電流比が小さくなる。この結果、短絡電流検出の精度を改善することができる。
本発明の実施の形態１に係る半導体装置を示す図である。 本発明の実施の形態１に係る半導体装置のパッケージ内部を示す図である。 本発明の実施の形態２に係る半導体装置のパッケージ内部を示す図である。 本発明の実施の形態３に係る半導体装置のパッケージ内部を示す図である。 本発明の実施の形態４に係る半導体装置のパッケージ内部を示す図である。 本発明の実施の形態５に係る半導体装置を示す図である。
本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す図である。パッケージ１の内部にＩＧＢＴ２と、それを制御する制御ＩＣ３と、ＩＧＢＴ２のエミッタ端子に接続されたインダクタＬとが設けられている。この半導体パッケージはインテリジェントパワーモジュール（Intelligent Power Module、IPM）である。インダクタＬはＮ相出力電極４を介してパッケージ１の外部に接続される。
パッケージ１の外部に設けられた抵抗ＲがＩＧＢＴ２のセンス端子に接続されている。この抵抗Ｒに印加される電圧により短絡電流を検出し、制御ＩＣ３にフィードバックにする。制御ＩＣ３は短絡電流を検出した場合にＩＧＢＴ２の回路遮断を行う。
図２は、本発明の実施の形態１に係る半導体装置のパッケージ内部を示す図である。リードフレームは、Ｎ相出力電極４、パッド５、センス出力電極６、及び中継電極７を有する。パッド５の上にＩＧＢＴ２が設けられている。ＩＧＢＴ２はエミッタ端子８とセンス端子９を有する。
エミッタ端子８はＡｌワイヤ１０により中継電極７に接続され、中継端子７はＡｌワイヤ１１によりセンス出力電極６に接続されている。センス端子９はＡｌワイヤ１２により中継電極７に接続されている。なお、従来技術では、センス端子９は中継電極７及びワイヤ１１を介さずに、Ａｌワイヤ１０だけによりセンス出力電極６に接続されていた。本実施の形態で追加されたＡｌワイヤ１１が図１のインダクタＬに該当する。
パッケージ１が、ＩＧＢＴ２、Ａｌワイヤ１０，１１，１２、パッド５、中継電極７、Ｎ相出力電極４の一部、及びセンス出力電極６の一部を封止する。なお、図２では制御ＩＣ３は図示を省略している。
Ａｌワイヤ１０，１１の合計の長さはＡｌワイヤ１２の長さより長い。従って、ＩＧＢＴ２のエミッタ端子８からＮ相出力電極４までの配線インダクタンスが、センス端子９からセンス出力電極６までの配線インダクタンスよりも大きい。これにより、センス端子９に短絡電流検出用の抵抗Ｒを接続するカレントセンス電流検出方式において、ＩＧＢＴ２のメイン部とセンス部のＩＧＢＴゲート電圧差が小さくなるため、両者の電流比が小さくなる。この結果、短絡電流検出の精度を改善することができる。
実施の形態２．
図３は、本発明の実施の形態２に係る半導体装置のパッケージ内部を示す図である。実施の形態１と比べて中継端子７とＡｌワイヤ１１が無い。その代わりに、センス端子９とセンス出力電極６を接続するＡｌワイヤ１２の本数が、エミッタ端子８とＮ相出力電極４を接続するＡｌワイヤ１０の本数より多い。このため、エミッタ端子８からＮ相出力電極４までの配線インダクタンスが、センス端子９からセンス出力電極６までの配線インダクタンスよりも大きくなる。従って、実施の形態１と同様の効果を得ることができる。
実施の形態３．
図４は、本発明の実施の形態３に係る半導体装置のパッケージ内部を示す図である。ＩＧＢＴ２、Ｎ相出力電極４、中継電極７、Ａｌワイヤ１０，１１，１２はそれぞれ複数相に分けられている。ここでは、ＵＮ相、ＶＮ相、ＷＮ相の三相に分けられている。それぞれの相の間でＩＧＢＴ２と中継電極７の位置関係によりＡｌワイヤ１０の長さが異なる。そこで、各相において、Ａｌワイヤ１０が長いほどＡｌワイヤ１１の本数を多くし、センス部のＡｌワイヤ１２を短くする。これにより、相間の配線インダクタンスの差が小さくなり、相間バラツキを小さくすることができる。
ただし、各相において、ＩＧＢＴ２のエミッタ端子８からＮ相出力電極４までの配線インダクタンスが、センス端子９からセンス出力電極６までの配線インダクタンスよりも大きくなるようにする。これにより、実施の形態１と同様の効果を得ることができる。
実施の形態４．
図５は、本発明の実施の形態４に係る半導体装置のパッケージ内部を示す図である。センス出力電極６は複数のフレームに分割され互いにワイヤ１３を介して接続されている。分割されたフレームのそれぞれに各相のＩＧＢＴ２のセンス端子９が接続されている。
実施の形態３ではセンス部のＡｌワイヤ１２の長さを相ごとで調整していたが、本実施の形態では、分割されたセンス出力電極６のフレーム間を接続するＡｌワイヤ１３の長さを相ごとで調整する。これにより実施の形態３と同様の効果を得ることができる。
実施の形態５．
図６は、本発明の実施の形態５に係る半導体装置を示す図である。実施の形態１のＩＧＢＴ２の代わりにＳｉＣＭＯＳトランジスタ１４を用いる。ＳｉＣＭＯＳトランジスタ１４はＩＧＢＴ２に比べて使用温度範囲が広く、温度特性による分流比バラツキが大きくなる。従って、ＳｉＣ搭載モジュールに本発明を適用することで更に顕著な効果を得ることができる。
１ パッケージ、２ ＩＧＢＴ（トランジスタ）、３ 制御ＩＣ、４ Ｎ相出力電極、６ センス出力電極、７ 中継電極、８ エミッタ端子（メイン端子）、９ センス端子、１０，１１，１２，１３ Ａｌワイヤ、１４ ＳｉＣＭＯＳトランジスタ（トランジスタ）、Ｒ 抵抗

Claims (4)

  1. メイン端子とセンス端子を有するトランジスタと、
    前記メイン端子と第１のワイヤで接続されたメイン出力電極と、
    前記センス端子と第２のワイヤで接続されたセンス出力電極と、
    前記トランジスタ、前記第１及び第２のワイヤ、前記メイン出力電極の一部、及び前記センス出力電極の一部を封止するパッケージと、
    前記パッケージの内部に設けられた中継電極とを備え、
    前記メイン端子から前記メイン出力電極までの配線インダクタンスは、前記センス端子から前記センス出力電極までの配線インダクタンスよりも大きく、
    前記第１のワイヤの長さは前記第２のワイヤの長さより長く、
    前記第１のワイヤは、前記メイン端子と前記中継電極を接続する第３のワイヤと、前記中継電極と前記メイン出力電極を接続する第４のワイヤとを有し、
    前記トランジスタ、前記メイン出力電極、前記中継電極、前記第２、第３及び第４のワイヤはそれぞれ複数相に分けられ、
    各相において、前記第３のワイヤが長いほど前記第４のワイヤの本数が多いことを特徴とする半導体装置。
  2. 前記パッケージの内部に設けられ、前記トランジスタを制御する制御ＩＣと、
    前記パッケージの外部に設けられ、前記センス出力電極に接続された抵抗とを更に備え、
    前記制御ＩＣは、前記抵抗に印加される電圧により短絡電流を検出した場合に前記トランジスタの回路遮断を行うことを特徴とする請求項１に記載の半導体装置。
  3. 前記センス出力電極は複数のフレームに分割され互いに第５のワイヤを介して接続され、それぞれに複数相の前記トランジスタの前記センス端子が接続されていることを特徴とする請求項１又は２に記載の半導体装置。
  4. 前記トランジスタはＳｉＣＭＯＳトランジスタであることを特徴とする請求項１〜３の何れか１項に記載の半導体装置。
JP2017085648A 2017-04-24 2017-04-24 半導体装置 Active JP6729474B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2017085648A JP6729474B2 (ja) 2017-04-24 2017-04-24 半導体装置
US15/796,878 US10122358B1 (en) 2017-04-24 2017-10-30 Packaged semiconductor device
DE102017223060.6A DE102017223060B4 (de) 2017-04-24 2017-12-18 Halbleitervorrichtung
CN201810373782.1A CN108736740B (zh) 2017-04-24 2018-04-24 半导体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017085648A JP6729474B2 (ja) 2017-04-24 2017-04-24 半導体装置

Publications (2)

Publication Number Publication Date
JP2018186600A JP2018186600A (ja) 2018-11-22
JP6729474B2 true JP6729474B2 (ja) 2020-07-22

Family

ID=63714657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017085648A Active JP6729474B2 (ja) 2017-04-24 2017-04-24 半導体装置

Country Status (4)

Country Link
US (1) US10122358B1 (ja)
JP (1) JP6729474B2 (ja)
CN (1) CN108736740B (ja)
DE (1) DE102017223060B4 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021234803A1 (ja) * 2020-05-19 2021-11-25 三菱電機株式会社 半導体モジュール

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04186645A (ja) * 1990-11-16 1992-07-03 Sanyo Electric Co Ltd マイクロ波集積回路の製造方法
JPH106384A (ja) 1996-06-18 1998-01-13 Nippon Ester Co Ltd ポリマーシートの成形装置
JP4708951B2 (ja) * 2005-10-21 2011-06-22 ニチコン株式会社 インバータモジュールおよびそれを用いたインバータ一体型交流モータ
JP5444619B2 (ja) * 2008-02-07 2014-03-19 株式会社ジェイテクト 多層回路基板およびモータ駆動回路基板
JP2011182591A (ja) * 2010-03-02 2011-09-15 Panasonic Corp 半導体装置
JP5280410B2 (ja) * 2010-06-21 2013-09-04 三菱電機株式会社 半導体装置、スナバデバイス
JP5706251B2 (ja) * 2011-06-30 2015-04-22 ルネサスエレクトロニクス株式会社 半導体装置
JP2013106384A (ja) 2011-11-10 2013-05-30 Toyota Motor Corp 電力変換装置及びその電流調整方法
US9781556B2 (en) 2013-04-05 2017-10-03 Intel Corporation Network-assisted to direct device discovery switch
JP6094420B2 (ja) * 2013-08-09 2017-03-15 三菱電機株式会社 半導体装置
JP2015228447A (ja) * 2014-06-02 2015-12-17 株式会社デンソー 半導体装置の製造方法
US9831159B2 (en) * 2015-06-09 2017-11-28 Infineon Technologies Americas Corp. Semiconductor package with embedded output inductor
JP6520437B2 (ja) * 2015-06-12 2019-05-29 富士電機株式会社 半導体装置
JP2017069412A (ja) * 2015-09-30 2017-04-06 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
DE102017223060A1 (de) 2018-10-25
CN108736740B (zh) 2020-06-30
US10122358B1 (en) 2018-11-06
CN108736740A (zh) 2018-11-02
DE102017223060B4 (de) 2021-05-12
JP2018186600A (ja) 2018-11-22
US20180309441A1 (en) 2018-10-25

Similar Documents

Publication Publication Date Title
JP5783997B2 (ja) 電力用半導体装置
US20170110395A1 (en) Semiconductor device
US9599655B2 (en) Semiconductor device
JP6065979B2 (ja) 半導体装置
US9941255B2 (en) Power semiconductor module
US10727213B2 (en) Power semiconductor module and power semiconductor device
JP5940211B2 (ja) 半導体装置
JP4892032B2 (ja) 電力変換装置
JP2008042950A (ja) 電力変換装置
JP5925364B2 (ja) 電力用半導体装置
JP2019029997A (ja) 半導体装置
JP2015032984A (ja) 半導体素子の駆動装置およびそれを用いた電力変換装置
US8570780B2 (en) Semiconductor device
JP6729474B2 (ja) 半導体装置
JP2009165285A (ja) 半導体装置
JP6490017B2 (ja) パワーモジュール、３相インバータシステム、およびパワーモジュールの検査方法
JP6107949B2 (ja) 半導体モジュール
JP7117904B2 (ja) 電力用半導体装置
US20200083700A1 (en) Semiconductor module and power conversion apparatus
CN109983699B (zh) 栅极驱动电路
US10629587B2 (en) Protection circuit and protection circuit system
WO2019022206A1 (ja) 半導体装置
JP2013059260A (ja) インバータ回路
JP2018037919A (ja) ゲート駆動回路
JP2010035391A (ja) インバータ回路

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190520

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200317

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200318

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200507

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200602

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200615

R150 Certificate of patent or registration of utility model

Ref document number: 6729474

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250