CN101295687A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101295687A
CN101295687A CNA2008100935954A CN200810093595A CN101295687A CN 101295687 A CN101295687 A CN 101295687A CN A2008100935954 A CNA2008100935954 A CN A2008100935954A CN 200810093595 A CN200810093595 A CN 200810093595A CN 101295687 A CN101295687 A CN 101295687A
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China
Prior art keywords
lead
semiconductor device
source
pad portion
coupled
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Granted
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CNA2008100935954A
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CN101295687B (zh
Inventor
武藤邦治
波多俊幸
佐藤仁久
冈浩伟
池田靖
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NEC Corp
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Renesas Technology Corp
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Publication of CN101295687A publication Critical patent/CN101295687A/zh
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Abstract

本发明公开了一种半导体器件。本发明的目的是实现其中密封功率MOSFET的小表面安装封装的导通电阻的减小。硅芯片安装在与构成漏极引线的引线集成的芯片焊盘部上。硅芯片的主表面上具有源极焊盘和栅极焊盘。硅芯片的背面构成功率MOSFET的漏极,并经由Ag浆料键合至芯片焊盘部的顶表面。构成源极引线的引线经由Al带电耦合至源极焊盘,而构成栅极引线的引线经由Au线电耦合至栅极焊盘。

Description

半导体器件
相关申请的交叉引用
分别于2007年6月20和2007年4月27日提交的本申请的相关日本专利申请2007-162684和2007-118833均包含专利说明书、附图和摘要,在此通过引用并入其全部内容。
技术领域
本发明涉及半导体器件,尤其是涉及具有小表面安装封装的半导体器件。
背景技术
用于便携式信息装置的功率控制开关或者充电/放电保护电路的功率MOSFET(金属氧化物半导体场效应晶体管)密封在小表面安装封装(例如SOP8)中。这种功率MOSFET例如在日本公开专利申请2000-164869或日本公开专利申请2000-299464中进行了描述。
日本公开专利申请2000-164869公开了一种用于降低在包含构成n+型硅衬底的上层的p型外延层的结构中形成的沟槽栅极功率MOSFET(金属氧化物半导体场效应晶体管)中的穿通击穿的风险的技术:形成n型漏极区使其在n+型硅衬底和沟槽的底部之间延伸;以及形成n型漏极区和p型外延层之间的结以使其在n+型硅衬底和沟槽的间隔之间延伸。
日本公开专利申请2000-299464公开了一种用于降低漏极区的导通电阻的技术:在第一导电类型的半导体衬底上布置第一导电类型的外延层和第二导电类型的阱层;在由这些外延层和阱层构成的上侧层中形成由绝缘层隔离的深沟槽栅极;在所述沟槽栅极下方形成漏极区;形成与所述沟槽栅极相邻的源极区;以及在所述阱层的上方形成主体区,所述主体区被利用杂质与所述阱层相比更重地掺杂。
发明内容
本发明人研究了用于在其中密封上述功率MOSFET的SOP8。本发明人研究的SOP8具有一种封装结构,其中其上形成有功率MOSFET的硅芯片利用模制树脂密封。
硅芯片安装在与漏极引线集成的芯片焊盘部上,其中硅芯片的主表面向上。硅芯片的背面形成功率MOSFET的漏极,并经由Ag浆料键合到芯片焊盘部的顶表面。
硅芯片在其主表面上具有源极焊盘和栅极焊盘。源极焊盘和栅极焊盘由导电膜制成,该导电膜主要由形成于硅芯片的最上层上的Al膜构成。源极焊盘具有比栅极焊盘更宽的面积以降低功率MOSFET的导通电阻。基于类似的原因,硅芯片的整个背表面形成功率MOSFET的漏极。
在模制树脂的外部,露出构成SOP8的外部连接端子的源极引线、漏极引线、和栅极引线。源极引线和源极焊盘,以及栅极引线和栅极焊盘经由Au线彼此电耦合。具有小面积的栅极焊盘利用单条Au线耦合至栅极引线。另一方面,具有比栅极焊盘宽的面积的源极焊盘利用多条Au线电耦合至源极引线。
但是,在具有这种结构的SOP8中,不能充分地降低源极焊盘与Au线或者源极引线与Au线之间的接触电阻。由于源极焊盘或源极引线与Au线之间的小接触面积使得即使通过增加Au线的数目也难以提供足够的接触面积,因此产生降低接触电阻的上述困难。而为了获得许多Au线的耦合而增加源极焊盘的面积增加了硅芯片的尺寸,因此增加了其在SOP8中的安装面积。
本发明的一个目的是提供能够实现具有低导通电阻的小表面安装封装的技术。
本发明的另一目的是提供能够实现表面安装封装的尺寸减小的技术。
本发明的又一目的是提供能够实现表面安装封装的产率和可靠性的提高的技术。
本发明的再一目的是提供能够实现表面安装封装的生产成本的降低的技术。
本发明的上述及其它目的和新颖特征将从此处的描述和附图中变得清楚。
接下来简述此处公开的本发明的典型发明的概要。
本发明的半导体器件具有已经被安装到引线框的芯片焊盘部分上的半导体芯片,该半导体芯片利用树脂封装密封,并使得引线框的外引线部分露在树脂封装外部,其中引线框具有栅极引线、源极引线、漏极引线、和与漏极引线集成的芯片焊盘部分。半导体芯片在其主表面上具有:栅极焊盘,耦合至功率MOSFET的栅电极;源极焊盘,耦合至功率MOSFET的源极,且具有比栅极焊盘的面积大的面积。半导体芯片的背面形成功率MOSFET的漏极,并利用Ag浆料耦合到芯片焊盘部分上。源极引线利用Al带耦合至源极焊盘。
在本发明中,术语“Al带”指的是主要由Al构成的导电材料所制成的带状连接器。Al带通常在被绕卷轴卷绕时安装在键合设备中。Al带例如通过超声键合或激光键合被耦合至引线或焊盘。由于Al带非常薄,在其耦合至引线或焊盘时它的长度和环形状可以自由确定。
有一种称为夹片(clip)的材料,作为类似于Al带的连接器。夹片是由例如Cu合金或Al制成的薄金属片,并被预先模制或形成为预定环形状和预定长度。当夹片耦合至引线和焊盘时,夹片的一端放置在引线上,另一端放置在焊盘上,且它们同时耦合。耦合方法的实例包括焊料键合、Ag浆料键合、和超声键合。
在本发明中,术语“带”指的是包含夹片的连接器。带的长度或环形状可以根据引线或焊盘的面积或者引线和焊盘之间的距离自由确定,不过,所述带优选为其环形状和长度已经预先确定的夹片。
接下来将简述此处公开的本发明的典型发明可以获得的优点。
本发明可以实现具有低导通电阻的表面安装半导体器件。
附图说明
图1为示出根据本发明实施例1的半导体器件的外观的平面图;
图2为示出根据本发明实施例1的半导体器件的外观的侧视图;
图3为示出根据本发明实施例1的半导体器件的内部结构的平面图;
图4为沿图3的A-A线所取的截面图;
图5为沿图3的B-B线所取的截面图;
图6为示出在半导体芯片上形成的功率MOSFET的局部截面图;
图7为示出最上层的导电膜以及位于导电膜下方的栅电极的平面图,该导电膜包括源极焊盘、栅极焊盘、形成在硅芯片上方的栅极互连;
图8为示出根据本发明实施例1的半导体器件的制造步骤的一个实例的流程图;
图9示出在将Al带楔入键合到硅芯片的源极焊盘时将振荡能添加到Ag浆料的方式;
图10解释用于导出Ag浆料的最佳弹性模量的选择指南等式;
图11为示出四个Ag浆料的抗断试验的结果的图表,用于确认选择指南等式的有效性;
图12为示出Ag浆料的弹性模量与剪切强度的关系的测量结果的图表;
图13为示出根据实施例2的半导体器件的内部结构的平面图;
图14为示出利用键合工具同时键合多个Al带的步骤的局部透视图;
图15为示出根据本发明实施例3的半导体器件的内部结构的平面图;
图16为示出根据本发明实施例4的半导体器件的内部结构的平面图;
图17为示出根据本发明实施例5的半导体器件的内部结构的平面图;
图18为示出根据本发明实施例6的半导体器件的外观的平面图;
图19为示出根据本发明实施例6的半导体器件的外观的平面图;
图20为示出根据本发明实施例6的半导体器件的内部结构的平面图;
图21为沿图20的C-C线所取的截面图;
图22示意性地示出根据本发明实施例6的半导体器件的操作;
图23为示出在根据本发明实施例6的半导体器件的制造步骤期间夹片与引线的接触区的局部平面图;
图24为示出在硅芯片上形成的IGBP的局部截面图;
图25示出使用本发明的实施例6的半导体器件的一个电路实例;
图26为示出根据本发明实施例7的半导体器件的内部结构的平面图;
图27为沿图26的D-D线所取的截面图;
图28为沿图26的E-E线所取的截面图;
图29为沿图26的F-F线所取的截面图;
图30为示出根据本发明实施例7的半导体器件的内部结构的平面图;
图31为沿本发明的G-G线所取的截面图;
图32为沿图30的H-H线所取的截面图;
图33为示出根据本发明另一实施例的半导体器件的内部结构的平面图;
图34为示出根据本发明再一实施例的半导体器件的内部结构的平面图;
图35为示出根据本发明又一实施例的半导体器件的内部结构的平面图。
具体实施方式
以下将基于附图具体描述本发明的实施例。在用于例示本发明实施例的所有附图中,具有相同功能的部件由相同的标号来标识,并将省略重复的描述。在用于例示本发明实施例的附图中,即便是平面图有时也带有阴影线,以辅助理解其构成。
实施例1
图1至图5示出根据本实施例的半导体器件,其中图1为的该半导体器件的外观平面图;图2为其外观侧视图;图3为其内部结构的平面图;图4为沿图3的A-A线所取的截面图;图5为沿图3的B-B线所取的截面图。
本实施例的半导体器件1A适用于SOP8,SOP8是一种小表面安装封装。构成SOP8的外部连接端子的八条引线4中的每一个的外引线部露在由环氧树脂制成的模制树脂2的外部。在图1所示的引线4中,第一至第三引线为源极引线,第四引线为栅极引线,第五至第八引线为漏极引线。
在模制树脂2内密封其上具有功率MOSFET的硅芯片3(将在后文描述)。该功率MOSFET用于例如便携式信息装置的功率控制开关或充电/放电保护电路。硅芯片3具有例如3.9mm(长边)×2.2mm(短边)的平面形状。
硅芯片3安装在芯片焊盘部4D上,硅芯片的主表面向上,其中芯片焊盘部4D与形成漏极引线的四条引线4(第五至第八引线)集成。硅芯片3的背面形成功率MOSFET的漏极,并经由Ag浆料5键合到芯片焊盘部4D的顶表面。芯片焊盘部4D和八条引线4(第一引线至第八引线)由Cu或Fe-Ni合金制成,并且它们在其表面上分别具有三层(Ni/Pd/Au)镀层(未示出),该镀层通过在用作主成分的Pd膜上方和下方堆叠Ni膜和Au膜而获得。主要由Pd膜构成的镀层的作用将在后文描述。
源极焊盘(源电极)7和栅极焊盘8形成在硅芯片3的主表面上。源极焊盘7和栅极焊盘8由形成为硅芯片3的最上层、且主要由Al膜构成的导电膜制成。源极焊盘7具有比栅极焊盘8更宽的面积,以降低功率MOSFET的导通电阻。由于类似的理由,硅芯片3的整个背面形成功率MOSFET的漏极。
在本实施例的半导体器件1A中,形成源极引线的三条引线4(第一至第三引线)在模制树脂2内彼此耦合。耦合部经由Al带10与源极焊盘7电耦合。Al带10的厚度约为0.1mm,宽度约为1mm。为了降低功率MOSFET的导通电阻,最好使得Al带10的宽度接近源极焊盘7的宽度,从而增加Al带10和源极焊盘7之间的接触面积。形成栅极引线的引线4(第四引线)经由Au线11与栅极焊盘8电耦合。
以下将描述在硅芯片3上形成的功率MOSFET。图6为示出作为功率MOSFET的一个实例的n沟道沟槽栅极功率MOSFET的硅芯片3的局部截面图。
n+型单晶硅衬底20在其主表面上具有通过外延生长形成的n-型单晶硅层21。n+型单晶硅衬底20和n-型单晶硅层21构成功率MOSFET的漏极。
在n-型单晶硅层21的一部分中形成p阱22。在n-型单晶硅层21的部分表面上形成氧化硅膜23,而在n-型单晶硅层21的其它部分中形成多个沟槽24。由氧化硅膜23覆盖的n-型单晶硅层21的区域构成元件隔离区,而其中形成沟槽24的区域构成元件形成区(有源区)。尽管未示出,但沟槽24具有多边平面形状(例如,方形、六边形或八边形)或者在一个方向延伸的带状。
每个沟槽24在其底表面和侧表面上具有用于构成功率MOSFET的栅极氧化膜的氧化硅膜25。沟槽24填充有用于构成功率MOSFET的栅电极的多晶硅膜26A。另一方面,氧化硅膜23上具有由多晶膜制成的栅引线电极26B,该多晶膜在与构成栅电极的多晶硅膜26A相同的步骤中沉积。栅电极(多晶硅膜26A)和栅引线电极26B在未示出的区域中电耦合。
在元件形成区的n-型单晶硅层21中,形成比沟槽24浅的p-型半导体区27。该p-型半导体区27构成功率MOSFET的沟道层。p-型半导体区27上具有p型半导体区28,p型半导体区28的杂质浓度高于p-型半导体区27。p型半导体区28上具有n+型半导体区29。p型半导体区28构成功率MOSFET的穿通停止层,而n+型半导体区29构成功率MOSFET的源极。
在其中形成功率MOSFET的元件形成区上,以及在其中形成栅极引线电极26B的元件隔离区上,形成氧化硅膜30和31作为两层。在元件形成区中,形成连接孔32,连接孔32穿透氧化硅膜31和30、p型半导体区28和n+型半导体区29,到达p-型半导体区27。在元件隔离区,形成连接孔33,连接孔33穿透氧化硅膜31和30,到达栅极引线电极26B。
在包含连接孔32和33内侧的氧化硅膜31上,形成各自都由薄TiW(钛钨)膜和厚Al膜的叠置膜制成的源极焊盘7和栅极互连34。在元件形成区中形成的源极焊盘7经由连接孔32电耦合至功率MOSFET的源极(n+型半导体区29)。连接孔32在其底部具有p+型半导体区35,用于使得源极焊盘7与p-型半导体区27进行欧姆接触。形成在元件隔离区的栅极互连34经由连接孔33下方的栅极引线电极26B耦合至功率MOSFET的栅电极(多晶硅膜26A)。
通过楔形键合(wedge bonding)方法将Al带10的一端电耦合至源极焊盘7。源极焊盘7优选具有氧化硅膜31和30上的3微米或更大的厚度,以在键合Al带10时减轻对功率MOSFET的冲击。
图7为示出作为最上层的导电膜的平面图,该导电膜包括形成于硅芯片3上的源极焊盘7、栅极焊盘8和栅极互连34,以及形成在硅芯片3下的栅电极(多晶硅膜26A)。栅极互连34电耦合至栅极焊盘8,源极焊盘7电耦合至Al互连36。硅芯片3在其周边具有Al互连37和38。栅极焊盘8和Al互连36、37和38由位于与源极焊盘7和栅极互连34的导电膜相同的层中的导电膜(TiW膜和Al膜的叠层)制成。在实际硅芯片3中,栅极互连34和Al互连36、37和38覆盖有表面保护膜(未示出),从而在最上导电膜中,仅源极焊盘7和栅极焊盘8从硅芯片3的表面露出。应该注意,在图7所示的实例中,其中形成栅电极(多晶硅膜26A)的沟槽24为正方平面形,因而栅电极(多晶硅膜26A)也为正方平面形。
图8为示出本实施例的半导体器件1A的制造步骤的一个实例的流程图。半导体器件1A的制造开始于根据已知的制造方法在硅晶片上形成功率MOSFET。然后将硅晶片切片成硅芯片3。制备其中形成有引线4和芯片焊盘部4D的引线框。利用Ag浆料5将硅芯片3安装到(芯片键合)到芯片焊盘部4D上。
通过已知的采用超声波的楔形键合方法,将Al带10键合在硅芯片3的源极焊盘7与构成源极引线的引线4(其中第一至第三引线已经彼此集成的部分)之间。然后,通过已知的采用热和超声波的球键合方法,将Au线11键合在硅芯片3的栅极焊盘8与构成栅极引线的引线4(第四引线)之间。Al带10的键合和Au线11的键合可以任意次序进行。
利用模具,使用模制树脂2密封硅芯片3(和芯片焊盘部4D、Al带10、Au线11、和引线4的内引线部分)。然后为模制树脂2的表面标记产品名称、生产号等等。在切割和去除露在模制树脂2外部的引线4的多余部分之后,将引线4形成为翅(gull-wing)形。在用于将好产品与缺陷产品区分开来的分类步骤之后,完成半导体器件1A。
在本实施例中,具有比Au线11更宽面积的Al带10用作导电材料,用于将具有比栅极焊盘8较宽面积的源极焊盘7电耦合至源极引线(引线4)。当Al带10被楔形键合到源极焊盘的表面时,键合工具12的大振荡能不仅增加到硅芯片3的表面,而且增加到位于硅芯片3和芯片焊盘部4D之间的Ag浆料5,如图9所示。因此,期望选择性地使用具有最佳弹性模量(Pa)的Ag浆料5,作为克服由于键合工具的大振荡能而导致在Ag浆料5中产生断裂的手段。
在本实施例中,通过如下的等式(1)定义Ag浆料5的弹性模量(Pa):
弹性模量(Pa)=2.6×粘合厚度(μm)/断裂位移(μm)×剪切强度(Pa)    (1)
在等式(1)中,粘合厚度为Ag浆料的厚度(μm),剪切强度(Pa)为剪切方向的力/截面面积(粘合面积)。断裂位移(μm)从图10所示的计算等式中导出。由于如下的不等式:断裂位移>允许Al带的超声键合的位移(在Al带超声键合期间由键合工具的振荡所导致的Ag浆料的位移量)成立,本实施例的Ag浆料5所需的弹性模量(Pa)的选择指南等式推导为{弹性模量(Pa)<2.6×粘合厚度(μm)/允许Al带的超声键合的位移(μm)×剪切强度(Pa)}。
以下将描述所进行的用于确认选择指南等式的有效性的抗断试验。试验所用的四个市场可购的Ag浆料((1)-(4))各自的弹性模量、剪切强度、和粘合厚度在表1中示出。在Al带的超声键合期间Ag浆料(1)、(3)和(4)的位移量均为0.128mm,而Ag浆料(2)的位移量为0.07mm。
表1
  弹性模量   剪切强度   粘合厚度
  Ag浆料(1)   5.30GPa   15.5MPa   15.4μm
  Ag浆料(2)   5.34GPa   8.6MPa   13.2μm
  Ag浆料(3)   2.42GPa   14.2MPa   24.4μm
  Ag浆料(4)   0.611GPa   3.8MPa   16.6μm
图11为示出用于确认选择指南等式的有效性的四个Ag浆料((1)-(4))的试验结果的图表。每个图表中的实线表示由等式(1)计算的各个Ag浆料((1)-(4))的弹性模量。
实线下方的区域为满足选择指南等式的区域,即可键合(bondable)区域。每个图表中的黑点表示各个Ag浆料((1)-(4))的实际弹性模量。
根据试验结果,其实际弹性模量满足选择指南等式的Ag浆料((3)和(4))没有断裂,而不满足选择指南等式的Ag浆料((1)和(2))断裂了。因此,已经从试验结果确认:通过选择满足上述选择指南等式的Ag浆料5可以有效地避免由于键合工具的振荡能导致发生的Ag浆料的断裂。
图12的图表示出当将Ag浆料的厚度设定为10μm且以标准超声键合输出(4W)键合Al带时Ag浆料的剪切强度与弹性模量的关系的测量结果。图表中的开圆表示不出现断裂的实例,而黑实圆表示出现断裂的实例。
这些测量结果表明Ag浆料的弹性模量优选在0.2GPa-5.3GPa的范围内,剪切强度(MPa)优选为8.5MPa或更大。在弹性模量小于0.2GPa时,由于过小的Ag含量导致不能获得期望的导电性。另一方面,在弹性模量超过5.3GPa时,由于太高的硬度阻止了在超声键合期间Ag浆料跟随振荡移动而变形,因此出现断裂。当Ag浆料具有小于8.5MPa的剪切强度时,它不能耐受在超声键合期间发生的冲击。
以下将描述在引线框(芯片焊盘部4D和引线4)表面上形成主要由Pd膜构成的镀层的作用。表格2示出在两种情况下,即在三个(Ag、Ni、Pd)镀层均形成在由Cu制成的引线框表面上的情况下和在不形成镀层的情况(裸Cu)下,源极引线和Al带、栅极引线和Au线、芯片焊盘部和Ag浆料之间的粘合状况(A指的是良好粘合,而B指的是差粘合)。
表2
源极:Al带,栅极:Au线,芯片键合材料:Ag浆料
Figure A20081009359500151
从表2明显可见,当在引线框表面上形成主要由Pd膜构成的镀层时,源极引线和Al带、栅极引线和Au线、以及芯片焊盘部与Ag浆料中的任意组合均展现良好的粘合状况。
表3
源极:Al带,栅极:Al线,芯片键合材料:Ag浆料
Figure A20081009359500161
从表3明显可见,当在引线框表面上形成主要由Pd膜构成的镀层时,甚至用Al线时栅极焊盘和栅极引线与之间的耦合也展现良好的粘合状态。因此,在引线框表面上形成主要由Pd膜构成的镀层使得能将任意组合与仅一种镀材耦合,导致制造步骤的简化。
根据本实施例,通过利用Al带10将构成源极引线的引线4耦合至源极焊盘7,与利用Au线进行引线4和源极焊盘7之间的耦合相比可以使得键合面积更大,这使得能降低半导体器件1A的电阻。此外,由于Al带10的成本低于Au线的成本,因此可以进一步降低半导体器件1A的制造成本。当这些耦合所需的电阻相等时,与利用Au线进行引线4和源极焊盘7之间的耦合相比可以减小源极焊盘的尺寸从而减小硅芯片3的尺寸,进而也能够降低半导体器件1A的制造成本。
本实施例使得能同时改进半导体器件1A的产率和可靠性,因为通过优化Ag浆料5的弹性模量和剪切强度可以防止由Al带10的超声键合而导致发生的Ag浆料5的断裂。
本实施例通过在引线框(芯片焊盘部4D和引线4)的表面上形成主要由Pd构成的镀层,使得能够实现从半导体器件1A消除Pb。
实施例2
图13为示出根据本实施例的半导体器件(SOP8)的内部结构的平面图。本实施例的半导体器件1B特征在于:构成源极引线的三条引线4(第一至第三引线)由多条Al带10电耦合至源极焊盘7。尽管对耦合至源极焊盘7的Al带10的数目没有特别限制,在图13中示出使用两条Al带10的耦合实例。
半导体器件(SOP8)取决于其类型或生成状况而在硅芯片3的尺寸上有所不同。源极焊盘7的面积根据硅芯片的尺寸而变化。当必须采用多种不同宽度的Al带10来制造上述半导体器件时,管理这些Al带10非常麻烦。另一方面,当仅采用一种具有较窄宽度的Al带10、且用于耦合的Al带10的数目根据源极焊盘7的面积而改变时,可以较容易和简单地管理Al带10。
对于多条Al带10至源极焊盘7的耦合而言,如图14所示的利用一个键合工具12同时键合多条Al带10的处理使得能够进行高效键合。
由于通过利用多条Al带10将构成源极引线的引线4耦合至源极焊盘7使得键合面积变大,因此可以促进半导体器件1B的电阻减小。
实施例3
图15为示出本实施例的半导体器件(SOP8)1C的内部结构的平面图。本实施例的半导体器件1C特征在于:在硅芯片3的主表面上形成的栅极焊盘8的面积扩大,以及不仅源极焊盘7和引线4、而且栅极焊盘8和引线4(栅极引线)由Al带10耦合。
根据本实施例,与利用Au线11进行栅极焊盘8和引线4之间的耦合相比,可以简化制造步骤。
实施例4
图16为示出本实施例的半导体器件(SOP8)1D的内部结构的平面图。本实施例的半导体器件1D特征在于:在模制树脂2外部露出的多条引线4中,源极引线由单条宽引线制成。
在本实施例中,源极引线的宽度增加使得能进一步降低导通电阻。此外,通过使得在模制树脂2外部露出的引线4的宽度更宽,改进了热辐射性能,从而可以获得具有小热阻的半导体器件1D。
实施例5
图17为示出根据本实施例的半导体器件(SOP8)1E的内部结构的平面图。本实施例的半导体器件1E特征在于:芯片焊盘部4D和引线4(第一和第二引线)利用Al带10耦合。在这种情况下,第一引线、第二引线、以及第五至第八引线用作漏极引线,第三引线用作源极引线,而第四引线用作栅极引线。
根据本实施例,热可以经由Al带10从芯片焊盘部4D释放到某些引线4(第一和第二引线)。这种热辐射性能的改进导致具有小热阻的半导体器件1E的实现。
实施例6
图18至21示出根据本实施例的半导体器件,其中图18为示出封装的顶表面的平面图,图19为示出封装的底表面的平面图,图20为示出内部结构的平面图,图21为沿C-C线所取的截面图。
根据本实施例的半导体器件1F适用于作为小表面安装封装的VSON8。从由环氧树脂制成的模制树脂40的底部露出构成VSON8的外部连接端子的八条引线41的外引线部。在图18所示的八条引线41中,第一至第三引线用作发射极引线,第四引线用作栅极引线,第五至第八引线用作集电极引线。
在根据上述实施例1-5的SOP8中,模制树脂2的外部尺寸为4.9mm×3.95mm(长边×短边),而在VSON8中,模制树脂40的外部尺寸为4.4mm×3.0mm(长边×短边)。在模制树脂40内,密封具有绝缘栅双极晶体管(IGBT)的硅芯片42(将在后文描述)。
如图20所示,硅芯片42以主表面向上的方式安装在与构成集电极引线的四条引线41(第五至第八引线)集成的芯片焊盘部41D上。硅芯片42的背面构成IGBT的集电极,并经由Ag浆料5键合到芯片焊盘部41D的顶表面。类似于上述SOP8的芯片焊盘部4D和引线4,芯片焊盘部41D和八条引线41(第一至第八引线)均由Cu或Fe-Ni合金制成。在它们的表面上,分别形成三层镀层(Ni/Pd/Au)(未示出),该镀层具有用作主成分的Pd膜以及在其上方和下方堆叠的Ni膜和Au膜。
在硅芯片42的主表面上,形成发射极焊盘(发射电极)43和栅极焊盘44。发射极焊盘43和栅极焊盘44由主要由Al膜构成、且形成为硅芯片42的最上层的导电膜制成。发射极焊盘43具有比栅极焊盘44更宽的面积,以减小IGBT的导通电阻。由于类似的理由,硅芯片42的整个背面形成IGBT的漏电极。
如图20所示,在本实施例的半导体器件1F中,构成发射极引线的三条引线41(第一至第三引线)中的两条引线41(第一和第二引线)在模制树脂40内彼此耦合,它们的耦合部经由Al带45电耦合至发射极焊盘43。也构成发射极引线的剩余引线41(第三引线)与上述两条引线41(第一和第二引线)分离,并经由Au线46电耦合至发射极焊盘43。构成栅极引线的引线41(第四引线)经由另一Au线46电耦合至栅极焊盘44。
在构成发射极引线的三条引线41(第一至第三引线)中,经由Au线46耦合至发射极焊盘43的第三引线构成用于驱动栅极的感测端子,而经由Al带45耦合至发射极焊盘43的第一和第二引线构成施加(force)端子。
如图22所示,当在IGBT的栅电极和发射极引线之间施加栅极电压时,由于电流通过被耦合至发射极引线的线,产生电压降。该电压降导致硅芯片的表面和发射极引线之间的电位差。因此,输入硅芯片的电压变小与电位差相应的量。该电位差的影响表现为电流变大或者驱动电压变低。
在本实施例中,为了克服上述问题,将发射极引线分成感测端子(第三引线)和施加端子(第一和第二引线)。感测端子(第三引线)经由Au线46耦合至发射极焊盘43,而施加端子(第一和第二引线)经由Al带45耦合至发射极焊盘43。通过采用上述结构,当在栅电极和发射极引线之间施加栅极电压时,电流在电阻低于感测端子(第三引线)的施加端子(第一和第二引线)一侧流动,而几乎不在具有较高电阻的感测端子(第三引线)一侧流动。因此,在栅电极和发射极引线之间不出现电位差,从而在栅电极和发射极引线之间施加的栅极电压几乎无损失地被输入到硅芯片中。
当将发射极引线分成感测端子(第三引线)和施加端子(第一和第二引线)时,第一和第二引线之间的耦合面积减小。这使得当并行放置宽Al带45的长边和硅芯片42的长边(沿图20的水平方向的边)时难以进行键合。图20所示的引线41中的第一和第二引线与发射极焊盘43之间位置关系,或者发射极焊盘43的小面积,特别是其在图20的垂直方向上的小宽度,影响上述困难。
在这种情况下,使用具有比图20所示的Al带45小的宽度的Al带使得能在并行排列它们的长边的情况下键合Al带和硅芯片42。但是,使用具有较小宽度的Al带减小了与引线41的接触面积,导致它们之间的接触电阻的增加。
在本实施例中,如图20所示,通过Al带45到硅芯片42一侧或者模制树脂40一侧的对角键合,实现宽Al带45到具有小面积的发射极焊盘43的表面的键合。此外,如图20所示,由于使得Al带45的一端与之键合的耦合部的宽度(A)宽于引线41的参考宽度(B),因此,即便Al带45采用对角布局,Al带45也可以稳定地耦合至引线41。
当宽Al带45键合至具有小面积的引线41的耦合部时,键合装置的夹片和引线41之间接触面积减小,从而引线41不能由夹片安全地固定,存在Al带45和引线41之间的粘合力降低的危险。在本实施例中,如图20所示,通过使得构成施加端子的一部分引线41(第一和第二引线)在构成感测端子的引线41(第三引线)和芯片焊盘部41D之间延伸,增加构成施加端子的引线41的面积。
如图23所示,上述在键合装置的夹片47和引线41(第一和第二引线)之间的接触面积的增加,使得能够通过夹片47安全地键合引线41。在Al带45在引线41(第一和第二引线)表面上的楔形键合期间,键合工具的振荡能被安全地传输到Al带45,导致Al带45和引线41之间的粘合力改进。
接着将描述形成于硅芯片42上的IGBT。图24为其上具有作为IGBT的一个实例的n沟道沟槽栅极IGBT的硅芯片42的局部截面图。
在p型收集器层60上,形成n型外延层。该n型外延层由n型缓冲层61和其上的n型漂移层(drift layer)62制成。n型漂移层61上具有p型阱63和p型基极层(base layer)64。在p型基极层64的一部分中形成多个沟槽,所述沟槽穿透p型基极层64,到达n型漂移层62。
在所述多个沟槽内侧,形成由氧化硅膜制成的栅极绝缘膜65,并在栅极绝缘膜65内侧形成栅电极66。在p型阱63上,经由氧化硅膜67形成栅极引线电极66A。栅电极65和栅极引线电极66A均由n型多晶膜制成,并且它们在未示出的区域中彼此耦合。
在p型基极层64的表面上,围绕多个沟槽形成n型发射极层68和p型接触层69。
在n沟道IGBT上,经由氧化硅膜70形成发射极焊盘43。发射极焊盘43经由形成于氧化硅膜70中的接触孔耦合至p型接触层69。在栅极引线电极66A上,经由氧化硅膜70形成栅极焊盘44。栅极焊盘44经由形成于氧化硅膜70中的接触孔耦合至栅极引线电极66A。发射极焊盘43和栅极焊盘44由例如WSi(硅化钨)膜和Al(铝)合金膜的叠层制成。
除了其中形成发射极焊盘43和栅极焊盘44的区域之外,硅芯片42的表面由钝化膜71覆盖。钝化膜71由例如氧化硅膜和氮化硅膜的叠层制成。硅芯片42在其背面具有与p型集电极层60邻接的集电极电极72。
图25示出使用本实施例的半导体器件1F的电路的一个实例。以标号73表示的是IGBT的驱动IC,74表示Xe(氙气)管,75表示触发变压器。
实施例7
图26至图29示出根据本实施例的半导体器件,其中图26为示出封装的内部结构的平面图,图27为沿图26的D-D线所取的截面图,图28为沿图26的E-E线所取的截面图,图29为沿F-F线所取的截面图。
本实施例的半导体器件1G适用于WPAK(一种小表面安装封装)。在由环氧树脂制成的模制树脂50的外部露出构成WPAK的外部连接端子的八条引线51的外引线部。在图26所示的八条引线51中,第一至第三引线是源极引线,第四引线是栅极引线,第五至第八引线是漏极引线。
在WPAK中,模制树脂50的外部尺寸为5.9mm×4.9mm(长边×短边)。类似于实施例1,其上形成有功率MOSFET的硅芯片52密封在模制树脂50内。WPAK的一个特点是:其上安装有硅芯片52的芯片焊盘部51D的背面露在模制树脂50外部,以及使得芯片焊盘部51D起到热沉的作用,以减小封装的热阻。
硅芯片52以主表面向上的方式安装在芯片焊盘部51D上,芯片焊盘部51D与构成漏极引线的四条引线51(第五至第八引线)集成。硅芯片52的背面构成功率MOSFET的漏极,并经由Ag浆料5键合到芯片焊盘部51D的上表面。芯片焊盘部51D和八条引线51(第一至第八引线)均由Cu或Fe-Ni合金制成。在它们的表面上,分别形成三层沉积层(Ni/Pd/Au)(未示出),该沉积层具有用作主成分的Pd膜以及在其上方和下方堆叠的Ni膜和Au膜。
在硅芯片52的主表面上,形成源极焊盘(源电极)53和栅极焊盘54。源极焊盘53和栅极焊盘54由主要由Al膜构成、且形成为硅芯片52的最上层的导电膜制成。源极焊盘53具有比栅极焊盘54更宽的面积,以减小功率MOSFET的导通电阻。由于类似的理由,硅芯片52的整个背面形成功率MOSFET的漏电极。
类似于实施例1的半导体器件(SOP8)1A,在本实施例的半导体器件1G中,构成源极引线的三条引线51(第一至第三引线)在模制树脂50内彼此耦合,且它们的耦合部经由Al带55电耦合至源极焊盘53。构成栅极引线的引线51(第四引线)经由一条Au线56电耦合至栅极焊盘54。
如上所述,在WPAK中,其上安装有硅芯片52的芯片焊盘部51D的背面在模制树脂50的外部露出。这种结构趋于导致如下问题:当由于它们之间的热膨胀系数差异而在模制树脂50和芯片焊盘部51D(和引线51)之间的界面处形成空间时,诸如水之类的外部物质通过该该空间渗透到模制树脂50中,破坏Ag浆料5。特别是在功率MOSFET中,硅芯片52的背面构成漏电极,因此Ag浆料5的破坏导致漏电阻的增加。
在本实施例中,作为针对上述问题的手段,沿芯片焊盘部51D的一侧(其上形成漏极引线的一侧)形成多个突起物57,如图26所示,并且这些突起物57配备有阶差(step difference)57s,如图28的放大图所示。作为另一手段,沿芯片焊盘部51D的三侧(芯片焊盘部51D除其上形成突起物57的一侧之外的三侧)形成半蚀刻部,如图28的放大图所示。阶差57s可以通过例如突起物57的压力加工来形成。半蚀刻部58可以利用蚀刻掩模通过已知的半蚀刻技术来形成。
因为通过阶差57s或半蚀刻部58可以停止由于模制树脂50和芯片焊盘部51D之间的热膨胀系数差异而导致的界面分离(界面不对准)的扩展,因此在芯片焊盘部51D的周边形成的阶差57s或半蚀刻部58对于防止界面分离有效。
针对模制树脂50和芯片焊盘部51D之间的界面分离的手段的进一步实例在图30至图32中示出,其中图30为示出封装的内部结构的平面图,图31为沿图30的G-G线所取的截面图,图32为沿图30的H-H线所取的截面图。请注意在图30中未示出硅芯片52、Al带55和Au线56。
在本实例中,沿芯片焊盘部51D的三侧(芯片焊盘部51D除沿其形成突起物57的一侧之外的三侧)形成多个突起物59,并且这些突起物59分别配备弯曲部59b,如图32的放大图所示。弯曲部59b可以通过例如使突起物59弯曲来形成。
类似于阶差57s或半蚀刻部58,在芯片焊盘部51D的周边形成的弯曲部59b防止了由于模制树脂50和芯片焊盘部51D之间的热膨胀系数差异而导致的界面分离(界面不对准)的扩展,因此它们对于防止界面分离有效。
阶差57s、半蚀刻部58和弯曲部59b可以单独形成或者组合形成。
基于某些实施例具体描述了本发明人做出的本发明。不言而喻,本发明并不限于这些实施例,可以多种方式进行修改,而不脱离本发明的范围。
例如,如图33所示,在实施例1的SOP8中,理想地,使得构成源极引线的三条引线4(第一至第三引线)的耦合部的宽度(A)宽于从模制树脂2露出的部分(外引线)的宽度(B)。这使得能够扩大Al带10和引线4之间的接触面积,从而降低它们之间的接触电阻。实施例6的VSON8和实施例7的WPAK也可以具有类似的优点。
在实施例4中,通过由宽引线构成从模制树脂2露出的引线4的源极引线(参见图16),意图获得导通电阻的降低和散热的改进。这些效果可以通过由一条宽引线构成每个源极引线和漏极引线进一步加强。
如图7所示,在硅芯片3的表面上形成许多功率MOSFET。如图35所示,可以使得Al带10和功率MOSFET之间的距离均匀,通过在源极焊盘的表面上以近似相等的间距放置Al带10,可以降低用于将Al带10耦合至功率MOSFET的源极焊盘7的电阻。
在上述实施例中,利用Ag浆料将硅芯片安装到芯片焊盘部上,但是可以利用除Ag浆料之外的球结合材料(例如,无铅(Pb)焊料)将硅芯片安装到芯片焊盘部上。
在上述实施例中,主要由Pd膜构成的镀层形成于引线框(芯片焊盘部4D和引线4)的表面上。镀层并不限于此。例如,如表2所示,与Al带耦合的源极引线的表面可以镀Ni或Pd(或裸Cu)中的任一个,与Al线耦合的栅极引线的表面可以镀Ag或Pd(或裸Cu)中的任一个,涂覆Ag浆料的芯片焊盘部的表面可以镀Ag或Pd中的任一个。因此,源极引线、栅极引线和芯片焊盘部均可以镀最适合的材料。
在上述实施例中,半导体器件适用于SOP8、VSON8或WPAK,而它可以适用于需要具有低电阻的各种小表面安装封装。此外,形成于硅芯片上的元件并不限于功率MOSFET或IGBT。
在上述实施例中,Al带用作将具有大面积的焊盘(源极焊盘或发射极焊盘)耦合至引线的材料,但是也可以使用由具有小电阻的其它金属材料(例如Au或Cu合金)制成的带。
本发明可以为用作便携式信息装置的功率控制开关或充电/放电保护电路的半导体器件所采用。

Claims (19)

1.一种半导体器件,包含:
半导体芯片,安装在引线框的芯片焊盘部上,并密封在树脂封装中;以及从所述树脂封装露出的所述引线框的外引线部,
其中所述引线框具有栅极引线、源极引线、漏极引线、以及与所述漏极引线集成的所述芯片焊盘部,
其中所述半导体芯片在其主表面上具有:栅极焊盘,耦合至功率MOSFET的栅电极;和源极焊盘,耦合至所述功率MOSFET的源极且具有比所述栅极焊盘大的面积,
其中所述半导体芯片的背面形成所述功率MOSFET的漏极,所述半导体芯片的背面利用Ag浆料键合到所述芯片焊盘部,并且
其中所述源极引线和所述源极焊盘经由Al带耦合。
2.根据权利要求1的半导体器件,其中所述Ag浆料的弹性模量(Pa)满足以下关系式:
Pa<2.6×Ag浆料的粘合厚度/允许Al带的超声键合的位移×Ag浆料的剪切强度。
3.根据权利要求1的半导体器件,其中所述Ag浆料的弹性模量落入从0.2GPa至5.3GPa的范围内,剪切强度为8.5MPa或更大。
4.根据权利要求1的半导体器件,其中所述源极引线和所述源极焊盘经由多条Al带耦合。
5.根据权利要求1的半导体器件,其中所述栅极引线和所述栅极焊盘经由Au线耦合。
6.根据权利要求1的半导体器件,其中所述栅极引线和所述栅极焊盘经由Al带耦合。
7.根据权利要求1的半导体器件,其中构成所述源极焊盘的导电膜具有3μm或更大的厚度。
8.根据权利要求1的半导体器件,其中所述源极引线的外引线部彼此整体耦合。
9.根据权利要求1的半导体器件,其中部分所述漏极引线经由所述Al带耦合至所述芯片焊盘部。
10.根据权利要求1的半导体器件,其中所述引线框在其表面上具有主要由Pd构成的镀层。
11.一种半导体器件,包含:
半导体芯片,安装在引线框的芯片焊盘部上,并密封在树脂封装中;以及从所述树脂封装露出的所述引线框的外引线部,
其中所述引线框具有栅极引线、发射极引线、集电极引线、以及与所述集电极引线集成的所述芯片焊盘部,
其中所述半导体芯片在其主表面上具有:栅极焊盘,耦合至IGBT的栅电极;和发射极焊盘,耦合至所述IGBT的发射极且具有比所述栅极焊盘大的面积,
其中所述半导体芯片的背面形成所述IGBT的漏极,所述半导体芯片的背面利用Ag浆料键合到所述芯片焊盘部,并且
其中所述发射极引线和所述发射极焊盘经由Al带耦合。
12.根据权利要求11的半导体器件,其中用于将所述发射极引线耦合至所述发射极焊盘的Al带在相对于所述树脂封装的边的对角线方向上延伸。
13.根据权利要求11的半导体器件,其中所述栅极引线和所述栅极焊盘经由Au线耦合。
14.根据权利要求13的半导体器件,其中
用于将所述发射极引线耦合至所述发射极焊盘的Al带在相对于所述树脂封装的边的对角线方向上延伸,并且
其中用于将所述栅极引线耦合至所述栅极焊盘的Au线在相对于所述树脂封装的边的对角线方向上延伸。
15.根据权利要求11的半导体器件,其中
所述发射极引线具有用于驱动栅极的施加端子和感测端子,并且
其中构成所述施加端子的发射极引线和构成所述感测端子的发射极引线彼此隔离。
16.根据权利要求15的半导体器件,其中构成所述施加端子的发射极引线的一部分在构成所述感测端子的发射极引线和所述芯片焊盘部之间延伸。
17.一种半导体器件,包含:
半导体芯片,安装在引线框的芯片焊盘部上,并密封在树脂封装中;以及从所述树脂封装露出的所述引线框的外引线部和所述芯片焊盘部的背面,
其中所述引线框具有栅极引线、源极引线、漏极引线、以及与所述漏极引线集成的所述芯片焊盘部,
其中所述半导体芯片在其主表面上具有:栅极焊盘,耦合至功率MOSFET的栅电极;和源极焊盘,耦合至所述功率MOSFET的源极且具有比所述栅极焊盘大的面积,
其中形成所述功率MOSFET的漏极的所述半导体芯片的背面利用Ag浆料键合到所述芯片焊盘部,
其中所述源极引线和所述源极焊盘经由Al带耦合,
其中所述栅极引线和所述栅极焊盘经由Au线耦合,
其中与所述芯片焊盘部集成的突起物放置在所述芯片焊盘部的周边,以及
其中所述突起物配备有阶差或弯曲部。
18.根据权利要求17的半导体器件,其中在所述芯片焊盘部的周边放置半蚀刻部来代替所述阶差或弯曲部,或与所述阶差或弯曲部组合。
19.根据权利要求1或17的半导体器件,其中密封在所述树脂封装内的源极引线的耦合部的宽度大于从所述树脂封装露出的每个源极引线的宽度。
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US20100105174A1 (en) 2010-04-29
KR20080096483A (ko) 2008-10-30
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