JP2017005165A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2017005165A JP2017005165A JP2015119233A JP2015119233A JP2017005165A JP 2017005165 A JP2017005165 A JP 2017005165A JP 2015119233 A JP2015119233 A JP 2015119233A JP 2015119233 A JP2015119233 A JP 2015119233A JP 2017005165 A JP2017005165 A JP 2017005165A
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- Prior art keywords
- lead frame
- terminal
- electrode
- main surface
- disposed
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 239000011347 resin Substances 0.000 claims abstract description 54
- 229920005989 resin Polymers 0.000 claims abstract description 54
- 238000007789 sealing Methods 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 28
- 229910000679 solder Inorganic materials 0.000 abstract description 26
- 230000017525 heat dissipation Effects 0.000 abstract description 14
- 238000005538 encapsulation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 238000001816 cooling Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
Description
実施の形態1.
図1に実施の形態1を示す。図1(a)には平面図(上面の封止樹脂は不図示)、図1(b)にはA−A’断面図、図1(c)には背面図を示す。
実施の形態2.
図2に実施の形態2を示す。図2(a)には平面図(上面の封止樹脂は不図示)、図2(b)にはB−B’断面図、図2(c)には背面図を示す。
実施の形態3.
図3には実施の形態3を示す。図3(a)には平面図(上面の封止樹脂は不図示)、図3(b)にはC−C’断面図、図3(c)には背面図を示す。
実施の形態4.
図4は実施の形態4を示す。図4(a)には平面図(上面の封止樹脂は不図示)、図4(b)にはD−D’断面図、図4(c)には背面図を示す。
実施の形態5.
図5は実施の形態5を示す。図5(a)には平面図(上面の封止樹脂は不図示)、図5(b)にはE−E’断面図、図5(c)には背面図を示す。
実施の形態6.
図6に実施の形態6を示す。図6(a)には平面図(上面の封止樹脂は不図示)、図6(b)にはF−F’断面図、図6(c)には背面図、図6(d)には基板への接続図を示す。
実施の形態7.
図7に実施の形態7を示す。図7(a)には平面図(上面の封止樹脂は不図示)、図7(b)にはG−G’断面図、図7(c)には背面図、図7(d)には基板への接続図を示す。
実施の形態8.
図8に実施の形態8を示す。図8(a)には平面図(上面の封止樹脂は不図示)、図8(b)にはH−H’断面図、図8(c)には背面図、図8(d)には基板への接続図を示す。
実施の形態9.
図9に実施の形態9を示す。図9(a)には平面図(上面の封止樹脂は不図示)、図9(b)にはI−I’断面図、図9(c)には背面図、図9(d)には基板への接続図を示
す。
実施の形態10.
図10に実施の形態10を示す。図10(a)には平面図(上面の封止樹脂は不図示)、図10(b)にはJ−J’断面図、図10(c)には背面図、図10(d)には基板への接続図を示す。
実施の形態11.
図11に実施の形態11を示す。図11(a)には平面図(上面の封止樹脂は不図示)、図11(b)にはK−K’断面図、図11(c)には背面図、図11(d)には基板への接続図を示す。
実施の形態12.
図12に実施の形態12を示す。図12(a)には平面図(上面の封止樹脂は不図示)、図12(b)にはL−L’断面図、図12(c)には背面図、図12(d)には基板への接続図を示す。
実施の形態13.
図13に実施の形態13を示す。図13(a)には平面図(上面の封止樹脂は不図示)、図13(b)にはM−M’断面図、図13(c)には背面図、図13(d)には基板への接続図を示す。
実施の形態14.
図14に実施の形態14を示す。図14(a)には平面図(上面の封止樹脂は不図示)、図14(b)にはN−N’断面図、図14(c)には背面図、図14(d)には基板への接続図を示す。
1a、1a-1、1a−2 アノード電極
1b、1b-1、1b−2 カソード電極
2 MOSFETチップ
2a ゲート電極
2b ソース電極
2c ドレイン電極
3、23、25、33、43、53、63、73 第1リードフレーム
4、24、26、34、44、54、64、74 第2リードフレーム
5、45、55 第3リードフレーム
6 ボンディングワイヤ
7 IGBTチップ
7a ゲート電極
7b エミッタ電極
7c コレクタ電極
8 FWDチップ
8a アノード電極
8b カソード電極
9 封止樹脂
11、11−1、11−2 カソード端子
12、12−1、12−2 アノード端子
13、13−1 ドレイン端子
14、14a、14b、14a−1、14b−1 ソース端子
15、15−1 ゲート端子
16、16−1 コレクタ端子
17、17a、17b、17a−1、17b−1 エミッタ端子
18 スルーホール
20 基板
21 配線パターン
201 ダイオード
202 MOSFET
301 ダイオード素子
302 カソード端子
303 アノード端子
401 MOFET素子
402 ゲート端子
403 ドレイン端子
404 ソース端子
500 配線パターン
Claims (19)
- 第1リードフレームと、
第2リードフレームと、を有する半導体装置において、
前記第1リードフレームには第1端子と、
前記第2リードフレームには第2端子と、を備え、
前記第1リードフレームの主面上には第1半導体チップと、
前記第2リードフレームの主面上には第2半導体チップと、を備え、
前記第1半導体チップの表面に配置された第1電極はボンディングワイヤによって前記第2リードフレームの前記主面上に電気的に接続され、
前記第2半導体チップの表面には第2電極と第3電極を有し、
前記第2電極はボンディングワイヤによって第3端子、および第4端子に電気的に接続され、
前記第3電極はボンディングワイヤによって第5端子に電気的に接続され、
前記第1リードフレームの他方の主面と前記第2リードフレームの他方の主面は封止樹脂から露出するように配置されていることを特徴とする半導体装置。 - 前記第1電極はボンディングワイヤによって第3リードフレームの主面に接続され、
前記第3リードフレームの前記主面はボンディングワイヤによって前記第2リードフレームの前記主面に接続し、
前記第3リードフレームの他方の主面は前記封止樹脂から露出していることを特徴とする請求項1に記載の半導体装置。 - 前記第1端子、前記第2端子、前記第3端子、前記第4端子、および前記第5端子は前記封止樹脂から露出するように配置されていることを特徴とする請求項1または2に記載の半導体装置。
- 第4リードフレームと、
第5リードフレームと、を有する半導体装置において、
前記第4リードフレームには第6端子と、
前記第5リードフレームには第7端子と、を備え、
前記第4リードフレームの主面上には第3半導体チップと、
前記第5リードフレームの主面上には第4半導体チップ、および第5半導体チップと、を備え、
前記第3半導体チップの表面に配置された第4電極はボンディングワイヤによって前記第5リードフレームの前記主面上に電気的に接続され、
前記第4半導体チップの表面には第5電極と第6電極と、
前記第5半導体チップの表面には第7電極と、を有し、
前記第5電極はボンディングワイヤによって第8端子、および第9端子に電気的に接続され、
前記第6電極はボンディングワイヤによって第10端子に電気的に接続され、
前記第7電極はボンディングワイヤによって前記第5電極に電気的に接続され、
前記第4リードフレームの他方の主面と前記第5リードフレームの他方の主面は封止樹脂から露出するように配置されていることを特徴とする半導体装置。 - 前記第4電極はボンディングワイヤによって第6リードフレームの主面に接続され、
前記第6リードフレームの前記主面はボンディングワイヤによって前記第4リードフレームの前記主面に接続し、
前記第6リードフレームの他方の主面は前記封止樹脂から露出していることを特徴とする請求項4に記載の半導体装置。 - 前記第6端子、前記第7端子、前記第8端子、前記第9端子、および前記第10端子は前記封止樹脂から露出するように配置されていることを特徴とする請求項4または5に記載の半導体装置。
- 前記第1リードフレームと前記第2リードフレームとの間にスルーホールを備えることを特徴とする請求項1に記載の半導体装置。
- 第7リードフレームと、
第8リードフレームと、を有する半導体装置において、
前記第8リードフレームには第11端子と、を備え、
前記第7リードフレームの主面上には第6半導体チップと、
前記第8リードフレームの主面上には第7半導体チップと、を備え、
前記第6半導体チップの表面に配置された第8電極はボンディングワイヤによって前記第8リードフレームの前記主面上に電気的に接続され、
前記第7半導体チップの表面には第9電極と第10電極を有し、
前記第9電極はボンディングワイヤによって第12端子、および第13端子に電気的に接続され、
前記第10電極はボンディングワイヤによって第14端子に電気的に接続され、
前記第7リードフレームの他方の主面と前記第8リードフレームの他方の主面は封止樹脂から露出するように配置されていることを特徴とする半導体装置。 - 前記第8電極はボンディングワイヤによって第9リードフレームの主面に接続され、
前記第9リードフレームの前記主面はボンディングワイヤによって前記第8リードフレームの前記主面に接続し、
前記第9リードフレームの他方の主面は前記封止樹脂から露出していることを特徴とする請求項8に記載の半導体装置。 - 前記第11端子、前記第12端子、前記第13端子、および前記第14端子は前記封止樹脂から露出するように配置されていることを特徴とする請求項8または9に記載の半導体装置。
- 前記第7リードフレームの前記他方の主面は基板上に配置された配線パターンと電気的に接続することを特徴とする請求項8または9に記載の半導体装置。
- 第10リードフレームと、
第11リードフレームと、を有する半導体装置において、
前記第11リードフレームには第15端子と、を備え、
前記第10リードフレームの主面上には第8半導体チップと、
前記第11リードフレームの主面上には第9半導体チップ、および第10半導体チップと、を備え、
前記第8半導体チップの表面に配置された第11電極はボンディングワイヤによって前記第11リードフレームの前記主面上に電気的に接続され、
前記第9半導体チップの表面には第12電極と第13電極と、
前記第10半導体チップの表面には第14電極と、を有し、
前記第12電極はボンディングワイヤによって第16端子、および第17端子に電気的に接続され、
前記第13電極はボンディングワイヤによって第18端子に電気的に接続され、
前記第14電極はボンディングワイヤによって前記第12電極に電気的に接続され、
前記第10リードフレームの他方の主面と前記第11リードフレームの他方の主面は封止樹脂から露出するように配置されていることを特徴とする半導体装置。 - 前記第11電極はボンディングワイヤによって第12リードフレームの主面に接続され、
前記第12リードフレームの前記主面はボンディングワイヤによって前記第11リードフレームの前記主面に接続し、
前記第12リードフレームの他方の主面は前記封止樹脂から露出していることを特徴とする請求項12に記載の半導体装置。 - 前記第15端子、前記第16端子、前記第17端子、および前記第18端子は前記封止樹脂から露出するように配置されていることを特徴とする請求項12または13に記載の半導体装置。
- 前記第10リードフレームの前記他方の主面は基板上に配置された配線パターンと電気的に接続することを特徴とする請求項12または13に記載の半導体装置。
- ダイオード+ダイオード、図8
第13リードフレームと、
第14リードフレームと、を有する半導体装置において、
前記第14リードフレームには第19端子と、を備え、
前記第13リードフレームの主面上には第11半導体チップと、
前記第14リードフレームの主面上には第12半導体チップと、を備え、
前記第11半導体チップの表面に配置された第15電極はボンディングワイヤによって前記第14リードフレームの前記主面上に電気的に接続され、
前記第12半導体チップの表面には第16電極と、を有し、
前記第16電極はボンディングワイヤによって第20端子に電気的に接続され、
前記第13リードフレームの他方の主面と前記第14リードフレームの他方の主面は封止樹脂から露出するように配置されていることを特徴とする半導体装置。 - ダイオード+ダイオード、図13
前記第16電極は、前記第19端子の両側に配置された前記第20端子にワイヤボンディングによって電気的に接続されていることを特徴とする請求項16に記載の半導体装置。 - 前記第19端子、および前記第20端子は、前記封止樹脂から露出するように配置されていることを特徴とする請求項16または17に記載の半導体装置。
- 前記第13リードフレームの前記他方の主面は基板上に配置された配線パターンと電気的に接続することを特徴とする請求項16乃至18のいずれか1つに記載の半導体装置。
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JP2015119233A JP6520437B2 (ja) | 2015-06-12 | 2015-06-12 | 半導体装置 |
CN201610404477.5A CN106252320B (zh) | 2015-06-12 | 2016-06-08 | 半导体装置 |
US15/177,827 US9754863B2 (en) | 2015-06-12 | 2016-06-09 | Semiconductor device |
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CN106252320A (zh) | 2016-12-21 |
CN106252320B (zh) | 2020-10-27 |
US9754863B2 (en) | 2017-09-05 |
JP6520437B2 (ja) | 2019-05-29 |
US20160365303A1 (en) | 2016-12-15 |
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