TWM456043U - 電力開關裝置 - Google Patents

電力開關裝置 Download PDF

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Publication number
TWM456043U
TWM456043U TW101213435U TW101213435U TWM456043U TW M456043 U TWM456043 U TW M456043U TW 101213435 U TW101213435 U TW 101213435U TW 101213435 U TW101213435 U TW 101213435U TW M456043 U TWM456043 U TW M456043U
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Taiwan
Prior art keywords
transistor
drain
coupled
pad
source
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TW101213435U
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English (en)
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Hsiang-Chi Meng
Tien-Chien Chang
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Ubiq Semiconductor Corp
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Priority to TW101213435U priority Critical patent/TWM456043U/zh
Priority to CN2013200929841U priority patent/CN203179873U/zh
Publication of TWM456043U publication Critical patent/TWM456043U/zh

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    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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Description

電力開關裝置
本創作與半導體元件封裝有關，特別是關於一種電力開關裝置。
一般而言，傳統的電力開關封裝結構中所採用之金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor,MOSFET)均為具有溝槽(trench)結構之金屬氧化物半導體場效電晶體。也就是說，傳統的電力開關封裝結構中之金屬氧化物半導體場效電晶體的源極設置於上方而其汲極則設置於下方。
請參照圖1A及圖1B，圖1A及圖1B分別繪示傳統的降壓型轉換器(buck converter)封裝結構之上視圖及剖面視圖。如圖所示，位於高側(high side)的第一電晶體M1與位於低側(low side)的第二電晶體M2均為傳統的具有溝槽結構之金屬氧化物半導體場效電晶體，第一電晶體M1與第二電晶體M2之源極S1、S2均設置於上方且第一電晶體M1與第二電晶體M2之汲極D1、D2則均設置於下方。
由於第一電晶體M1的源極S1設置於上方，但第二電晶體M2之汲極D2設置於下方，為了要將第一電晶體M1的源極S1與第二電晶體M2之汲極D2相連，即需如同圖1所示透過導線W形成第一電晶體M1的源極S1與第二電晶體M2之汲極D2之間的耦接，以形成多晶片模組(Multi-Chip Module, MCM)型態之封裝結構。然而，採用上述導線耦接方式不僅會增加電路佈局及後段製程之複雜度，亦會導致漏感(leakage conductance)變大。此外，對於印刷電路板PCB之電路佈局而言，由於第二電晶體M2之源極S2設置於第二電晶體M2的上方，導致其散熱效果差。
因此，本創作提出一種電力開關裝置，以解決先前技術所遭遇到之上述種種問題。
本創作之一範疇在於提出一種電力開關裝置。於一具體實施例中，電力開關裝置包含基板、第一電晶體及第二電晶體。基板具有第一焊墊、第二焊墊及第三焊墊。第一電晶體具有第一表面與第二表面。第一電晶體之源極形成於第一電晶體之第一表面。第二電晶體為橫向擴散金屬氧化物半導體場效電晶體。第二電晶體具有第一表面與第二表面。第二電晶體之汲極形成於第二電晶體之第一表面。第一電晶體之第二表面耦接第一焊墊，第二電晶體之第二表面耦接第二焊墊，第三焊墊耦接第一電晶體之源極與第二電晶體之汲極。
於一實施例中，第三焊墊透過帶式連接(ribbon bond)的方式來耦接第一電晶體之源極與第二電晶體之汲極。
於一實施例中，第一電晶體為具有溝槽結構或平面結構之金屬氧化物半導體場效電晶體。
於一實施例中，第一電晶體之汲極形成於第一電晶體之第二表面。
於一實施例中，第二電晶體之源極形成於第二電晶體之第二表面。
於一實施例中，第二焊墊耦接一接地端。
於一實施例中，第一電晶體之源極與第二電晶體之汲極透過導電部彼此耦接。
於一實施例中，電力開關裝置還包含控制器，分別耦接第一電晶體與第二電晶體。
於一實施例中，電力開關裝置還包含封裝膠體，用以包覆第一電晶體與第二電晶體。
相較於先前技術，本創作所揭露之電力開關裝置係採用與傳統不同的橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor,LDMOS)場效電晶體作為位於低側(low side)的電晶體，以形成多晶片模組(Multi-Chip Module,MCM)型態之封裝結構，可應用於全橋(full bridge)、半橋(half bridge)或降壓型轉換器(buck converter)等電路結構。LDMOS場效電晶體本身即具有下列優點：熱穩定性佳、頻率穩定性高、高增益、耐久性佳、低噪音、低回饋電容、低汲極-源極導通電阻值(on-resistance,RDS(ON) )、偏流電路簡單、輸入阻抗恒定及低熱阻等。
由於本創作之電力開關裝置採用帶式連接(ribbon bond)等方式耦接位於高側之電晶體的源極與位於低側之電晶體的汲極，故能夠有效降低傳統上採用導線耦接兩電晶體所導致之漏感，並可大幅簡化電路佈局及後段製程之複雜度。再者，對於印刷電路板之電路佈局而言，由於位於低側之電晶體的源極設置於下方，故其相對應之接地墊(ground pad)面積遠較先前 技術來得大，使得其散熱效率亦能獲得大幅提昇。
關於本創作之優點與精神可以藉由以下的創作詳述及所附圖式得到更的瞭解。
根據本創作之一較佳具體實施例為一種之電力開關裝置。於此實施例中，該電力開關裝置具有多晶片模組(Multi-Chip Module,MCM)型態之封裝結構，可應用於全橋(full bridge)、半橋(half bridge)或降壓型轉換器(buck converter)等電路結構，但不以此為限。
請參照圖2A及圖2B，圖2A及圖2B分別繪示此實施例之電力開關裝置的上視圖及剖面視圖。需說明的是，為了顯示方便起見，圖2A省略了封裝膠體的部分。如圖所示，電力開關裝置2設置於基板PCB(例如印刷電路板)上。基板PCB具有第一焊墊R1、第二焊墊R2及第三焊墊R3。第二焊墊R2耦接一接地端。電力開關裝置2包含有位於高側(high side)的第一電晶體M1、位於低側(low side)的第二電晶體M2、導電部C及封裝膠體GL。
於此實施例中，位於高側的第一電晶體M1採用的是具有溝槽(trench)結構或平面(planar)結構之金屬氧化物半導體場效電晶體；位於低側的第二電晶體M2採用的是橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor,LDMOS)場效電晶體。相較於傳統的金屬氧化物半導體場效電晶體，位於低側的第二電晶體M2所採用之LDMOS場效電晶體本身即具有下列優點：熱穩定性佳、頻率穩定性高、高增益、 耐久性佳、低噪音、低回饋電容、低汲極-源極導通電阻值(RDS(ON) )、偏流電路簡單、輸入阻抗恒定及低熱阻等。
位於高側的第一電晶體M1具有閘極G1、源極S1及汲極D1；位於低側的第二電晶體M2具有閘極G2、源極S2及汲極D2。位於高側的第一電晶體M1之閘極G1與源極S1形成於第一電晶體M1之第一表面(較遠離基板PCB)，而其汲極D1形成於第一電晶體M1之第二表面(較靠近基板PCB)；位於低側的第二電晶體M2之閘極G2與汲極D2形成於第二電晶體M2之第一表面(較遠離基板PCB)，而其源極S2形成於第二電晶體M2之第二表面(較靠近基板PCB)。
導線架LF1設置於第一電晶體M1之汲極D1與基板PCB之第一焊墊R1之間。導線架LF2設置於第二電晶體M2之源極S2與基板PCB之第二焊墊R2之間。第三焊墊R3透過導線架LF耦接第一電晶體M1之源極S1與第二電晶體M2之汲極D2。
於此實施例中，位於高側的第一電晶體M1之源極S1形成於第一電晶體M1之第一表面且位於低側的第二電晶體M2之汲極D2形成於第二電晶體M2之第一表面，亦即電力開關裝置2內之欲形成耦接的第一電晶體M1之源極S1與第二電晶體M2之汲極D2均位於電晶體上方的第一表面，此實施例中之導電部C採用的是材質較軟的鋁帶(Aluminum ribbon)，並可透過帶式連接(ribbon bond)的方式耦接第一電晶體M1之源極S1上、第二電晶體M2之汲極D2上以及導線架LF上，以形成多晶片模組(Multi-Chip Module,MCM)型態之封裝結構。
由於第一電晶體M1之源極S1與第二電晶體M2之汲極 D2之間採用鋁帶連接方式耦接，故能夠有效降低傳統上採用導線耦接兩電晶體所導致之漏感，並可大幅簡化電路佈局及後段製程之複雜度。至於封裝膠體GL用以將第一電晶體M1、第二電晶體M2及導電部C等元件包覆於導線架上。實際上，封裝膠體GL可以是樹脂或其他塑膠封裝材料，並無特定之限制。
如圖2B所示，第一電晶體M1之汲極D1與基板PCB之間設置有導線架(lead frame)LF1；第二電晶體M2之源極S2與基板PCB之間設置有導線架LF2；導電部C與基板PCB之間設置有導線架LF。於此實施例中，導線架LF1、LF2及LF由銅構成，但不以此為限。此外，導線架LF1與基板PCB之間、導線架LF2與基板PCB之間以及導線架LF與基板PCB之間均設置有焊料(solder)R，以增進彼此間之連接性。
位於低側之第二電晶體M2的源極S2設置於第二電晶體M2的下方，可直接透過導線架LF2耦接至基板PCB，因此，如圖2B所示，導線架LF2相對應之接地墊面積A’將會遠較圖1B所示之先前技術中的接地墊面積A來得大，故能大幅提昇其散熱效率。
至於圖2C則繪示包含上述串接之兩電晶體M1及M2與控制器20之降壓型轉換器電路的一實施例。如圖2C所示，控制器20分別耦接至位於高端的第一電晶體M1、位於低端的第二電晶體M2以及輸入電壓VIN 與第一電晶體M1之間。二極體d1之兩端分別耦接至第一電晶體M1與第二電晶體M2之間以及第二電晶體M2與接地端之間。電感器L1之兩端分別耦接至第一電晶體M1與第二電晶體M2之間以及輸出電壓VOUT 。電容器C1之兩端分別耦接至電感器L1與輸出電壓VOUT 之間以及接地端。在一些實施例中，控制器20可以是含有驅動器的脈寬調變控制器(PWM controller)或驅動器(Driver)，但不以此為限。
圖2D則繪示控制器20採用帶式連接(ribbon bond)方式分別耦接第一電晶體M1及第二電晶體M2，第一電晶體M1及第二電晶體M2之間亦採用帶式連接方式耦接。如圖2D所示，控制器20透過鋁帶C分別耦接第一電晶體M1的閘極G1及第二電晶體M2的閘極G2，並且第一電晶體M1之源極S1與第二電晶體M2之汲極D2之間亦透過鋁帶C耦接。在其他實施例中，控制器20可透過打線連接(wire bond)方式來分別耦接第一電晶體M1的閘極G1及第二電晶體M2的閘極G2。
至於圖2E則繪示控制器20透過鋁帶C分別耦接第一電晶體M1的閘極G1及第二電晶體M2的閘極G2，在其他實施例中，控制器20可透過打線連接(wire bond)方式來分別耦接第一電晶體M1的閘極G1及第二電晶體M2的閘極G2。此外，第一電晶體M1之源極S1與第二電晶體M2之汲極D2之間亦透過鋁帶C耦接之外，第二電晶體M2的汲極D2還透過另一鋁帶C耦接導線架LF，藉以增加導通內阻(Rds_on)。實際上，上述耦接第二電晶體M2的汲極D2與導線架LF以增加導通內阻之作法亦可應用於本創作之其他實施例中。
接著，將就形成於基板PCB上之電力開關裝置2的封裝流程進行說明。首先，如圖3A所示，分別提供導線架LF1、LF2及LF。接著，如圖3B及圖3C所示，分別於導線架LF1及LF2上設置第一電晶體M1及第二電晶體M2。
接著，如圖3D所示，將導電部C(鋁帶)設置於第一電晶 體M1之源極S1上、第二電晶體M2之汲極D2上及導線架LF上。之後，如圖3E所示，使用封裝膠體GL將圖3D所示之各元件包覆起來，並且封裝膠體GL的底部與導線架LF1、LF2及LF之底部對齊。然後，如圖3F所示，分別形成第一焊料R1、第二焊料R2及第三焊料R3於導線架LF1、LF2及LF之底部上，完成電力開關裝置2。最後，如圖3G所示，將完成的電力開關裝置2設置於基板CPB上。
根據本創作之另一較佳具體實施例為一種之電力開關裝置。於此實施例中，該電力開關裝置具有多晶片模組型態之封裝結構，可應用於全橋、半橋或降壓型轉換器等電路結構，但不以此為限。
請參照圖4A及圖4B，圖4A及圖4B分別繪示此實施例之電力開關裝置的上視圖及剖面視圖。如圖所示，此實施例與上述實施例之差異在於：圖4A及圖4B中之導電部C’係由一銅片或金屬薄片構成，導電部C’即可設置於第一電晶體M1之源極S1與第二電晶體M2之汲極D2之上，並且導電部C’與第一電晶體M1之源極S1之間、導電部C’與第二電晶體M2之汲極D2之間以及導電部C’與導線架LF之間設置有焊料(solder)R，以增進彼此間之連接性。
由於第一電晶體M1之源極S1與第二電晶體M2之汲極D2之間採用金屬導電元件進行耦接，故能夠有效降低傳統上採用導線耦接兩電晶體所導致之漏感，並可大幅簡化其電路佈局及後段製程之複雜度。此外，位於低側之第二電晶體M2的源極S2設置於第二電晶體M2的下方，可直接透過導線架LF2耦接至基板PCB，因此，如圖4B所示，導線架LF2相對應之接地墊面積A’將會遠較圖1B所示之先前技術中的接地墊面 積A來得大，故能大幅提昇其散熱效率。
根據本創作之另一具體實施例為一種之電力開關裝置。於此實施例中，該電力開關裝置具有多晶片模組型態之封裝結構，可應用於全橋、半橋或降壓型轉換器等電路結構，但不以此為限。
請參照圖5A及圖5B，圖5A及圖5B分別繪示此實施例之電力開關裝置的上視圖及剖面視圖。如圖所示，此實施例與上述實施例之差異在於：圖5A及圖5B中之導電部C”採用的是銅線或金線，並可直接銲於第一電晶體M1之源極S1與第二電晶體M2之汲極D2之間，以及第二電晶體M2之汲極D2與導線架LF之間，不需於其間設置任何焊料。
位於低側之第二電晶體M2的源極S2設置於第二電晶體M2的下方，可直接透過導線架LF2耦接至基板PCB，因此，如圖4B所示，導線架LF2相對應之接地墊面積A’將會遠較圖1B所示之先前技術中的接地墊面積A來得大，故能大幅提昇其散熱效率。
相較於先前技術，本創作所揭露之電力開關裝置係採用與傳統不同的橫向擴散金屬氧化物半導體(LDMOS)場效電晶體作為位於低側的電晶體，以形成多晶片模組型態之封裝結構，可應用於全橋、半橋或降壓型轉換器等電路結構中。LDMOS場效電晶體本身即具有下列優點：熱穩定性佳、頻率穩定性高、高增益、耐久性佳、低噪音、低回饋電容、偏流電路簡單、輸入阻抗恒定及低熱阻等。
由於本創作之電力開關裝置採用帶式連接等方式耦接位於高側之電晶體的源極與位於低側之電晶體的汲極，故能夠有 效降低傳統上採用導線耦接兩電晶體所導致之漏感，並可大幅簡化電路佈局及後段製程之複雜度。再者，對於印刷電路板之電路佈局而言，由於位於低側之電晶體的源極設置於下方，故其相對應之接地墊面積遠較先前技術來得大，使得其散熱效率亦能獲得大幅提昇。
藉由以上較佳具體實施例之詳述，希望能更加清楚描述本創作之特徵與精神，而並非以上述所揭露的較佳具體實施例來對本創作之範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本創作所欲申請之專利範圍的範疇內。
M1‧‧‧第一電晶體
M2‧‧‧第二電晶體
S1、S2‧‧‧源極
D1、D2‧‧‧汲極
W‧‧‧導線
PCB‧‧‧基板(印刷電路板)
2、4、5‧‧‧電力開關裝置
R‧‧‧焊料
C、C’、C”‧‧‧導電部
GL‧‧‧封裝膠體
G1、G2‧‧‧閘極
R1‧‧‧第一焊墊
R2‧‧‧第二焊墊
R3‧‧‧第三焊墊
LF1、LF2、LF‧‧‧導線架
A、A’‧‧‧接地墊面積
20‧‧‧控制器
VIN ‧‧‧輸入電壓
d1‧‧‧二極體
L1‧‧‧電感器
C1‧‧‧電容器
VOUT ‧‧‧輸出電壓
圖1A及圖1B分別繪示傳統的降壓型轉換器封裝結構之上視圖及剖面視圖。
圖2A及圖2B分別繪示根據本創作之一較佳具體實施例之電力開關裝置的上視圖及剖面視圖。
圖2C繪示包含串接之兩電晶體與控制器之降壓型轉換器電路。
圖2D繪示控制器採用帶式連接方式分別耦接第一電晶體及第二電晶體，並且第一電晶體及第二電晶體之間亦採用帶式連接方式耦接的上視圖。
圖2E繪示控制器還透過鋁帶耦接第二電晶體的汲極與導線架，藉以增加第二電晶體之導通內阻的上視圖。
圖3A至圖3G分別繪示製造電力開關裝置於基板上之流 程圖。
圖4A及圖4B分別繪示根據本創作之另一具體實施例之電力開關裝置的上視圖及剖面視圖。
圖5A及圖5B分別繪示根據本創作之另一具體實施例之電力開關裝置的上視圖及剖面視圖。
M1‧‧‧第一電晶體
M2‧‧‧第二電晶體
S1、S2‧‧‧源極
D1、D2‧‧‧汲極
PCB‧‧‧基板(印刷電路板)
2‧‧‧電力開關裝置
A’‧‧‧接地墊面積
GL‧‧‧封裝膠體
C‧‧‧導電部
R1、R2、R3‧‧‧焊料
LF1、LF2、LF‧‧‧導線架

Claims (9)

  1. 一種電力開關裝置，包含：一基板，具有一第一焊墊、一第二焊墊及一第三焊墊；一第一電晶體，具有一第一表面與一第二表面，該第一電晶體之源極形成於該第一電晶體之該第一表面；以及一第二電晶體，為一橫向擴散金屬氧化物半導體場效電晶體，該第二電晶體具有一第一表面與一第二表面，該第二電晶體之汲極形成於該第二電晶體之該第一表面，其中該第一電晶體之該第二表面耦接該第一焊墊，該第二電晶體之該第二表面耦接該第二焊墊，該第三焊墊耦接該第一電晶體之源極與該第二電晶體之汲極。
  2. 如申請專利範圍第1項所述之電力開關裝置，其中該第三焊墊透過帶式連接的方式來耦接該第一電晶體之源極與該第二電晶體之汲極。
  3. 如申請專利範圍第1項所述之電力開關裝置，其中該第一電晶體為具有溝槽結構或平面結構之金屬氧化物半導體場效電晶體。
  4. 如申請專利範圍第1項所述之電力開關裝置，其中該第一電晶體之汲極形成於該第一電晶體之該第二表面。
  5. 如申請專利範圍第1項所述之電力開關裝置，其中該第二電 晶體之源極形成於該第二電晶體之該第二表面。
  6. 如申請專利範圍第1項所述之電力開關裝置，其中該第二焊墊耦接一接地端。
  7. 如申請專利範圍第1項所述之電力開關裝置，其中該第一電晶體之源極與該第二電晶體之汲極透過一導電部彼此耦接。
  8. 如申請專利範圍第1項所述之電力開關裝置，還包含：一控制器，分別耦接該第一電晶體與該第二電晶體。
  9. 如申請專利範圍第1項所述之電力開關裝置，還包含：一封裝膠體，用以包覆該第一電晶體與該第二電晶體。
TW101213435U 2012-07-12 2012-07-12 電力開關裝置 TWM456043U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI708529B (zh) * 2019-09-12 2020-10-21 崧虹科技股份有限公司 具有切換開關之焊接點
EP4261878A1 (en) * 2022-04-13 2023-10-18 Infineon Technologies Austria AG Multi-chip device with gate redistribution structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10666140B2 (en) 2016-08-22 2020-05-26 Infineon Technologies Americas Corp. Power converter with at least five electrical connections on a side

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI708529B (zh) * 2019-09-12 2020-10-21 崧虹科技股份有限公司 具有切換開關之焊接點
EP4261878A1 (en) * 2022-04-13 2023-10-18 Infineon Technologies Austria AG Multi-chip device with gate redistribution structure

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