TWI385769B - 用於高效直流-直流功率轉換器的高壓側和低壓側ｎ溝道金屬氧化物半導體場效應電晶體組合封裝 - Google Patents

用於高效直流-直流功率轉換器的高壓側和低壓側ｎ溝道金屬氧化物半導體場效應電晶體組合封裝 Download PDF

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TWI385769B
TWI385769B TW097131488A TW97131488A TWI385769B TW I385769 B TWI385769 B TW I385769B TW 097131488 A TW097131488 A TW 097131488A TW 97131488 A TW97131488 A TW 97131488A TW I385769 B TWI385769 B TW I385769B
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Taiwan
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pad
gate
source
field effect
effect transistor
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TW097131488A
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English (en)
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TW200910555A (en
Inventor
Hebert Francois
Zhang Xiaotian
Liu Kai
Sun Ming
Bhalla Anup
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Alpha & Omega Semiconductor
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Dc-Dc Converters (AREA)

Description

用於高效直流-直流功率轉換器的高壓側和低壓側N溝道金 屬氧化物半導體場效應電晶體組合封裝
本發明涉及半導體元件，尤其涉及用於高效直流-直流功率轉換器的高壓側和低壓側金屬氧化物半導體場效應電晶體(MOSFETs)組合封裝。
為了進一步縮小功率元件的尺寸，提高功率元件的效率和減少直流-直流功率轉換電路中封裝的數量和成本，傳統的技術面臨了一些技術困境和限制。在MOSFET功率組件領域大家熟知的是N溝道電晶體(NMOSFET)，其可被相對於源極電壓的正向柵極電壓驅動而導通。另外，還有P溝道MOSFETs(PMOSFET)其可被相對於源極電壓的負向柵極電壓驅動而導通。
使用NMOSFET功率元件的傳統功率轉換器一般最少需要三個元件：柵極驅動器積體電路、高壓側NMOSEFT和低壓側NMOSFET。通常，高壓側NMOSFETs和低壓側NMOSFETs使用兩個不同的分立封裝或者分別設置在同一個封裝內的兩個不同的晶片襯墊上，這種封裝方式就需要更大的封裝空間。使用兩個不同的晶片襯墊還導致了更多的寄生電阻和電容，並且由於晶片襯墊尺寸減小，從而增加了其熱電阻。晶片襯墊是指用來貼附MOSFET的裸露的金屬區域。另外，使用功率轉換器的元件的小型化趨勢使得晶片襯墊的可用尺寸越來越小，結果導致了低壓側和高 壓側晶片尺寸縮小，其導致了漏源開態電阻的增加。
第1圖是現有技術用於功率轉換器的包括低壓側和高壓側NMOSFETs的封裝的俯視圖。如第1圖所示，高壓側標準垂直雙擴散金屬氧化物半導體場效應電晶體(VDMOSFET)102有一個汲極連接到位於底面上的汲極襯墊(未顯示)，該襯墊面向導電的第一晶片襯墊106。汲極襯墊可通過一個導電環氧層118連接到第一晶片襯墊106。第二低壓側標準VDMOSFET 104用作低壓側NMOSFET。在本文中，除非明確指出其他情況，VDMOSFET是指N溝道VDMOSFET。而標準VDMOSFET是指底部汲極VDMOSFET，除了明確指出的例外情況，一般是指源極形成於晶片的頂部而汲極形成於襯底處的VDMOSFET。傳統的VDMOSFET組件是底部汲極。低壓側標準VDMOSFET 104有一個汲極通過底部汲極襯墊(未顯示)電連接和物理連接於晶片襯墊108，連接方式採用諸如導電環氧層120或者其他晶片貼附方式如焊料球或者共晶粘結。位於高壓側標準VDMOSFET 102的背向第一晶片襯墊106側的頂面上的源極襯墊107，通過鍵合線114電連接到源極引線110。類似地，低壓側標準VDMOSFET104的頂部源極襯墊109通過鍵合線116電連接於源極引線112。通過位於NMOSFETs 102,104背向晶片襯墊106，108一側的柵極襯墊103，105可分別電連接到高壓側NMOSFET 102和低壓側NMOSFET 104的柵極。在功率轉換封裝中，高壓側源極和低壓側汲極一般是互相連接的。 在傳統封裝中，上述連接是通過第二晶片襯墊108和高壓側VDMOSFET102的源極襯墊107之間的額外鍵合線122實現的。額外鍵合線122增加了寄生電感，從而妨礙了高效運轉。這個封裝包括一個模塑膠將所有的元件包裝起來。封裝的邊界用虛線101指示出來。
為了隔離第一晶片襯墊和第二晶片襯墊106、108，他們必須被安裝到一個電絕緣材料上並且相互之間間隔有寬度為D的間隙。兩個隔離晶片襯墊106和108之間的寬度d導致了可用的晶片放置區的減少。為了在較小的區域內安裝NMOSFETs，需要使用更小的高壓側和低壓側NMOSFET。這就導致了高壓側和低壓側晶片尺寸的減少，並因此增加了汲極開態電阻R ds-on。晶片襯墊尺寸的減少還導致了熱電阻的增加。
如果一個是NMOSFET，而另一個是PMOSFET，那麼高壓側和低壓側MOSFET可以設置在同一個晶片襯墊上。然而由於PMOSFET上通孔的移動性較低，P溝道MOSFET(PMOFET)的性能比N溝道MOSFET(NMOSFET)的性能要差很多。這是本領域內的技術人員所熟知的。
本發明的目的是提供一種用於高效直流-直流功率轉換器的高壓側和低壓側N溝道金屬氧化物半導體場效應電晶體組合封裝。本發明的優點是可以進一步縮小功率元件的尺寸、寄生電感和電容，並能提高功率元件的效率和減少 直流-直流功率轉換電路中封裝的數量和成本。
為達上述目的，本發明公開了一種電路封裝元件，其特徵在於，該電路封裝元件包括一個共同晶片襯墊；一個具有源極電觸點的第一垂直N溝道金屬氧化物半導體場效應電晶體，所述的源極位於面向共同晶片襯墊表面的一側且電接觸該共同晶片襯墊；一個具有汲極電觸點的第二垂直N溝道金屬氧化物場效應電晶體，所述的汲極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊。
所述的第一N溝道金屬氧化物半導體場效應電晶體是一個高壓側N溝道金屬氧化物半導體場效應電晶體，所述的第二N溝道金屬氧化物半導體場效應電晶體是一個低壓側N溝道金屬氧化物半導體場效應電晶體。
所述的高壓側N溝道金屬氧化物半導體場效應電晶體包括一個底部源極N溝道橫向雙擴散N溝道金屬氧化物半導體場效應電晶體，而所述的低壓側N溝道金屬氧化物半導體場效應電晶體包括一個底部汲極N溝道垂直雙擴散N溝道金屬氧化物半導體場效應電晶體。
所述的高壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊和汲極襯墊都位於高壓側N溝道金屬氧化物半導體場效應電晶體背對共同晶片襯墊的一側，而所述的柵極襯墊和汲極襯墊分別電連接到各自的柵極引線。
所述的第二N溝道金屬氧化物半導體場效應電晶體的柵極襯墊和源極襯墊分別通過若干鍵合線分別連接到各自的柵極引線和源極引線。
所述的高壓側N溝道金屬氧化物半導體場效應電晶體的汲極襯墊和低壓側N溝道金屬氧化物半導體場效應電晶體的源極襯墊分別位於高壓側N溝道金屬氧化物半導體場效應電晶體和低壓側N溝道金屬氧化物半導體場效應晶體背對共同晶片襯墊的一側，而所述的各自的汲極襯墊和源極襯墊則分別通過第一和第二連接金屬板連接到汲極和源極引線。
所述的第一連接金屬板包括若干形成於其上的第一凹槽，該凹槽將汲極引線連接到高壓側N溝道金屬氧化物半導體場效應電晶體的汲極襯墊，該凹槽置於連接金屬板上以提供和汲極的連接；所述的第二連接金屬板包括若干第二凹槽，該凹槽將源極引線連接到低壓側N溝道金屬氧化物半導體場效應電晶體的源極襯墊，該凹槽置於連接金屬板上以提供和源極的連接。
所述的若干第一凹槽和第二凹槽分別焊接到汲極襯墊和源極襯墊上。
所述的高壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊和低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊分別通過鍵合線連接到柵極引線，所述的高壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊和低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊則分別通過高壓側和低壓側連接金屬板連接到柵極引線。
所述的高壓側柵極連接金屬板包括一個形成在其上的凹槽，該凹槽置於和高壓側N溝道金屬氧化物半導體場效 應電晶體上的柵極襯墊接觸的位置；所述的低壓側柵極連接金屬板包括一個形成在其上的凹槽，該凹槽將柵極引線連接到低壓側N溝道金屬氧化物半導體場效應電晶體上的柵極襯墊，凹槽置於和低壓側N溝道金屬氧化物半導體場效應電晶體上的柵極襯墊接觸的位置。
所述的凹槽焊接到低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊上。
所述的高壓側N溝道金屬氧化物半導體場效應電晶體的汲極襯墊位於背對共同晶片襯墊上的一側，所述的低壓側N溝道金屬氧化物半導體場效應電晶體的源極襯墊位於背對共同晶片襯墊的一側，所述的汲極襯墊和源極襯墊分別通過一根或者多根鋁電源排線連接到汲極引線和源極引線。
所述的高壓側N溝道金屬氧化物半導體場效應電晶體和低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊分別通過鍵合線電連接到柵極引線，所述的高壓側N溝道金屬氧化物半導體場效應電晶體和低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊分別通過連接金屬板或者電源排線連接到柵極引線。
所述高壓側N溝道金屬氧化物半導體場效應電晶體是一個底部汲極N溝道金屬氧化物半導體場效應電晶體，其在底部上具有一個或者多個汲極襯墊，以及一個柵極襯墊，在頂部有一個或者多個源極襯墊，以倒裝晶片的方式安裝在共同晶片襯墊上，倒裝晶片是指晶片頂部接近兵並 面向共同晶片襯墊，即柵極襯墊和一個或多個源極襯墊接近並面向共同晶片襯墊。
所述的高壓側倒裝N溝道金屬氧化物半導體場效應電晶體的汲極襯墊和低壓側N溝道金屬氧化物半導體場效應電晶體的一個或者多個源極襯墊分別通過相應的高壓側和低壓側連接金屬板電連接到相應的汲極引線和源極引線。
所述的倒裝晶片連接金屬板包括若干形成在連接金屬板之上的凹槽，該凹槽被應用於將汲極引線連接到高壓側倒裝N溝道金屬氧化物半導體場效應電晶體的一個或者多個汲極襯墊，該凹槽位於與汲極襯墊接觸的位置。
所述的高壓側倒裝N溝道金屬氧化物半導體場效應電晶體還包括利用一個或者多個焊料球形成的柵極和源極之間的電連接。
所述的低壓側源極連接金屬板包括一個連接金屬板，該連接金屬板上若干形成於其上的凹槽，所述的連接班將源極引線耦合到低壓側N溝道金屬氧化物半導體場效應電晶體的源極襯墊，所述的凹槽位於與一個或者多個源極襯墊接觸的位置上。
位於低壓側源極連接金屬板上的若干凹槽被焊接到低壓側N溝道金屬氧化物半導體場效應電晶體上的一個或者多個源極襯墊上，所述的低壓側N溝道金屬氧化物半導體場效應電晶體的柵極通過低壓側柵極連接金屬板電連接到柵極引線，所述的低壓側柵極連接金屬板具有形成在其上的凹槽，所述的凹槽將柵極引線耦合到相應的低壓側N溝 道金屬氧化物半導體場效應電晶體上的柵極襯墊，所述的凹槽位於與柵極襯墊接觸的位置。
所述的低壓側柵極連接金屬板上的凹槽焊接到柵極襯墊。
低壓側N溝道金屬氧化物半導體場效應電晶體的源極通過一根或者多根電源排線或者夾子連接到源極引線，而所述的低壓側N溝道金屬氧化物半導體場效應電晶體的柵極通過一根導電線或者夾子連接到柵極引線。
所述的高壓側倒裝N溝道金屬氧化物半導體場效應電晶體的汲極通過一導電排線或者導電夾子連接到一個或者多個汲極引線，而所述的高壓側倒裝N溝道金屬氧化物半導體場效應電晶體的柵極通過一個焊料球電連接到柵極引線。
本發明公開了一種電路封裝元件，包括一個共同晶片襯墊；一個具有源極電觸點的高壓側N溝道金屬氧化物半導體場效應電晶體，其源極位於面向共同晶片襯墊表面的一側且電接觸該共同晶片襯墊；所述的高壓側N溝道金屬氧化物半導體場效應電晶體包括一個底部源極N溝道橫向雙擴散金屬氧化物半導體場效應電晶體；一個具有汲極電觸點的低壓側標準N溝道金屬氧化物半導體場效應電晶體，其汲極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊；所述的低壓側N溝道金屬氧化物半導體場效應電晶體是一個垂直雙擴散金屬氧化物半導體場效應電晶體。
本發明公開了一種電路封裝元件，包括一個共同晶片襯墊；一個具有源極電觸點的高壓側N溝道金屬氧化物半導體場效應電晶體，其源極位於面向共同晶片襯墊表面的一側且電接觸該共同晶片襯墊，所述的高壓側N溝道金屬氧化物半導體場效應電晶體以倒裝結構的方式安裝在共同晶片襯墊；一個具有汲極電觸點的低壓側標準N溝道金屬氧化物半導體場效應電晶體，其汲極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊，所述的低壓側N溝道金屬氧化物半導體場效應電晶體是垂直雙擴散金屬氧化物半導體場效應電晶體。
本發明公開了一種電路封裝元件，包括：一個共同晶片襯墊；一個具有源極電觸點的高壓側N溝道金屬氧化物半導體場效應電晶體，其源極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊；一個具有汲極電觸點的低壓側標準N溝道金屬氧化物半導體場效應電晶體，其汲極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊；一個金屬氧化物半導體場效應電晶體驅動器積體電路，該金屬氧化物半導體場效應電晶體驅動器積體電路具有耦合到高壓側N溝道金屬氧化物半導體場效應電晶體柵極的高壓側柵極驅動器輸出和一個耦合到低壓側N溝道金屬氧化物半導體場效應電晶體的柵極的低壓側柵極驅動器。
本發明具有以下效果和優點：
1.可以進一步縮小功率元件的尺寸。
2.可以減少寄生電感和電容。
3.可以能提高功率元件的效率。
4.可以減少直流-直流功率轉換電路中封裝的數量和成本。
雖然為了說明本發明，以下詳細的說明包括很多具體細節，但本領域內的普通技術人員都會理解對於本發明細節的變化和修改都包含在本發明的範圍以內。因此，以下描述的本發明的實施例不喪失一般性，並且對所述的發明未施加任何限制。
如上文所討論的，使用NMOSFET功率元件的功率轉換器典型地包括三個部件：一個柵極驅動器積體電路，一個高壓側NMOSFET和一個低壓側NMOSFET。傳統方式中，高壓側和低壓側NMOSFETs設置在同一個封裝中的兩個獨立晶片襯墊上。減少元件數量的一個可能的方法就是使用PMOSFET和NMOSFET功率元件的組合封裝。如果，例如，高壓側功率元件是一個PMOSFET元件，而低壓側功率元件是一個NMOSFET元件，則兩個功率元件就可以被貼附在同一個晶片襯墊上。不幸的是，PMOSFET元件的性能比NMOSFET元件的性能要差很多。結果導致使用PMOSFET和NMOSFET元件的功率轉換電路具有較高的直流電阻和較低的效率。然而，在低壓側和高壓側底部汲極NMOSFETs的傳統安裝方式中，由於使用了連接高壓側NMOSFFT源極和低壓側NMOSFET汲極的鍵合線，從而 導致了不良的寄生電感。傳統NMOSFETs的源極設置在頂部而汲極設置在底端。對於諸如高壓側低壓側功率轉換器之類的電路，這種設置需要將NMOSFETs安裝在兩個不同的晶片襯墊上，這樣就增加了熱電阻且導致了安裝晶片的可用空間減少。
本發明的實施例通過使用NMOSFET元件作為在高壓側和低壓側NMOSFETs，從而克服了由於使用安裝在電壓轉換電路封裝中共同襯底上的PMOSFET和NMOSFET功率元件所導致的低效率和高電阻的缺點。本發明的實施例通過將一個底部汲極低壓側NMOSFET元件和一個高壓側NMOSFET元件安裝到同一個晶片襯墊上並且高壓側NMOSFET組件的源極面向同一個晶片襯墊，從而克服了傳統上由於將底部汲極高壓側和低壓側NMOSFETs安裝到不同的晶片襯墊上所帶來的寄生電感的缺點。本發明的實施例通過將一個底部汲極低壓側NMOSFET元件和一個高壓側NMOSFET元件安裝到同一個晶片襯墊上並且高壓側NMOSFET組件的源極面向同一個晶片襯墊，從而克服了傳統上將高壓側和低壓側晶片安裝在不同的晶片襯墊上所帶來的熱電阻的增加和NMOSFET晶片空間減少的缺點。
在本發明的一個實施例中，高壓側和低壓側NMOSFETs可被結合在同一個導電襯底或者晶片襯墊上。高壓側和低壓側NMOSFETs封裝在一起，且高壓側NMOSFET的源極端和低壓側NMOSFET的汲極端面向共同襯底的表面。根據本發明的一個實施例，功率轉換器電 路封裝包括一個安裝在共同晶片襯墊上的高壓側的底部源極NMOSFET和一個底部汲極安裝在共同晶片襯墊的低壓側的標準VDMOSFET。
除非明確指出其他類型，此處所指的VDMOSFET是指N溝道VDMOSFET。另外，除非明確指出其他類型，此處所指的標準VDMOSFET是指底部汲極VDMOSFET，也就是，汲極形成於襯底。舉例說明，低壓側標準VDMOSFET可以是在本文中引用的申請號為5998833的美國專利所公開的隔離柵極溝槽(SGT)雙擴散金屬氧化物半導體(DMOS)，還可以是標準垂直槽柵極DMOS，例如從加州桑尼維爾的萬國半導體(AOS)獲得的型號為AO4922的器件，還可以是在此處引用的申請號為4344081的美國專利中公開過的標準垂直平面MOSFET，或者還可以是在本文中引用的正在申請中的申請號為11/444，853，申請日為2006年5月31日的名稱為“平面分立柵極高性能MOSFET結構和製造方法”中描述的平面分立柵極垂直MOSFET。溝槽DMOS可能產生較低的電阻率(Rds-on *尺寸)從而達到最好的性能。通過使用隔離柵極溝槽DMOS技術可以達到低電容。
根據一個實施例，高壓側底部源極NMOSFET是一個橫向雙擴散MOSFET(LDMOSFET)，如引用了所有公佈文件的在申請中的申請日為2006年7月27日，申請號為11494830，名稱為“底部源極LDMOSFET結構和方法”的美國專利中所描述的底部源極LDMOSFET。底部源極 LDMOSFET有一個汲極位於頂部，源極-形成於襯底--位於底部。第2A圖-第2B圖是根據本發明一個實施例中的高壓側和低壓側NMOSFET電路封裝元件的俯視圖。第2A圖-第2B圖中，所示的此類功率轉換器電路元件和在本發明中的其他地方所描述的其他功率轉換器電路都可被應用到多種使用高壓側和低壓側元件的不同應用中。此類應用包括但不限於功率轉換器電路，音頻放大器電路，射頻(RF)放大電路和運算放大器(op-amp)輸出狀態。例如，第2A圖-第2B圖所示的此類電路封裝元件可被用於並且不限於功率轉換電路。
如第2A圖所示，在封裝組件200中，底部源極N溝道LDMOSFET202位於共同晶片襯墊206的高壓側，而低壓側標準N溝道VDMOSFET204位於共同晶片襯墊206的低壓側。除非明確指出其他情況，在此處所指的高壓側LDMOSFET是指高壓側N溝道底部源極LDMOSFET，也就是汲極形成在晶片的頂部，而源極形成在晶片的襯底處-位於晶片的底部。高壓側LDMOSFET202安裝在共同晶片襯墊206上，其源極面向、物理貼附且電連接到共同晶片襯墊206上，例如，通過一個導電黏合層208，如導電環氧層或者，更好的用焊料球來進行連接。低壓側標準VDMOSFET204同樣通過一個導電黏合層210如導電環氧層或者更好的用焊料球物理貼附和電連接於共同晶片襯墊206，且低壓側標準VDMOSFET204的汲極面向共同晶片襯墊206。位於高壓側LDMOSFET202和低壓側標準 VDMOSFET204背向共同晶片襯墊206的一側上的柵極襯墊203，205分別通過各自的鍵合線224和226連接到柵極引線220和222。位於背向共同晶片襯墊206一側的高壓側LDMOSFET202的汲極襯墊207，通過鍵合線214電連接到各自的汲極引線212。類似的，低壓側標準VDMOSFET204的源極襯墊209通過鍵合線216分別電連接於各自的源極引線218。在此處使用的術語“柵極襯墊”，“汲極襯墊”和“源極襯墊”是指MOSFET相對暴露和導電的區域，其分別和MOSFET的柵極，源極和汲極區電接觸。除非明確說明，在以下圖中，封裝被裝在一個未顯示的模塑膠中。
第2B圖-第2C圖描述了功率轉換電路封裝元件201中高壓側和低壓側NMOSFETs的組合封裝，其類似於第2A圖中所示的封裝，但在此封裝中，高壓側LDMOSFET202的頂部汲極襯墊207和低壓側標準VDMOSFET204的頂部源極襯墊209分別連接到共同汲極引線217和共同源極引線219。
第2D圖是一個如第2A圖-第2C圖所示的高壓側和低壓側MOSFETs安裝在共同襯底上的功率轉換電路230的電路圖。如第2D圖所示，高壓側LDMOSFET202的汲極DHS 電耦合到輸入電壓VIN ，高壓側LDMOSFET202的源極SHS 電耦合到低壓側標準VDMOSFET204的汲極DLS 。低壓側標準VDMOSFET204的源極SLS 電耦合到接地引腳PGND。高壓側LDMOSFET202的柵極(GHS )和低壓側標準VDMOSFET204的柵極(GLS )分別電耦合到高壓側柵極 電壓VGHS 和低壓側柵極電壓VGLS 。高壓側和低壓側MOSFETs202和204置於如虛線框211所指的模塑膠中 。由通常用於功率轉換電路的MOSFET驅動器積體電路(IC)232來提供柵極電壓VGHS ,VGLS 。市場上可以買到的可被用於MOSFET驅動器積體電路232的MOSFET包括但不限於lntersil公司生產的型號為LSL6207的高壓同步整流降壓MOSFET驅動器和美國加州Semtech公司生產型號為SC1205的高速同步功率MOSFET驅動器。
在不喪失一般性的情況下舉例說明，MOSFET驅動器積體電路232具有輸入端，該輸入端包括啟動輸入EN，脈寬調節輸入PWM，正電源電壓VS，接地引腳PGND和一個汲極引腳DRN。另外，MOSFET驅動器積體電路232包括輸出引腳，如高壓側柵極驅動器TG，低壓側柵極驅動器BG和一個引導電壓引腳BST。一個適合的源極電壓(例如+5V)為電壓引腳VS供電。在一些實施例中，電壓源極和接地引腳PGND之間可連接一電容。MOSFET驅動器可以這樣配置，就是當有一個足夠的電壓應用於啟動針腳EN，MOSFET驅動器232內部電路將被啟動。用於脈寬調製解調輸入PWM的脈寬調製信號為MOSFET驅動器積體電路232提供驅動器信號。
高壓側柵極驅動器TG耦合到高壓側MOSFET202的柵極GHS ，從而提供高壓側柵極電壓VGHS 。同樣的，低壓側柵極驅動器BG耦合到低壓側MOSFET204的柵極GLS 來提供低壓側柵極電壓VGHS 。汲極引腳DRN連接在高壓側 MOSFET292的源極SHS 和低壓側MOSFET204的汲極DLS 之間，從而為高壓側柵極驅動器TG提供一個回路。自舉電壓引腳BST為高壓側柵極MOSFET202提供浮動自舉電壓。在一些應用中，自舉電容CB 耦合在自舉電壓引腳BST和汲極引腳DRN之間。電容器C電耦合在VIN 和輸出電壓VSW (開關電壓)之間，一個肖特基二極體DSCH 電耦合在開關電壓VSW 和接地引腳PGND之間，接地引腳連接於源極接地端SGND。集成的肖特基二極體通過減少低壓側體二極體恢復損失，減少開關時的振盪等來提高電路性能。注意到肖特基二極體集成在低壓側MOSFET組件204上。MOSFETs和肖特基二極體的組合封裝的例子包括但是不局限於SRFETTM 家族產品，如可以從加利福尼亞桑尼維爾的萬國半導體公司獲得的型號為AOL1412的器件。
第2E圖、第2F圖中的截面圖和第2G圖、第2H圖展示了高壓側NMOSFE HS和低壓側NMOSFET LS的組合封裝的優點。在現有技術第2E圖中，高壓側NMOSFET HS和低壓側NMOSFET LS都是底部汲極NMOSFETS，其分別位於兩個電絕緣的晶片襯墊DPH ,DPL 上。低壓側MOSET的汲極DL 面向低壓側晶片襯墊DPL 。高壓側MOSFET的汲極DH 面向高壓側晶片襯墊DPH 。雖然圖中未顯示，高壓側和低壓側NMOSFETs HS、LS晶片襯墊DPH 、DPL 和引線框架LF都包裝在一個模塑膠中。低壓側NMOSFET的源極SL 電耦合在引線框架LF。低壓側NMOSFET的汲極DL 通過鍵合線BW耦合到高壓側NMOSFET的源極SH ，該鍵 合線BW電接觸於低壓側晶片襯墊DPL 。如第2G圖所示，是由於鍵合線BW的緣故導致寄生電感L1。對比而言，如第2F圖所示，高壓側NMOSFET HS和低壓側MOSFET LS組合封裝於一個共同晶片襯墊DPCS 上，且高壓側NMOSFET的源極面向共同晶片襯墊DPC ，由於去掉了鍵合線因此除去了如第2H圖所示的寄生電感L1。雖然圖中未顯示，高壓側和低壓側NMOSFETs HS，LS，共同晶片襯墊DPC ，以及引線框架LF用一個模塑膠包裝起來。注意到出於簡化的原因，在第2G圖和第2H圖中由於外部連接而產生的寄生電容和電感被忽略掉了。
在一些實施例中，使用平面MOSFET導致了超低的連接電容。理論上，高壓側MOSFETR，或者低壓側MOSFETR，又或者兩者都是可以是平面的。在一個優選實施例中，高壓側MOSFET可以是平面元件，其和具有隔離柵極溝槽DMOS結構的低壓側MOSFET組合在一起，例如其可以是申請號為5998833的美國專利所示的類型，更可能是用於低壓側MOSFET LS的集成肖特基二極體。
第3圖是根據本發明一個實施例中所述的具有高壓側和低壓側NMOSFETs組合封裝的平面鍵合功率轉換電路封裝300的俯視圖，所述的NMOSFETs包括一個高壓側底部源極LDMOSFET和線連接柵極。如第3圖所示，高壓側LDMOSFET302和低壓側標準(底部汲極)VDMOSFET304組合封裝在一個共同晶片襯墊306上。高壓側LDMOSFET302和低壓側標準VDMOSFET304分別通過各 自的導電層308和310電連接到共同晶片襯墊306上。導電層308和310可以是導電黏合層，例如，導電環氧層或者更好用焊料球。分別置於各襯墊底部的高壓側LDMOSFET302的源極襯墊和低壓側標準VDMOSFET304的汲極襯墊，被設置為面向共同晶片襯墊306。高壓側LDMOSFET302和低壓側標準VDMOSFET304的柵極襯墊303、305分別通過各自的鍵合線328、330連接到柵極引線324和326。
位於高壓側LDMOSFET302背向第一晶片襯墊306一側的汲極襯墊307，通過第一連接金屬板312電連接到汲極引線320。同樣的，位於低壓側標準VDMOSFET304背向共同晶片襯墊306一側的源極襯墊309，通過第二連接金屬板314電連接到源極引線322。第一連接金屬板312包括若干汲極凹槽315和錨定孔317。第二連接金屬板314包括若干源極凹槽316和錨定孔318。汲極凹槽315位於並且是衝壓在或者洞開在第一連接金屬板312上，這樣可以在回流焊接的過程中與高壓側LDMOSFET302上的汲極襯墊307對準。同樣地，源極凹槽316位於並且是衝壓在或者洞開在第二連接金屬板314上，因此可以在回流焊接的過程中與低壓側標準VDMOSFET304的源極襯墊309對準。軟焊料可被放置到汲極凹槽315和源極凹槽316中，並分通過凹槽315、316上的通孔(未顯示)流到高壓側LDMOSFET302上的汲極襯墊307和低壓側標準VDMOSFET304上的源極襯墊309，從而分別在高壓側 LDMOSFET302的汲極與汲極引線320之間以及低壓側標準VDMOSFET304的源極和源極引線322之間形成電性互聯。
第4圖是根據本發明的一個實施例中的具有高壓側和低壓側NMOSFETs組合封裝的金屬板連接功率轉換電路封裝301的俯視圖，其中，NMOSFETs包括一個高壓側LDMOSFET和一個金屬板連接柵極。第4圖所示的金屬板連接高壓側和低壓側NMOSFET組合封裝元件類似於第3圖所示的封裝，但是第4圖中底部源極LDMOSET302和低壓側標準VDMOSFET304上的柵極襯墊303和305分別通過柵極連接金屬板336和338電連接到柵極引線324和326。高壓側柵極金屬板336包括一個凹槽332，該凹槽332其位於且衝壓或者洞開在高壓側柵極連接金屬板336上，因此可以在回流焊接過程中與高壓側底部源極LDMOSFET302上，的柵極襯墊303對準。低壓側柵極連接金屬板338包括一凹槽334，該凹槽334位於且是衝壓或者洞開在低壓側柵極連接金屬板338上，因此可以在回流焊接過程中與低壓側標準VDMOSFET304上的柵極襯墊305對準。高壓側LSMOSFET302的柵極襯墊303和柵極連接金屬板336之間的電互聯，以及低壓側標準VDMOSFET304的柵極襯墊305和柵極連接金屬板338之間的電互聯可以通過在柵極襯墊303和305的外部開口沉積軟焊劑來形成，軟焊劑擠壓在柵極凹槽332和334周圍可以減少壓力和阻力。
關於使用如上第3圖和第4圖所描述的利用包含凹槽的連接金屬板形成的互連的詳細描述可以在正在申請中的名稱為“包含凹槽金屬板互連的半導體封裝”(Semiconductor Package Having Dimpled Plate Interconnection)申請號為11/799474申請日為2007年4月30日申請人為孫明(案號為AOS025)的美國專利中獲得，其完整的公開檔作為參考在此處引用。
本發明的前幾個實施例中使用了一個底部源極NMOSFET作為高壓側NMOSFET。此處的“底部源極”MOSFET是指製成的MOSFET中，其源極區和/或相關的源極襯墊位於晶片底部，而其他區域(柵極和汲極)和/或他們相關的襯墊位於源極和/或源極襯墊的頂部。一個底部源極MOSFET的例子在本文中引用的申請號為11/495803的美國專利申請中進行了描述。相比而言，“標準”(或者底部汲極)MOSFET，其汲極區域和/或相關的汲極襯墊形成在晶片的底部而其他區域(源極和柵極)和/獲其相關的襯墊形成在汲極區域和/或汲極襯墊的頂部。根據本發明的一個實施例，高壓側MOSFET可是標準(底部汲極)VDMOSFET，其以倒裝晶片的結構安裝在共同晶片襯墊上，其中，底部汲極襯墊位於背向共同晶片襯墊的一側，而源極襯墊安裝在面向共同晶片襯墊的的反面。在此類實施例中的高壓側VDMOSFET可以是個平面分立柵極垂直MOSFET、隔離柵極溝槽垂直MOSFET、標準溝槽VDMOSFET或標準溝槽DMOS。
第5A圖是包含高壓側和低壓側NMOSFETs金屬板連接組合封裝的功率轉換電路封裝500的俯視圖，其中NMOSFETs包括一個以倒裝晶片形成安裝的具有金屬板連接柵極的高壓側標準(底部汲極)VDMOSFET502。如第5A圖所示，倒裝高壓側標準VDM6OSFET5026和一個低壓側標準VDMOSFET504封裝在一個共同晶片襯墊506上。如第5B圖-第5C圖所示，高壓側VDMOSFET502以其柵極襯墊503和源極襯墊511位於面向共同晶片襯墊506的一側這種倒裝結構安裝。在下文中，高壓側VDMOSFET是指具有倒裝結構的高壓側標準(底部汲極)VDMOSFET。源極襯墊511通過倒裝晶片焊料球530電連接於共同晶片襯墊506。在這個實施例中，高壓側VDMOSFE502的柵極襯墊503電連接到柵極引線528，其位於靠近共同晶片襯墊506的高壓側VDMOSFET502的下面。柵極襯墊503和柵極引線528之間的電連接可以通過諸如一個或者多個晶片極封裝(CSP)或者倒裝晶片焊料球526來實現，該CSP或倒裝晶片焊料球放在高壓側VDMOSFET502和柵極引線528之間且與柵極襯墊503對準來提供電連接。
在倒裝結構中，高壓側VDMOSFET502的汲極襯墊507位於背向共同晶片襯墊506的一側。汲極襯墊507通過一個倒裝晶片連接金屬板512電連接到汲極引線532。倒裝晶片連接金屬板512包括若干汲極凹槽515和錨定孔517。汲極凹槽515位於且衝壓或者洞開在倒裝晶片連接金屬板512 上，因此可以在回流焊接過程中與高壓側VDMOSFET502上的汲極襯墊對準。軟焊劑被襯墊到汲極凹槽515中，並且通過汲極凹槽515上的通孔(未顯示)流動到高壓側VDMOSFET502的汲極襯墊，從而在汲極襯墊507和汲極引線532之間形成電連接。晶片極封裝/倒裝晶片焊料球530置於高壓側VDMOSFET502和共同晶片襯墊506之間來形成源極電連接。晶片極封裝/倒裝晶片焊料球526和530可以是直徑為100um的銅柱或者焊料球。
和第4圖所示的低壓側標準VDMOSFET304類似，標準VDMOSFET504的源極襯墊509通過低壓側標準源極連接金屬板514電連接到源極引線534。低壓側源極連接金屬板514包括若干源極凹槽516和錨定孔518。源極凹槽516位於且衝壓在或者洞開在第二連接金屬板514上，因此在回流焊接過程中，與源極襯墊509對準。低壓側標準VDMOSFET504的柵極襯墊505通過一個柵極金屬板522電連接到柵極引線524。柵極金屬板522包括一個凹槽520，凹槽520位於且衝壓在或者洞開在柵極金屬板522上，因此在回流焊接過程中和柵極襯墊505對準。軟焊料沉積到源極凹槽516和柵極凹槽520中，通過源極凹槽516上的通孔(未顯示)流動到源極襯墊509，從而在源極襯墊509和源極引線534之間形成電連接。低壓側標準VDMOSFET504的汲極襯墊513面向並且電連接到共同晶片襯墊506。低壓側標準VDMOSFET504通過一個導電環氧層510電接觸於共同晶片襯墊506。
第5B圖是第5A圖中，具有高壓側和低壓側MOSFETSs金屬板連接組合封裝功率轉換電路封裝500沿著線B-B的截面圖，其中MOSFETs具有一個高壓側倒裝晶片VDMOSFET502。如第5A圖所示，高壓側VDMOSFET502以倒裝晶片方式安裝，因此其源極面向共同晶片襯墊506。如第5B圖所示，CSP/倒裝晶片焊料球530位於高壓側VDMOSFET502和共同晶片襯墊506之間，從而在高壓側VDMOSFET502的源極襯墊511和共同晶片襯墊506之間形成電連接。第5C圖是第5A圖中具有高壓側和低壓側MOSFETs金屬板連接組合封裝的功率轉換電路封裝500沿著線C-C的截面圖，其中NMOSFETs具有一個高壓側倒裝VDMOSFET502。如第5C圖所示，CSP/倒裝晶片焊料球530位於高壓側VDMOSFET502和共同晶片襯墊506之間以形成源極襯墊511和共同晶片襯墊506之間的電連接，而晶片極封裝倒裝晶片焊料球526設置在柵極引線528和高壓側VDMOSFET502之間，並且與高壓側VDMOSFET502的柵極襯墊503對準，以形成柵極襯墊503和柵極引線528之間的電連接。
第6圖是具有高壓側和低壓側NMOSFETs組合封裝的功率轉換電路封裝600的電路俯視圖，其中，MOSFETs具有鋁電源排線互聯。如第6圖所示，底部源極高壓側LDMOSFET602和低壓側標準VDMOSFET604共同封裝在一個共同晶片襯墊606上。底部源極高壓側LDMOSFET602的汲極襯墊607利用一根或多根鋁電源排連電連接到汲極 引線620。同樣地，低壓側標準VDMOSFET604的源極襯墊609也通過一根或者多根鋁電源排線電連接到源極引線622。高壓側LDMOSFET602和低壓側標準VDMOSFET604的柵極襯墊603和605分別通過各自的鋁電源排線614和615電連接到各自的柵極引線616和618。鋁電源排線612、613和鋁線614、615都可以使用超聲波加熱連接到襯墊和引線。作為選擇，柵極襯墊603、605可以通過鍵合線，連接金屬板或者鋁電源排線(未顯示)電連接到各自的柵極引線616、618。
第7圖上將具有倒裝或倒裝晶片配置安裝的高壓側標準VDMOSFET和低壓側標準VDMOSFET通過鋁電源排線互聯的組合封裝的功率轉換電路封裝700的電路圖。如第7圖所示，倒裝高壓側VDMOSFET702和一個傳統安裝的低壓側標準VDMOSFET704共同封裝在一個共同晶片襯墊706上。高壓側VDMOSFET702的汲極襯墊707通過鋁電源排線或者夾子708電連接到汲極引線720。焊料球712位於高壓側VDMOSFET702的下面從而達到高壓側VDMOSFET702的源極襯墊711和共同晶片襯墊706之間，從而和高壓側VDMOSFET702的柵極襯墊703和柵極引線716之間的電性互聯。
低壓側VDMOSFET704的源極襯墊709通過一根鋁電源排線或者夾子710電連接到源極引線722。低壓側VDMOSFET704的柵極襯墊705可以通過一根鋁電源排線或者夾子714電連接到柵極引線718。作為替換，柵極襯墊 703，705可以通過鍵合線、連接金屬板或者鋁電源排線(未顯示)電連接到各自的柵極引線716，718。
鋁電源排線和鋁線都可以通過超聲波加熱連接到襯墊或者引線上。
本發明的實施例和現有技術比起來，可以使高壓側和低壓側NMOSFETF封裝於較小的空間中。對於NMOSFETS來說，較小的封裝空間可以使功率轉換電路或者元件的配置做的更小且價格更加低廉。另外，使用共同晶片襯墊可以較大程度的減少甚至消滅傳統封裝所導致的寄生電感。
雖然上文對本發明的優選實施例進行了完整的描述，但是還可以使用各種替代，修改和等效形式。例如，高壓側和低壓側NMOSFETS指定了特定的電晶體型號，例如：LDMOSFET和VDMOSFET。這些是優選實施例，但是不能說明本發明僅限於此類電晶體型號。理論上，任何型號的垂直NMOSFET都可以使用，只要其汲極和源極位於實施例中所描述中的相同位置。
另外，雖然以上描述了應用於功率轉換電路一個實施例，但是本發明的實施例並不局限于此類應用。本發明的實施例可以被應用於任何情形，只要兩個垂直NMOSFETs中的其中一個的汲極電連接到另一個的源極。
因此，本發明的範圍不應通過上文的描述確定，而是應該通過附後的申請專利範圍及其等效內容的全部範圍確定。任何技術特徵不論是否優選都可以和任何其他不論是否優選的技術特徵組合。在附後的申請專利範圍中，除非 另有明確的指定，原文中的不定冠詞"A"或"An"指該冠詞之後的專案的數量為一個或多個。附後的申請專利範圍不應解釋為其包括方法加功能的限制，除非這樣的限制在所給出的申請專利範圍中明確地指出。
BG‧‧‧低壓側柵極驅動器
BST‧‧‧引導電壓引腳
BW、114、116、214、216、224、226、328、330‧‧‧鍵合線
C‧‧‧電容器
CB ‧‧‧電容
d‧‧‧寬度
DRN‧‧‧汲極引腳
DSCH ‧‧‧肖特基二極體
DL 、DH 、DLS ‧‧‧汲極
DPC 、DPCS 、DPH 、DPL 、206、306、506、706‧‧‧共同晶片襯墊
GHS 、GLS ‧‧‧柵極
LF‧‧‧引線框架
NMOSFET‧‧‧N溝道電晶體
PGND‧‧‧接地引腳
SL 、SH 、SH 、S SLS ‧‧‧源極
SGND‧‧‧源極接地端
TG‧‧‧高壓側柵極驅動器
VIN ‧‧‧電壓
VGHS ‧‧‧高壓側柵極電壓
VGLS ‧‧‧低壓側柵極電壓
VS‧‧‧電壓引腳
VSW ‧‧‧開關電壓
VDMOSFET‧‧‧垂直雙擴散金屬氧化物半導體 場效應電晶體
101‧‧‧虛線
102‧‧‧高壓側標準VDMOSFET
103、105、203、205、303、305、503、603、605、703、705‧‧‧柵極襯墊
104‧‧‧低壓側標準VDMOSFET
106、108、306‧‧‧晶片襯墊
107、109、209、309、509、511、609、709、711‧‧‧源極襯墊
110、112、218、322、722、219‧‧‧源極引線
118、120、510‧‧‧導電環氧層
122‧‧‧額外鍵合線
200‧‧‧封裝組件
201‧‧‧功率轉換電路封裝元件
202、302、502、602、702‧‧‧高壓側LDMOSFET
204、304、504、604、704‧‧‧低壓側標準N溝道 VDMOSFET
207、307、507、513、707‧‧‧汲極襯墊
208、210‧‧‧導電黏合層
212、217、320、532、620、622、720‧‧‧汲極引線
220、222、324、326、508、524、616、618、716、718‧‧‧柵極引線
230‧‧‧功率轉換電路
300‧‧‧平面鍵合功率轉換電路封裝
301‧‧‧金屬板連接功率轉換電路封裝
302‧‧‧高壓側LDMOSFET
304‧‧‧低壓側標準VDMOSFET
308、310‧‧‧導電層
312‧‧‧第一連接金屬板
314‧‧‧第二連接金屬板
315、515‧‧‧汲極凹槽
316、516‧‧‧源極凹槽
317、318、518‧‧‧錨定孔
332、334、506、520‧‧‧凹槽
336、338、522‧‧‧柵極連接金屬板
500‧‧‧功率轉換電路封裝
512‧‧‧倒裝晶片連接金屬板
514‧‧‧低壓側源極連接金屬板
526、530、712‧‧‧晶片焊料球
612、613、614、615‧‧‧鋁電源排線
708、710‧‧‧夾子
第1圖是現有技術用於功率轉換器的高壓側和低壓側NMOSFETs封裝的俯視圖；第2A圖-第2B圖是根據本發明一個實施例中具有高壓側和低壓側NMOSFETs的電路封裝元件的俯視圖；第2C圖是第2B圖電路封裝元件的立體圖；第2D圖是功率轉換電路的電路圖，此功率轉換電路可用於連接如第2A圖-第2C圖所示的高壓側和低壓側NMOSFET電路封裝元件；第2E圖是現有技術中高壓側和低壓側NMOSFET電路封裝元件的側視橫截面面圖；第2F圖是根據本發明的一個實施例中高壓側和低壓側NMOSFET電路封裝元件的側視橫截面圖；第2G圖是現有技術高壓側和低壓側NMOSFET電路封裝元件的等效電路圖；第2H圖是根據本發明一個實施例中高壓側和低壓側NMOSFET電路封裝元件的等效電路圖；第3圖是根據本發明的一個實施例中的具有高壓側和低壓側NMOSFETs組合封裝的金屬板連接電路封裝的俯視圖，NMOSFETs具有線連接柵極的高壓側底部源極橫向雙擴散MOSFET(LDMOSFET)；第4圖是根據本發明的一個實施例中的使用金屬板連接柵極將高壓側和低壓側NMOSFET進行組合封裝的電路封裝元件的俯視圖； 第5A圖是根據本發明的一個實施例中的具有高壓側和低壓側NMOSFET金屬板連接組合封裝的電路封裝元件的俯視圖，其中高壓側NMOSFET以倒裝晶片結構進行封裝；第5B圖是沿著第5A圖中線B-B的橫截面圖；第5C圖是沿著第5A圖中線C-C的橫截面圖；第6圖是根據本發明的一個實施例中的具有用鋁電源排線互聯的高壓側和低壓側NMOSFETs的組合封裝的電路封裝元件的俯視圖；第7圖是根據本發明的一個實施例中的具有高壓側和低壓側NMOSFETs組合封裝的電路封裝元件的俯視圖，高壓側底部源極或者倒裝晶片垂直MOSFET用鋁電源排線互聯。
LF‧‧‧引線框架
SL 、SH ‧‧‧源極
DL 、DH ‧‧‧汲極
DPC ‧‧‧共同晶片襯墊

Claims (25)

  1. 一種電路封裝元件，包括一個共同晶片襯墊；一個具有源極電觸點的第一垂直N溝道金屬氧化物半導體場效應電晶體，所述的源極位於面向共同晶片襯墊表面的一側且電接觸該共同晶片襯墊；一個具有汲極電觸點的第二垂直N溝道金屬氧化物場效應電晶體，所述的汲極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊。
  2. 如申請專利範圍第1項所述的電路封裝元件，其特徵在於，所述的第一N溝道金屬氧化物半導體場效應電晶體是一個高壓側N溝道金屬氧化物半導體場效應電晶體，所述的第二N溝道金屬氧化物半導體場效應電晶體是一個低壓側N溝道金屬氧化物半導體場效應電晶體。
  3. 如申請專利範圍第2項所述的電路封裝元件，其特徵在於，所述的高壓側N溝道金屬氧化物半導體場效應電晶體包括一個底部源極N溝道橫向雙擴散N溝道金屬氧化物半導體場效應電晶體，而所述的低壓側N溝道金屬氧化物半導體場效應電晶體包括一個底部汲極N溝道垂直雙擴散N溝道金屬氧化物半導體場效應電晶體。
  4. 如申請專利範圍第2項所述的電路封裝元件，其特徵在於，所述的高壓側N溝道金屬氧化物半導體場效應 電晶體的柵極襯墊和汲極襯墊都位於高壓側N溝道金屬氧化物半導體場效應電晶體背對共同晶片襯墊的一側，而所述的柵極襯墊和汲極襯墊分別電連接到各自的柵極引線。
  5. 如申請專利範圍第1項所述的電路封裝元件，其特徵在於，所述的第二N溝道金屬氧化物半導體場效應電晶體的柵極襯墊和源極襯墊分別通過若干鍵合線分別連接到各自的柵極引線和源極引線。
  6. 如申請專利範圍第2項所述的電路封裝元件，其特徵在於，所述的高壓側N溝道金屬氧化物半導體場效應電晶體的汲極襯墊和低壓側N溝道金屬氧化物半導體場效應電晶體的源極襯墊分別位於高壓側N溝道金屬氧化物半導體場效應電晶體和低壓側N溝道金屬氧化物半導體場效應晶體背對共同晶片襯墊的一側，而所述的各自的汲極襯墊和源極襯墊則分別通過第一和第二連接金屬板連接到汲極和源極引線。
  7. 如申請專利範圍第6項所述的電路封裝元件，其特徵在於，所述的第一連接金屬板包括若干形成於其上的第一凹槽，該凹槽將汲極引線連接到高壓側N溝道金屬氧化物半導體場效應電晶體的汲極襯墊，該凹槽置於連接金屬板上以提供和汲極的連接；所述的第二連接金屬板包括若干第二凹槽，該凹槽將源極引線連接到低壓側N溝道金屬氧化物半導體場效應電晶體的源極襯墊，該凹槽置於連接金屬板上以提供和源極的連 接。
  8. 如申請專利範圍第7項所述的電路封裝元件，其特徵在於，所述的若干第一凹槽和第二凹槽分別焊接到汲極襯墊和源極襯墊上。
  9. 如申請專利範圍第8項所述的電路封裝元件，其特徵在於，所述的高壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊和低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊分別通過鍵合線連接到柵極引線，所述的高壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊和低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊則分別通過高壓側和低壓側連接金屬板連接到柵極引線。
  10. 如申請專利範圍第9項所述的電路封裝元件，其特徵在於，所述的高壓側柵極連接金屬板包括一個形成在其上的凹槽，該凹槽置於和高壓側N溝道金屬氧化物半導體場效應電晶體上的柵極襯墊接觸的位置；所述的低壓側柵極連接金屬板包括一個形成在其上的凹槽，該凹槽將柵極引線連接到低壓側N溝道金屬氧化物半導體場效應電晶體上的柵極襯墊，凹槽置於和低壓側N溝道金屬氧化物半導體場效應電晶體上的柵極襯墊接觸的位置。
  11. 如申請專利範圍第10項所述的電路封裝元件，其特徵在於，所述的凹槽焊接到低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊上。
  12. 如申請專利範圍第2項所述的電路封裝元件，其特徵在於，所述的高壓側N溝道金屬氧化物半導體場效應電晶體的汲極襯墊位於背對共同晶片襯墊上的一側，所述的低壓側N溝道金屬氧化物半導體場效應電晶體的源極襯墊位於背對共同晶片襯墊的一側，所述的汲極襯墊和源極襯墊分別通過一根或者多根鋁電源排線連接到汲極引線和源極引線。
  13. 如申請專利範圍第12項所述的電路封裝元件，其特徵在於，所述的高壓側N溝道金屬氧化物半導體場效應電晶體和低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊分別通過鍵合線電連接到柵極引線，所述的高壓側N溝道金屬氧化物半導體場效應電晶體和低壓側N溝道金屬氧化物半導體場效應電晶體的柵極襯墊分別通過連接金屬板或者電源排線連接到柵極引線。
  14. 如申請專利範圍第2項所述的電路封裝元件，其特徵在於，所述高壓側N溝道金屬氧化物半導體場效應電晶體是一個底部汲極N溝道金屬氧化物半導體場效應電晶體，其在底部上具有一個或者多個汲極襯墊，以及一個柵極襯墊，在頂部有一個或者多個源極襯墊，以倒裝晶片的方式安裝在共同晶片襯墊上，倒裝晶片是指晶片頂部接近兵並面向共同晶片襯墊，即柵極襯墊和一個或多個源極襯墊接近並面向共同晶片襯墊。
  15. 如申請專利範圍第14項所述的電路封裝元件，其特徵 在於，所述的高壓側倒裝N溝道金屬氧化物半導體場效應電晶體的汲極襯墊和低壓側N溝道金屬氧化物半導體場效應電晶體的一個或者多個源極襯墊分別通過相應的高壓側和低壓側連接金屬板電連接到相應的汲極引線和源極引線。
  16. 如申請專利範圍第12項所述的電路封裝元件，其特徵在於，所述的倒裝晶片連接金屬板包括若干形成在連接金屬板之上的凹槽，該凹槽被應用於將汲極引線連接到高壓側倒裝N溝道金屬氧化物半導體場效應電晶體的一個或者多個汲極襯墊，該凹槽位於與汲極襯墊接觸的位置。
  17. 如申請專利範圍第16項所述的電路封裝元件，其特徵在於，所述的高壓側倒裝N溝道金屬氧化物半導體場效應電晶體還包括利用一個或者多個焊料球形成的柵極和源極之間的電連接。
  18. 如申請專利範圍第17項所述的電路封裝元件，其特徵在於，所述的低壓側源極連接金屬板包括一個連接金屬板，該連接金屬板上若干形成於其上的凹槽，所述的連接班將源極引線耦合到低壓側N溝道金屬氧化物半導體場效應電晶體的源極襯墊，所述的凹槽位於與一個或者多個源極襯墊接觸的位置上。
  19. 如申請專利範圍第18項所述的電路封裝元件，其特徵在於，位於低壓側源極連接金屬板上的若干凹槽被焊接到低壓側N溝道金屬氧化物半導體場效應電晶體上 的一個或者多個源極襯墊上，所述的低壓側N溝道金屬氧化物半導體場效應電晶體的柵極通過低壓側柵極連接金屬板電連接到柵極引線，所述的低壓側柵極連接金屬板具有形成在其上的凹槽，所述的凹槽將柵極引線耦合到相應的低壓側N溝道金屬氧化物半導體場效應電晶體上的柵極襯墊，所述的凹槽位於與柵極襯墊接觸的位置。
  20. 如申請專利範圍第19項所述的電路封裝元件，其特徵在於，所述的低壓側柵極連接金屬板上的凹槽焊接到柵極襯墊。
  21. 如申請專利範圍第14項所述的電路封裝元件，其特徵在於，低壓側N溝道金屬氧化物半導體場效應電晶體的源極通過一根或者多根電源排線或者夾子連接到源極引線，而所述的低壓側N溝道金屬氧化物半導體場效應電晶體的柵極通過一根導電線或者夾子連接到柵極引線。
  22. 如申請專利範圍第21項所述的電路封裝元件，其特徵在於，所述的高壓側倒裝N溝道金屬氧化物半導體場效應電晶體的汲極通過一導電排線或者導電夾子連接到一個或者多個汲極引線，而所述的高壓側倒裝N溝道金屬氧化物半導體場效應電晶體的柵極通過一個焊料球電連接到柵極引線。
  23. 一種電路封裝元件，包括：一個共同晶片襯墊； 一個具有源極電觸點的高壓側N溝道金屬氧化物半導體場效應電晶體，其源極位於面向共同晶片襯墊表面的一側且電接觸該共同晶片襯墊；所述的高壓側N溝道金屬氧化物半導體場效應電晶體包括一個底部源極N溝道橫向雙擴散金屬氧化物半導體場效應電晶體；一個具有汲極電觸點的低壓側標準N溝道金屬氧化物半導體場效應電晶體，其汲極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊；所述的低壓側N溝道金屬氧化物半導體場效應電晶體是一個垂直雙擴散金屬氧化物半導體場效應電晶體。
  24. 一種電路封裝元件，包括：一個共同晶片襯墊；一個具有源極電觸點的高壓側N溝道金屬氧化物半導體場效應電晶體，其源極位於面向共同晶片襯墊表面的一側且電接觸該共同晶片襯墊，所述的高壓側N溝道金屬氧化物半導體場效應電晶體以倒裝結構的方式安裝在共同晶片襯墊；一個具有汲極電觸點的低壓側標準N溝道金屬氧化物半導體場效應電晶體，其汲極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊，所述的低壓側N溝道金屬氧化物半導體場效應電晶體是垂直雙擴散金屬氧化物半導體場效應電晶體。
  25. 一種電路封裝元件，包括：一個共同晶片襯墊； 一個具有源極電觸點的高壓側N溝道金屬氧化物半導體場效應電晶體，其源極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊；一個具有汲極電觸點的低壓側標準N溝道金屬氧化物半導體場效應電晶體，其汲極位於面向共同晶片襯墊的一側且電接觸該共同晶片襯墊；一個金屬氧化物半導體場效應電晶體驅動器積體電路，該金屬氧化物半導體場效應電晶體驅動器積體電路具有耦合到高壓側N溝道金屬氧化物半導體場效應電晶體柵極的高壓側柵極驅動器輸出和一個耦合到低壓側N溝道金屬氧化物半導體場效應電晶體的柵極的低壓側柵極驅動器。
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