TW201244052A - A combined packaged power semiconductor device - Google Patents

A combined packaged power semiconductor device Download PDF

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Publication number
TW201244052A
TW201244052A TW100115173A TW100115173A TW201244052A TW 201244052 A TW201244052 A TW 201244052A TW 100115173 A TW100115173 A TW 100115173A TW 100115173 A TW100115173 A TW 100115173A TW 201244052 A TW201244052 A TW 201244052A
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TW
Taiwan
Prior art keywords
wafer
power semiconductor
low
electrically connected
mosfet
Prior art date
Application number
TW100115173A
Other languages
Chinese (zh)
Other versions
TWI469311B (en
Inventor
Yueh-Se Ho
Hamza Yilmaz
Yanxun Xue
Jun Lu
Original Assignee
Alpha & Omega Semiconductor
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Publication date
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Priority to TW100115173A priority Critical patent/TWI469311B/en
Publication of TW201244052A publication Critical patent/TW201244052A/en
Application granted granted Critical
Publication of TWI469311B publication Critical patent/TWI469311B/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A combined packaged power semiconductor device includes a flipped top source low-side MOSFET electrically connected to a top surface of a die paddle, a first metal interconnection plate connecting between a bottom drain of a high-side MOSFET or a top source of a flipped high-side MOSFET to a bottom drain of the low-side MOSFET, and a second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally that reduces the overall size of semiconductor devices and can maximize the chip' s size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

Description

201244052 六、發明說明： 【發明所屬之技術領威】 [0001] 本發明涉及一種功率半導體元件，特別是有關於一種將 多個晶片等元器件聯合封裝在同一個功率半導體元件中 的結構。 【先前技術·】 [0002] 目前，典型的功率半導體元件中，通常將MOSFET晶片（ 金屬氧化物半導體場效電晶體）和控制晶片聯合封裝在 同一個封裝體内，以減少週邊元件數量，同時提高電源 等的利用效率。 [0003] 對於DMOSFET (雙擴散金屬氧化物半導體場效電晶體）晶 片來說，如果能將其設置在晶片上表面的源極與導線架 的晶片基座連接’就能使該晶片基座的底面外露作為地 極和散熱之用。 [0004] 上述封裝結構的實現’需要將晶片翻轉後安裝在晶片基 座上’這將面臨如下的一些問題：例如，如何使導線架 外露的晶片基座具有盡可能大而簡單的外形，並使晶片 源極與該晶片基座能有最大的連接，以獲取更好的散熱 性能；如何在翻轉並安裝晶片至晶片基座時，使晶片上 表面設置的閘極與該控制晶片之間具有可靠的電氣連接 [0005] 然而，圖1所示的現有一種具體的半導體元件，其是對應 圖2的電路原理設置的，包含有p型高端m〇SFET(HS)、 N型低端MOSFET (LS)以及控制晶片，三者在導線架的 同一個平面上安裝。那麼封裝體的安裝空間很大程度上 100115173 表單編號A0101 第4頁/共45頁 1(ir 201244052 [0006] Ο [0007] ❹ [0008] [0009] [0010] [0011] 限制了該高端MOSFET、低端MOSFET以及控制晶片的尺寸 ’這對功率半導體元件的性能提高具有很大的影響。 而且’上述平面佈置的封裝結構中，如低端M〇SFET等晶 片上表面的電極，通過導線鍵合直接與其他晶片連接， 或由導線連接至引腳後’再與連接至同一引腳的其他晶 片或外部元器件連接。因此，該種封裝結構很難實現將 晶片翻轉安裝，使其上表面的源極與晶片基座連接，也 就無法獲得上述外露晶片基座作為地極和幫助散熱的效 果。 【發明内容】 本發明的目的是提供一種聯合封裝的功率半導體元件， 能夠將多個半導體晶片立體封裝在同一個封裝體中，以 減小半導體元件的整體尺寸；並能夠在同樣大小的封裝 體内增大晶片的尺寸，來有效提高半導體元件的產品性 能。進一步使翻轉設置的底層晶片的頂部源極能夠與晶 片基座連接，將該晶片基座的底面最大面積外露後連接 地極並幫助散熱。 為了達到上述目的，本發明的技術手段是提供一種聯合 封裝的功率半導體元件，包含： 分別具有底部汲極、頂部閘極和頂部源極的高端m〇sfet 晶片和低端MOSFET晶片； 導線架，其設置有晶片基座，以及與晶片基座分隔且無 電性連接的若干引腳； 该低端MOSFET晶片翻轉粘接在該晶片基座上，使其頂部 100115173 表單編號A0101 第5頁/共45頁 1003213894-0 201244052 源極與該晶片基座的頂面形成電性連接；該頂部源極， 還通過與該晶片基座封裝後外露的底面電極電性連接， 並進行散熱； [0012] 第一金屬連接板，堆疊粘接在該低端M〇SFET晶片的底部 汲極上； [0013] 該兩端MOSFET晶片直接堆疊或翻轉後堆疊粘接在該第一 金屬連接板上，使高端MOSFET晶片的底部汲極或者翻轉 後的頂部源極，通過該第一金屬連接板與該低端m〇sfet 晶片的底部沒極形成電性連接； [0014] 第二金屬連接板，堆疊粘接並電性連接在該高端mosFET 晶片的頂部源極’或翻轉後的該底部沒極上； [0015] 控制晶片，也設置在該晶片基座上，其設置的若干電極 ，分別與該若干引腳之間，以及與該高端和低端的 MOSFET晶片的該電極之間，對應形成電性連接。 [0016] 一種較佳實施例中，該若干引腳包含低端閘極引腳，其 設置有引出部分及内聯部分； [0017] 對應該内聯部分的位置，在該晶片基座上開設有一相匹 配的缺口，使該低端閘極引腳在該缺口内，與該晶片基 座之間形成相互分離的對應設置； [0018] 翻轉設置的該低端MOSFET晶片，其頂部閘極粘接在該内 聯部分上，與該低端閘極引腳形成電性連接。 [0019] 該低端閘極引腳的内聯部分，由底面向上設置有一半腐 蚀區；該半腐蚀區在封裝時被塑封材料填充。 100115173 表單編號A0101 第6頁/共45頁 1003213894-0 201244052 [0020] ^與該内聯部分相對應的晶片基座侧邊，由底面向上也 有半腐蚀區，斜腐*區，其寬度與㈣聯部分的 寬度相叹配，並在封裝時被㈣材料填充。 _]該㈣U片通過連接導線鍵合，形成與該低端閘極引腳 的引出部分的電性連接。 闕另—種較佳實施射，該聯合封裝的功率半導體元件還 包含第二中間聯結件； [0023] _安裝的該低端M〇SFET晶片，其了頁部閑極與該第二中 間聯結件的導電的上表面對應枯接並形成電性連接； 國該第二中間聯結件，其下表面雌在該晶片基座上，並 與該晶片基座相絕緣。 [0025]該低端MOSFET晶片，其頂部源極通過加厚的導電粘接膠 ’電性連接在該晶片基座上； [0026] 該加厚的導電粘接膠的厚度，與該晶片基座上設置第二 中間聯結件及其上下方的粘接膠後的厚度相匹配。 [0027] 該實施例的一種改進結構中’對應該低端MOSFET晶片的 頂部閘極位置’在該晶片基座的頂面上形成有第二凹槽 [0028] 該第二中間聯結件，對應粘接在相匹配的該第二凹槽内 ’並在其周邊與該晶片基座分離且相絕緣。 [⑻29]該第二中間聯結件是一導電金屬片，其下表面通過絕緣 的枯接耀’固定貼附在該晶片基座上或該第二凹槽内。 100115173 表單編號A0101 第7頁/共45頁 1003213894-0 201244052 [0030] 或者’該第二中間聯結件設置有導電的金屬上層和絕緣 體下層；該絕緣體下層的底面通過導電或不導電的粘接 膠’固定貼附在該晶片基座上或該第二凹槽内。 [0031] 該控制晶片與該第二中間聯結件的上表面電性連接，以 形成其與翻轉安裝的該低端Μ 〇 S F E T晶片的頂部閘極的電 性連接。 [0032] 還有一種較佳實施例，該控制晶片，其底面絕緣粘接在 該晶片基座上； [0033] 翻轉安裝的該低端MOSFET晶片，覆蓋在該控制晶片頂面 的一部分；該被覆蓋頂面上的其中一些電極，與該低端 MOSFET晶片的頂部閘極和一部分頂部源極直接粘接，形 成電性連接。 [0034] 該低端MOSFET晶片的其餘頂部源極，通過加厚的導電枯 接膠’電性連接在該晶片基座上； [0035] 該加厚的導電粘接膠的厚度，與該晶片基座上設置控制 晶片及其上下方的粘接膠後的厚度相匹配。 [0036] 該實施例的—種改進結構中，該晶片基座的頂面形成有 晶片凹槽； [0037] 該控制晶片對應粘接在相匹配的該晶片凹槽内，並在其 周邊與該晶片基座相分離且相絕緣。 [0038] 另外，該聯合封裝的功率半導體元件，還包含第一中間 聯結件； [0039] 100115173 表單编號A0101 翻轉安裝的該高端MOSFET晶片 第8頁/共45頁 ，其頂部閘極與該第一中 1003213894-0 201244052 [0040] [0041] [0042] Ο [0043] [0044] [0045] Ο [0046] [0047] 100115173 間聯結件的導電的上表面對應粘接並形成電性連接； 該第一中間聯結件，其下表面粘接在該第一金屬連接板 上’並與該第一金屬速接板相絕緣。 該西端MOSFET晶片，其頂部源極通過加厚的導電粘接膠 ，電性連接在該第一金屬連接板上； 該加厚的導電枯接膠的厚度’與該第—金屬連接板上設 置第一中間聯結件及其上下方的粘接膠後的厚度相匹配 〇 該實施例的一種改進結構中，對應該高端M〇SFET晶片的 頂部閘極位置，在該第一金屬連接板的頂面上形成有第 —凹槽； 該第一中間聯結件，對應粘接在相匹配的該第一凹槽内 ’並在其周邊與該第一金屬連接板分離且相絕緣。 *亥第一中間聯結件是一導電金屬片，其下表面通過絕緣 的粘接膠，固定貼附在該第一金屬連接板上或該第一凹 槽内。 或者’該第一中間聯結件設置有導電的金屬上層和絕緣 體下層；該絕緣體下層的底面通過導電或不導電的粘接 膠’固定贴附在該第一金屬連接板上或該第一凹槽内。 該控制晶片與該第一中間聯結件的上表面電性連接，以 形成其與翻轉安裝的該南端MOSFET晶片的頂部閘極的電 性連接。 該高端MOSFET晶片的頂部源極及頂部閘極，或者翻轉安 表單編號A0101 第9頁/共45頁 1003213894-0 [0048] 201244052 裝的該高端MOSFET晶片的底部汲極，分別與該控制晶片 通過連接導線鍵合形成電性連接。 [0049] [0050] [0051] [0052] [0053] [0054] 100115173 該若干引腳包含開關引腳，其與該第一金屬連接板電性 連接’ s亥控制晶片，與該開關引腳通過連接導線鍵合’ 形成其與該第一金屬連接板的電性連接。 該若干引腳包含高端源極引腳；高端M0SFET晶片的頂部 源極，通過該第二金屬連接板，與該高端源極引腳形成 電性連接。 該若干引腳包含高端汲極引腳；翻轉安裝的該高端 MOSFET晶片的底部汲極，通過該第二金屬連接板與所述 高端汲極引腳形成電性連接。 本發明該聯合封裝的功率半導體元件，其優點在於：本 發明由於在晶片基座上依次向上堆疊設置了低端M0SFET 晶片、第一金屬連接板、高端MOSFET晶片和第二金屬連 接板，實現了該些半導體晶片在同一封裝體中的立體封 裝，減小了功率半導體元件的整體尺寸。 在上述一些較佳的實施例中，分別描述了在第一金屬連 接板的頂面上，和/或晶片基座的頂面上，分別開設有第 一、第二凹槽的結構，使第一、第二中間聯結件能夠絕 緣設置在對應凹槽内，分別將翻轉安裝的高端和低端 MOSFET晶片的頂部閘極引出，繼而通過連接導線鍵合實 現與其他晶片或元器件的電性連接。 在另一些較佳實施例中，還描述了在晶片基座的頂面開 設晶片凹槽的結構，其與上述第二凹槽的結構可同時或 表單編號A0101 第10頁/共45頁 1003213894-0 201244052 [0055] f) [0056] [0057]201244052 VI. Description of the Invention: [Technical Leadership of Invention] [0001] The present invention relates to a power semiconductor element, and more particularly to a structure in which a plurality of wafers and the like are collectively packaged in the same power semiconductor element. [Prior Art·] [0002] At present, in a typical power semiconductor device, a MOSFET wafer (metal oxide semiconductor field effect transistor) and a control wafer are usually packaged in the same package to reduce the number of peripheral components. Improve the utilization efficiency of power supplies and the like. [0003] For a DMOSFET (Double-Diffused Metal Oxide Semiconductor Field Effect Transistor) wafer, if it can be placed on the upper surface of the wafer and the source of the wafer is connected to the wafer holder of the lead frame, the wafer base can be The bottom surface is exposed as a ground and heat sink. [0004] The implementation of the above package structure 'requires the wafer to be flipped over and mounted on the wafer base'" will face the following problems: for example, how to make the exposed wafer base of the lead frame have the largest possible and simple shape, and Having the largest connection between the source of the wafer and the base of the wafer for better heat dissipation performance; how to have the gate between the upper surface of the wafer and the control wafer when flipping and mounting the wafer to the wafer base Reliable Electrical Connection [0005] However, the prior art specific semiconductor component shown in FIG. 1 is provided corresponding to the circuit principle of FIG. 2, and includes a p-type high-end m〇SFET (HS) and an N-type low-side MOSFET ( LS) and the control chip, the three are mounted on the same plane of the lead frame. Then the installation space of the package is largely 100115173 Form No. A0101 Page 4 / Total 45 Page 1 (ir 201244052 [0006] [0007] [0008] [0011] [0011] The high-side MOSFET is limited The low-side MOSFET and the size of the control wafer' have a great influence on the performance improvement of the power semiconductor device. Moreover, in the above-mentioned planar arrangement of the package structure, the electrode on the upper surface of the wafer such as the low-side M〇SFET is passed through the wire bond. It is directly connected to other wafers, or connected by wires to pins, and then connected to other wafers or external components connected to the same pin. Therefore, it is difficult to flip the wafer to the upper surface of the package structure. The source is connected to the wafer base, so that the exposed wafer base can be obtained as a ground electrode and help heat dissipation. SUMMARY OF THE INVENTION An object of the present invention is to provide a jointly packaged power semiconductor component capable of multiple semiconductors The wafer is three-dimensionally packaged in the same package to reduce the overall size of the semiconductor component; and the wafer size can be increased in the same size package. In order to effectively improve the product performance of the semiconductor component, the top source of the flip-chip underlying wafer can be further connected to the wafer pedestal, and the maximum area of the bottom surface of the wafer pedestal is exposed and connected to the ground electrode to help dissipate heat. The technical means of the present invention is to provide a jointly packaged power semiconductor component, comprising: a high-end m〇sfet chip and a low-end MOSFET chip having a bottom drain, a top gate and a top source, respectively; a lead frame provided with a wafer a pedestal, and a plurality of pins separated from the wafer pedestal and electrically connected; the low-end MOSFET wafer is flip-bonded on the wafer pedestal to make the top 100115173 Form No. A0101 Page 5 / Total 45 Page 1003213894-0 The source is electrically connected to the top surface of the wafer base; the top source is electrically connected to the exposed bottom electrode after the wafer base is packaged, and heat is dissipated; [0012] the first metal connecting plate Stacking and bonding on the bottom drain of the low-side M〇SFET wafer; [0013] the two-terminal MOSFET wafer is directly stacked or flipped and stacked and bonded On the first metal connection board, the bottom drain of the high-side MOSFET chip or the flipped top source is electrically connected to the bottom of the low-side m〇sfet wafer through the first metal connection plate; a second metal connection plate, stacked and electrically connected to the top source of the high-side MOSFET wafer or to the inverted bottom of the bottom; [0015] a control wafer, also disposed on the wafer substrate, A plurality of electrodes are disposed between the plurality of pins and between the electrodes of the high-side and low-side MOSFET wafers to form an electrical connection. [0016] In a preferred embodiment, the plurality of pins comprise a low-side gate pin provided with a lead-out portion and an in-line portion; [0017] a position corresponding to the in-line portion is opened on the wafer base Having a matching gap, the low-side gate pin is disposed in the gap, and a corresponding arrangement is formed between the wafer base and the wafer base; [0018] the low-end MOSFET wafer is flipped and the top gate is viscous Connected to the inline portion to form an electrical connection with the low-side gate pin. [0019] The inscribed portion of the low-side gate pin is provided with a semi-etched region from the bottom surface; the semi-etched region is filled with a molding material during packaging. 100115173 Form No. A0101 Page 6 of 45 1003213894-0 201244052 [0020] ^ The side of the wafer base corresponding to the inline part, there is also a semi-corrosive zone from the bottom surface, oblique shard * area, its width and (4) The width of the joint is matched and filled with (4) material during packaging. _] The (four) U-chip is bonded by a connecting wire to form an electrical connection with the lead-out portion of the low-side gate pin. Preferably, the jointly packaged power semiconductor component further comprises a second intermediate junction; [0023] the low-end M〇SFET wafer mounted, the page idler and the second intermediate junction The conductive upper surface of the piece corresponds to the ground and forms an electrical connection; the second intermediate joint member has a lower surface on the wafer base and is insulated from the wafer base. [0025] The low-end MOSFET chip has a top source electrically connected to the wafer base via a thick conductive adhesive; [0026] the thickness of the thickened conductive adhesive and the wafer base The thickness of the second intermediate joint member and the upper and lower adhesives are matched on the seat. [0027] In a modified structure of this embodiment, 'the top gate position corresponding to the low-end MOSFET wafer' is formed with a second recess [0028] on the top surface of the wafer base, corresponding to the second intermediate joint, corresponding to Bonding in the matching second recesses' is separated and insulated from the wafer pedestal at its periphery. [(8) 29] The second intermediate joint member is a conductive metal sheet, the lower surface of which is fixedly attached to the wafer base or the second recess by an insulating squeak. 100115173 Form No. A0101 Page 7 of 45 1003213894-0 201244052 [0030] Or 'The second intermediate joint is provided with a conductive upper metal layer and a lower insulator layer; the bottom surface of the lower layer of the insulator is made of a conductive or non-conductive adhesive 'Fixedly attached to the wafer base or the second recess. And [0031] the control wafer is electrically connected to the upper surface of the second intermediate junction member to form an electrical connection with the top gate of the flip-chip mounted low-side F S F E T wafer. [0032] In another preferred embodiment, the control wafer has a bottom surface that is insulatively bonded to the wafer base; [0033] flipping the mounted low-end MOSFET wafer over a portion of the top surface of the control wafer; Some of the electrodes on the top surface of the cover are directly bonded to the top gate of the low-side MOSFET wafer and a portion of the top source to form an electrical connection. [0034] the remaining top source of the low-side MOSFET chip is electrically connected to the wafer base through a thick conductive adhesive; [0035] the thickness of the thickened conductive adhesive, and the wafer The thickness of the control wafer and the adhesive tape above and below it is matched on the pedestal. [0036] In a modified structure of the embodiment, the top surface of the wafer base is formed with a wafer groove; [0037] the control wafer is correspondingly bonded in the matching groove of the wafer, and is in the periphery thereof The wafer susceptor is phase separated and insulated. [0038] In addition, the jointly packaged power semiconductor component further includes a first intermediate junction; [0039] 100115173 Form No. A0101 flipped the high-side MOSFET wafer mounted on page 8 of 45, with the top gate and the First, 1003213894-0 201244052 [0042] [0044] [0047] [0047] The electrically conductive upper surface of the 100115173 joint is bonded and electrically connected The first intermediate joint member has a lower surface bonded to the first metal connecting plate 'and insulated from the first metal quick-connecting plate. The western-side MOSFET chip has a top source electrically connected to the first metal connecting plate through a thick conductive adhesive; the thickened conductive adhesive has a thickness 'set with the first metal connecting plate The thickness of the first intermediate junction member and its upper and lower adhesives is matched. In a modified structure of this embodiment, the top gate position of the high-end M〇SFET wafer is corresponding to the top of the first metal connection plate. A first groove is formed on the surface; the first intermediate joint member is correspondingly bonded in the matching first groove and is separated from and insulated from the first metal connecting plate at a periphery thereof. The first intermediate joint member is a conductive metal sheet, and the lower surface thereof is fixedly attached to the first metal connecting plate or the first recess by an insulating adhesive. Or 'the first intermediate joint member is provided with a conductive upper metal layer and a lower insulator layer; the bottom surface of the lower layer of the insulator is fixedly attached to the first metal connecting plate or the first groove by a conductive or non-conductive adhesive Inside. The control wafer is electrically coupled to the upper surface of the first intermediate junction to form an electrical connection with the top gate of the flip-mounted south end MOSFET wafer. The top and top gates of the high-side MOSFET chip, or the flip-up form number A0101, page 9 / total 45 pages 1003213894-0 [0048] 201244052 installed the bottom drain of the high-side MOSFET chip, respectively, with the control wafer The connecting wires are bonded to form an electrical connection. [0054] [0054] 100115173 The plurality of pins include a switch pin electrically connected to the first metal connection board, and the switch pin The electrical connection with the first metal connecting plate is formed by connecting wire bonding '. The plurality of pins include a high side source pin; a top source of the high side MOSFET chip is electrically connected to the high side source pin through the second metal connection plate. The plurality of pins comprise a high-side drain pin; the bottom drain of the high-side MOSFET chip that is flipped mounted is electrically connected to the high-side drain pin through the second metal link. The joint packaged power semiconductor device of the present invention has the advantage that the present invention realizes that the low-side MOSFET chip, the first metal connection plate, the high-side MOSFET chip and the second metal connection plate are sequentially stacked on the wafer base. The three-dimensional packaging of the semiconductor wafers in the same package reduces the overall size of the power semiconductor components. In some of the above preferred embodiments, the first and second recesses are respectively formed on the top surface of the first metal connecting plate and/or the top surface of the wafer base. 1. The second intermediate connecting member can be insulated and disposed in the corresponding groove, respectively extracting the top gates of the flip-mounted high-end and low-end MOSFET chips, and then electrically connecting with other wafers or components through connecting wire bonding. . In other preferred embodiments, a structure in which a groove of a wafer is formed on a top surface of the wafer base is described, and the structure of the second groove may be simultaneously or in the form number A0101, page 10, total 45, 1003213894- 0 201244052 [0055] f) [0057]

G 分別设置。絕緣固定在該晶片凹槽内的控制晶片，與其 上方的低端MOSFET晶片的頂部源極、頂部閘極可直接對 應電性粘接，節省連接導線，也簡化了封裴技術。而且 ，該結構將控制晶片也進行了立體封裝，進一步減小了 功率半導體元件的整體厚度。 本發明所述翻轉安裝的低端M〇SFET晶片，其至少一部分 頂部源極，與晶片基座電性連接，並通過該晶片基座外 露的底面與地極連接的同時，有效進行散熱。 在一些實施例中，還可以在該低端閘極引腳的内聯部分 ，以及晶片基座上與之對應的側邊，從底面向上分別設 置半腐蝕區；該半腐蝕區在封裝時被塑封材料填充，增 加元件的連接強度同時，還能夠使該晶片基座的外露底 面結構簡單美觀。 本發明上述使多個晶片堆疊設置，且使晶片基座底面外 露的面積盡可能大的實施結構，可以方便地擴展至其他 多個半導體晶片、控制器等其他各種元器件的立體封裝 ，形成各種半導體元件。相比現有半導體元件的封裝結 構，本發明在同樣大的導線架上可充分擴展各晶片的尺 寸，有效提高半導體元件的產品性能。 [0058] 【實施方式】 以下根據圖4〜圖21，詳細說明本發明的·一些較佳實施例 ，以更好的理解本發明的技術手段和有益效果。 以下實施例中，都是由2個MOSFET晶片分別作為高端 MOSFET晶片和低端M0SFET晶片與控制晶片連接後，將三 100115173 表單編號A0101 第11頁/共45頁 1003213894-0 [0059] 201244052 者聯合封裝在同一個封裝體内，形成獨立的功率半導體 元件。但應當注意的是’這些具體描述及實例並非用來 限制本發明的範圍。 [0060] 如圖2所示，上述低端MOSFET (LS)是N型M0SFET晶片 ’高端MOSFET (HS)是P型M0SFET晶片。該高端和低端 MOSFET晶片均具有底部汲極、頂部源極和頂部閘極；其 中’高端MOSFET (HS)的閘極G1及低端MOSFET (LS) 的閘極G2均與該控制晶片連接；高端MOSFET (HS)的源 極S1連接電源接入端Vin，其汲極D1連接低端MOSFET ( LS)的汲極D2連接，作為開關端Lx與該控制晶片連接； 而低端MOSFET的源極S2與接地端Gnd連接，形成該功率 半導體元件。 [0061] 如圖3所示’上述低端MOSFET ( LS )是N型MOSFET晶片 ’高端MOSFET (HS)也是N型MOSFET晶片。該高端和低G is set separately. The control wafer insulated and fixed in the groove of the wafer can directly correspond to the top source and the top gate of the low-side MOSFET chip above it, thereby saving the connecting wires and simplifying the sealing technology. Moreover, the structure also performs a three-dimensional encapsulation of the control wafer, further reducing the overall thickness of the power semiconductor device. The flip-mounted low-side M〇SFET chip of the present invention has at least a portion of the top source electrically connected to the wafer pedestal and is thermally coupled to the ground via the exposed bottom surface of the wafer pedestal. In some embodiments, a semi-etched region may also be disposed from the bottom surface to the inscribed portion of the low-side gate pin and the corresponding side of the wafer base; the semi-etched region is The filling of the molding material increases the connection strength of the component, and also enables the exposed bottom surface structure of the wafer base to be simple and beautiful. According to the present invention, the embodiment in which a plurality of wafers are stacked and the exposed area of the bottom surface of the wafer base is as large as possible can be easily extended to three-dimensional packages of other semiconductor chips, controllers, and the like, and various types of components are formed. Semiconductor component. Compared with the package structure of the conventional semiconductor device, the present invention can sufficiently expand the size of each wafer on the same large lead frame, thereby effectively improving the product performance of the semiconductor device. [Embodiment] Hereinafter, some preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 21 to better understand the technical means and advantageous effects of the present invention. In the following embodiments, after two MOSFET chips are connected as a high-side MOSFET chip and a low-side MOSFET chip and a control chip, respectively, the three 100115173 form number A0101 page 11/45 pages 1003213894-0 [0059] 201244052 are combined. Packaged in the same package to form separate power semiconductor components. It should be noted, however, that the specific description and examples are not intended to limit the scope of the invention. As shown in FIG. 2, the low-side MOSFET (LS) is an N-type MOSFET wafer. The high-side MOSFET (HS) is a P-type MOSFET chip. The high-side and low-side MOSFET chips each have a bottom drain, a top source, and a top gate; wherein the gate G1 of the high side MOSFET (HS) and the gate G2 of the low side MOSFET (LS) are connected to the control chip; The source S1 of the high-side MOSFET (HS) is connected to the power supply terminal Vin, and the drain D1 is connected to the drain D2 of the low-side MOSFET (LS), and is connected to the control chip as the switch terminal Lx; and the source of the low-side MOSFET S2 is connected to the ground terminal Gnd to form the power semiconductor element. [0061] As shown in FIG. 3, the above low-side MOSFET (LS) is an N-type MOSFET chip. The high-side MOSFET (HS) is also an N-type MOSFET chip. The high end and low

端MOSFET晶片均具有底部汲極、頂部源極和頂部閘極； 其中’高端MOSFET (HS)的閘極G3及低端MOSFET (LS )的閘極G2均與該控制晶片連接；高端M0SFET (HS)的 汲極D3連接電源接入端Vin，其源極53連接低端m〇sfet (LS)的沒極D2連接，作為開關端LX與該控制晶片連接 ’而低端MOSFET的源極S2與接地端Gnd連接，形成該功 率半導體元件。 [0062] 實施例1-1 [0〇63]凊配合參見圖2、圖4、圖6所示，是本發明所述功率半導 體元件的一種實施結構，其中圖4是該功率半導體元件的 100115173 表單編號A0101 第12頁/共45頁 1003213894-0 201244052 [0064] [0065]Ο [0066] [0067] Ο [0068] 總體結構示意圖，圖6是圖4中A-Α位置的剖面圖。對應圖 2所示的電路原理圖可見，該功率半導體元件中將p型的 高端MOSFET晶片30 ’ N型的低端MOSFET晶片20和控制晶 片40進行了聯合封裝。 該功率半導體元件中，包含一導線架，該導線架上設置 有一晶片基座100，以及與該晶片基座1〇〇分隔且無電性 連接的若干引腳。 該高端和低端MOSFET晶片分別設置有底部汲極、頂部源 極和頂部閘極；與之對應，該若干引腳包含有高端源極 引腳72、低端閘極引腳71、開關引腳74以及若干控制引 腳75。 該晶片基座100的形狀大小，至少對應該低端MOSFET晶 片20與控制晶片40在同一平面佈置時的形狀大小。 該低端閘極引腳71的一端作為引出部分712，另一端作為 内聯部分711。對應該内聯部分711的位置，在該晶片基 座100的侧邊上開設有一相匹配的缺口 1〇1，使該低端閘 極引腳71與該晶片基座1 〇 〇之間形成相互分離的對應設置 〇 該低端MOSFET晶片20翻轉後，通過導電型的枯接膠91固 定貼附至該晶片基座100上’該低端jt〇SFET晶片20的主 體覆蓋在晶片基座100的頂面一端，使其頂部源極22與該 晶片基座100形成電性連接；同時其頂部閘極21對應覆蓋 在該低端閘極引腳71的内聯部分711上，並通過導電的粘 接膠91與該低端閘極引腳71粘接形成電性連接。 100115173 表單編號A0101 第13頁/共45頁 1003213894-0 201244052 [0069] 該低端閘極引腳71的内聯部分711，由低端閘極引腳71的 底面向上，設置有一半腐蝕區713，其在封裝時將被塑封 材料填充’以增加該内聯部分711與低端M〇SFET晶片2〇 的連接強度。在與該内聯部分71丨對應的晶片基座1〇〇側 邊，根據該内聯部分711的寬度，從晶片基座1〇〇的底面 向上也設置有半腐蝕區104 ;該半腐蝕區j 〇4在封裝時也 被塑封材料填充，以使該晶片基座1〇〇的外露底面形狀簡 單。 [0070] 由於，包含低端閘極引腳71的引出部分712的上述所有引 腳，以及除該半腐蝕區1〇4之外的晶片基座1〇{)底面部分 ，都將如圖8所示在封裝後暴露在該功率半導體元件的底 面之外。該低端MOSFET晶片20的頂部源極22，通過該晶 片基座1〇〇的底面與地極連接，形成了圖2中的接地端Gnd 。同時，晶片基座1〇〇的底面大部分面積暴露在封裝體外 ’具有良好的散熱效果。 [00Ή]該控制晶片40，固定設置在該晶片基座1〇〇的頂面另一端 。3亥控制晶片40頂面設置有若干電極，分別通過若干導 線鍵合，使該若干控制引腳75 ,以及該低端閘極引腳71 的引出部分712，分別與該控制晶片40形成電性連接。 [0072]第一金屬連接板51 (或者也可以是金屬連接帶之類的金 屬連接體），通過導電的粘接膠91固定貼附在該低端 MOSFET晶片20上，使該低端M0SFET晶片2〇的底部汲極 23與該第一金屬連接板51的底面形成電性連接，並通過 該第一金屬連接板51進一步與該開關引腳74形成電性連 接。 100115173 表單編號A0101 第14頁/共45頁 1003213894 201244052 [0073] 该向端MOSFET晶片30，通過導電的粘接膠91固定貼附至 該第一金屬連接板51上，使其底部汲極33與該第一金屬 連接板51的頂面形成電性連接，並經由該第一金屬連接 板51同時與該低端M0SFET晶片20的底部汲極23及該開關 引腳74形成電性連接。通過連接導線80鍵合，將該開關 引腳74電性連接至該控制晶片4〇的電極上，形成如圖2中 開關端Lx的電路連接。 [0074] Ο [0075] 該高端M0SFET晶片30的頂部閘極31、頂部源極32，與該 控制晶片40之間，也分別通過連接導線8〇鍵合形成電性 連接。 第二金屬連接板52 ’通過導電的粘接膠91固定貼附在該 高端M0SFET晶月30上，使該高端M0SFET晶片30的頂部 源極32與該第二金屬連接板52形成電性連接，並通過該 第二金屬連接板52進一步與該高端源極引腳72實現電性 連接，形成圖2中的電源接入端Vi η。 [0076] ❹ [0077] 實施例1 - 2 請配合參見圖3、圖5、圖6、圖7所示，其中圖5是該功率 半導體元件的總體結構示意圖，圖6是圖5中Α-Α位置的剖 面圖’圖7是圖5中C-C位置的剖面囷。對應圖3所示的電 路原理圖可見，該功率半導體元件中聯合封裝了控制晶 片40以及Ν型的高端和低端M0SFET晶片。 本實施例中所述晶片基座1〇〇以及與其相分隔的若干引腳 的導線架結構與上述實施例中相同；控制晶片40、低端 M0SFET晶片20在晶片基座100上連接設置的結構與上述 100115173 表單編號Α0101 第15頁/共45頁 1003213894-0 [0078] 201244052 實施例中也相同。現簡述如下： [_]配合參見圖5、圖6和圖8所示，該低端M0SFET晶片2〇翻 轉後粘接在晶片基座100上，其頂部源極22與該晶片基座 100電性連接，其頂部閘極21與該低端閘極引腳71的内聯 部分711電性連接。第—金屬連接板51堆疊在該低端 MOSFET晶片20上’形成該低端M〇SFET晶片2〇的底部汲 極23與該開關引腳74之間的電性連接。該控制晶片4〇也 設置在該晶片基座100上，通過連接導線8〇鍵合’實現控 制晶片40與若干控制引腳75、該低端閘極引腳71的引出 部分71 2、該開關引腳74之間的電性連接◊該晶片基座 1 00與該低端閘極引腳71的内聯部分711相對應的位置， 從底面向上分別設置有半腐蝕區1〇4和713，並在封裝時 由塑封材料填充該半腐蝕區1〇4和713。所有引腳（含低 端閘極引腳71的引出部分712)，以及除該半腐敍區丨〇4 之外的晶片基座100底面部分，都在封裝後暴露在該功率 半導體元件的底面之外。 [〇〇8〇]請配合參見圖3、圖5、圖7所示，與上述實施例中不同， 由於該咼端MOSFET晶片30是一N型MOSFET，其在翻轉後 堆疊設置在該第一金屬連接板51上，使該高端恥””晶 片30的頂部源極32與該第一金屬連接板51通過導電的粘 接膠91固定並形成電性連接。此時，該高端仙”以晶片 30的頂部源極32與該低端MOSFET晶片20的底部汲極23， 經由該第一金屬連接板51形成電性連接，並進一步通過 该開關引腳7 4與s亥控制晶片4 0實現電性連接，形成圖3中 的開關端Lx。 100115173 表單編號A0101 第16頁/共45頁 1003213894-0 201244052 [0081] 而翻轉安裝的該高端MOSFET晶片30，其頂部閘極31通過 一第一中間聯結件61，固定設置在該第一金屬連接板51 上，並通過該第一中間聯結件61形成該頂部閘極31與該 控制晶片40的電性連接。 [0082] 具體的，該第一金屬連接板51的頂面開設有一第一凹槽 511，該第一凹槽511的形狀大小與該第一中間聯結件61 相匹配，並與翻轉安裝的該高端MOSFET晶片30的頂部閘 極31位置相對應。 〇 [0083] 該第一中間聯結件61與其下方的該第一金屬連接板51之 間相絕緣，而與其上方的該高端MOSFET晶片30的頂部閘 極31之間電性連接。例如，該第一中間聯結件61可以是 一導電金屬片，其下表面通過絕緣的粘接膠92貼附在該 第一凹槽511内；或者該第一中間聯結件61也可以設置上 表面為導電的金屬上層，下表面為玻璃層等絕緣體下層 ，此時，該絕緣體下層的底面可通過導電或不導電的粘 接膠與該第一凹槽511固定連接。 C) 1 [0084] 該第一中間聯結件61的上表面與該高端MOSFET晶片30的 頂部閘極31之間，通過導電的粘接膠91形成電性連接。 該頂部閘極31不完全覆蓋該第一中間聯結件61的上表面 ，使該控制晶片40與該第一中間聯結件61之間由連接導 線80鍵合，實現控制晶片40與該頂部閘極31之間的電性 連接。 [0085] 第二金屬連接板52，通過導電的粘接膠91固定貼附在該 高端MOSFET晶片30上，使該高端MOSFET晶片30的底部 100115173 表單編號A0101 第17頁/共45頁 1003213894-0 201244052 汲極33與該第二金屬連接板52形成電性連接，並通過該 第二金屬連接板52進一步與高端汲極引腳73實現電性連 接，形成圖3中的電源接入端ηn。該控制晶片4〇與該底 部汲極33之間也通過連接導線8〇鍵合形成電性連接。 [0086] [0087] [0088] [0089] 實施例2 -1 β月配合參見圖2、圖9、圖π所示，其中圖9是該功率半導 體π件的總體結構示意圖，圖η是圖9*Β_Β位置的剖面 圖。對應圖2所示的電路原理圖可見，該功率半導體元件 中將Ρ型的高端MOSFET晶片30，Ν型的低端MOSFET晶片 20和控制晶片40進行了聯合封裝。 與實施例卜1中相類似，本實施例在導線架的晶片基座 1〇〇—端没置了控制晶片，在另一端向上堆疊設置了翻 轉的低端MOSFET晶片20、第一金屬連接板51、高端 MOSFET晶片30和第二金屬連接板52。其中，第一金屬連 接板51在其頂面和底面，分別與該高端和低端M〇SFET晶 片的底部汲極23和33電性連接，並連接至該開關引腳74 ，進一步在開關引腳74上鍵合連接導線8〇實現與該控制 晶片40的電性連接，形成圖2中開關端1^。第二金屬連接 板52在該高端MOSFET晶片30上，與其頂部源極32電性連 接，並通過高端源極引腳72引出，形成圖2中電源輸入端 Vin。該控制晶片40還通過若干連接導線8〇鍵合，分別與 該鬲端MOSFET晶片30的頂部閘極31、頂部源極32，以及 若干控制引腳7 5電性連接。 與上述實施例1 -1中結構不同，本實施例中，與翻轉安裝 100115173 表單編號A0101 第18頁/共45頁 1003213894-0 201244052 [0090] Ο [0091] ❹ [0092] 的該低端MOSFET晶片20的頂部閘極21位置相對應，在該 晶片基座100的頂面半腐#形成有一第二凹槽102。一第 一中間聯結件6 2與該第二凹槽1 0 2相匹配，且對應固定在 該第二凹槽102内，並保持與該晶片基座100分離且相絕 緣。 具體的，與實施例1 - 2中類似，該第二中間聯結件6 2可以 是一導電金屬片，其下表面通過絕緣的粘接勝92貼附在 該第二凹槽1 〇 2内；或者該第二中間聯結件6 2也可以設置 上表面為導電的金屬上層，下表面為玻璃層等絕緣體下 層’此時，該絕緣體下層的底面可通過導電或不導電的 粘接膠與該第二凹槽102固定連接。 翻轉的該低端M0SFET晶片20，其頂部閘極21通過導電的 粘接膠91，與該第二中間聯結件62的導電上表面形成電 性連接。該頂部閘極21並不完全覆蓋該第二中間聯結件 62，使該控制晶片40與該第二中間聯結件62的上表面之 間由連接導線80鍵合，實現控制晶片40與該頂部閘極21 之間的電性連接。 同時，該低端M0SFET晶片20的頂部源極22，通過導電的 枯接膝91與該晶片基座1〇〇頂面形成電性連接，並通過該 晶片基座100的底面與地極連接，形成了圖2中的接地端 Gnd。 由於本實施例將該第二中間聯結件62設置在該晶片基座 100上的第二凹槽102内，實施例1-1中低端閘極引腳η 的引出部分712 ’可在本實施例中替換為一增設的控制引 100115173 表單編號A0101 第19頁/共45頁 1003213894-0 [0093] 201244052 腳75。而且，由於不需要設置實施例i-丨中晶片基座丨〇〇 和低端閘極引腳71底面向上的半腐蝕區，因而，如圖13 所示’本實施例中晶片基座100的底面在封裝後可完全暴 露在該功率半導體元件外，散熱面積更大。 [0094] 實施例2 - 2 [0095] 請配合參見圖圖3、圖圖7、圖10、圖11所示，其中圖1〇 是該功率半導體元件的總體結構示意圖，圖7是圖1〇中〇 C位置的剖面圖，圖11是圖1 〇中B-B位置的剖面圖。對應 圖3所示的電路原理圖可見，該功率半導體元件中聯合封 裝了控制晶片40以及N型的高端和低端MOSFET晶片。 [0096] 本實施例在導線架的晶片基座1〇〇—端設置了控制晶片40 ’在另一端向上堆疊設置了翻轉的低端MOSFET晶片20、 第一金屬連接板51、翻轉的高端MOSFET晶片30和第二金 屬連接板52。 [0097] 其中，與上述實施例2-1中類似，本實施例中在該晶片基 座1 0 0頂面的第二凹槽1 〇 2内固定設置有該第二中間聯結 件62，其與該晶片基座1〇〇相分離且絕緣連接。該低端 MOSFET晶片20 ’翻轉安裝在該晶片基座1〇〇及該第二中 間聯結件62上’分別通過該導電的粘接膠91，將該低端 MOSFET晶片20的頂部源極22與該晶片基座1 〇〇頂面形成 電性連接’其頂部閘極21與該第二中間聯結件62的導電 上表面形成電性連接。The terminal MOSFET wafers have a bottom drain, a top source, and a top gate; wherein the gate G3 of the high side MOSFET (HS) and the gate G2 of the low side MOSFET (LS) are connected to the control chip; the high side MOSFET (HS) The drain D3 is connected to the power supply terminal Vin, the source 53 is connected to the low-end M2 of the low-end m〇sfet (LS), and the switch terminal LX is connected to the control chip' and the source S2 of the low-side MOSFET is The ground terminal Gnd is connected to form the power semiconductor element. [0062] Embodiment 1-1 [0〇63] 凊 cooperation shown in FIG. 2, FIG. 4, FIG. 6, is an implementation structure of the power semiconductor device of the present invention, wherein FIG. 4 is the power semiconductor device 100115173 Form No. A0101 Page 12 of 45 1003213894-0 201244052 [0064] [0067] [0067] A general structural diagram, and FIG. 6 is a cross-sectional view of the A-Α position of FIG. Corresponding to the circuit schematic shown in Fig. 2, the low-side MOSFET wafer 20 of the p-type high-side MOSFET wafer 30' N and the control wafer 40 are jointly packaged in the power semiconductor device. The power semiconductor device includes a lead frame on which a wafer base 100 is disposed, and a plurality of pins that are separated from the wafer base and electrically connected. The high-side and low-side MOSFET chips are respectively provided with a bottom drain, a top source and a top gate; correspondingly, the plurality of pins include a high-side source pin 72, a low-side gate pin 71, and a switch pin. 74 and a number of control pins 75. The wafer pedestal 100 is sized to at least correspond to the shape of the low-side MOSFET wafer 20 in the same plane as the control wafer 40. One end of the low-side gate pin 71 serves as the lead-out portion 712, and the other end serves as the in-line portion 711. Corresponding to the position of the inscribed portion 711, a matching notch 111 is formed on the side of the wafer base 100, so that the low-end gate pin 71 and the wafer base 1 are mutually formed. The corresponding arrangement of the separation 〇 after the low-side MOSFET wafer 20 is inverted, is fixedly attached to the wafer pedestal 100 by a conductive type of adhesive 91. The body of the low-end jt 〇 SFET wafer 20 covers the wafer pedestal 100. The top end of the top surface has its top source 22 electrically connected to the wafer base 100; and the top gate 21 thereof covers the inscribed portion 711 of the low-side gate pin 71 and passes through the conductive paste. The glue 91 is bonded to the low-end gate pin 71 to form an electrical connection. 100115173 Form No. A0101 Page 13 of 45 1003213894-0 201244052 [0069] The inscribed portion 711 of the low-side gate pin 71 is provided with a half-etched region 713 from the bottom surface of the low-side gate pin 71. It will be filled with a molding material at the time of packaging to increase the connection strength of the inscribed portion 711 and the low-end M〇SFET wafer 2A. On the side of the wafer base 1 corresponding to the inline portion 71A, a semi-etched region 104 is also disposed upward from the bottom surface of the wafer base 1 according to the width of the inscribed portion 711; j 〇 4 is also filled with a molding material during packaging to make the exposed bottom surface of the wafer pedestal 1 形状 simple. [0070] Since all of the above-mentioned pins including the lead-out portion 712 of the low-side gate pin 71, and the bottom portion of the wafer base 1 〇{) except the half-etched region 1〇4, will be as shown in FIG. The package is exposed to the outside of the bottom surface of the power semiconductor component after packaging. The top source 22 of the low-side MOSFET wafer 20 is connected to the ground through the bottom surface of the wafer substrate 1 to form the ground terminal Gnd in FIG. At the same time, most of the bottom surface of the wafer substrate 1 is exposed to the outside of the package to have a good heat dissipation effect. [00] The control wafer 40 is fixedly disposed at the other end of the top surface of the wafer substrate 1A. The top surface of the 3H control wafer 40 is provided with a plurality of electrodes, and the plurality of control wires 75 and the lead-out portion 712 of the low-side gate pin 71 are respectively electrically connected to the control wafer 40 through a plurality of wire bonds. connection. [0072] The first metal connecting plate 51 (or a metal connecting body such as a metal connecting tape) is fixedly attached to the low-end MOSFET wafer 20 by a conductive adhesive 91 to make the low-side MOSFET chip. The bottom turn 23 of the second turn is electrically connected to the bottom surface of the first metal connecting plate 51, and is further electrically connected to the switch pin 74 through the first metal connecting plate 51. 100115173 Form No. A0101 Page 14 of 45 1003213894 201244052 [0073] The MOSFET wafer 30 is fixedly attached to the first metal connecting plate 51 by a conductive adhesive 91 to make the bottom datum 33 and The top surface of the first metal connecting plate 51 is electrically connected, and is electrically connected to the bottom drain 23 of the low-side MOSFET wafer 20 and the switch pin 74 via the first metal connecting plate 51. The switch pin 74 is electrically connected to the electrode of the control chip 4 through the bonding wire 80 bonding to form a circuit connection as shown in Fig. 2 at the switch terminal Lx. [0074] The top gate 31 and the top source 32 of the high-side MOSFET wafer 30 are also electrically connected to the control wafer 40 by bonding wires 8 分别, respectively. The second metal connecting plate 52 ′ is fixedly attached to the high-end MOSFET 30 by the conductive adhesive 91 , so that the top source 32 of the high-side MOSFET 30 is electrically connected to the second connecting plate 52 . The second metal connecting plate 52 is further electrically connected to the high side source pin 72 to form the power receiving end Vi η in FIG. 2 . [0071] Embodiment 1 - 2 Please refer to FIG. 3, FIG. 5, FIG. 6, and FIG. 7. FIG. 5 is a schematic diagram of the overall structure of the power semiconductor device, and FIG. 6 is a diagram of FIG. A cross-sectional view of the Α position 'Fig. 7 is a cross-sectional view of the CC position in Fig. 5. Corresponding to the circuit schematic shown in Fig. 3, the control semiconductor wafer 40 and the high-side and low-side MOSFETs of the Ν type are jointly packaged in the power semiconductor device. The lead frame structure of the wafer pedestal 1 〇〇 and the plurality of pins spaced apart therefrom in this embodiment is the same as that in the above embodiment; the control wafer 40 and the low-end MOSFET electrode 20 are connected to each other on the wafer pedestal 100. The same applies to the above-described 100115173 form number Α0101 page 15/45 page 1003213894-0 [0078] 201244052 in the embodiment. The following is briefly described as follows: [_] As shown in FIG. 5, FIG. 6, and FIG. 8, the low-side MOSFET wafer 2 is flipped and bonded to the wafer pedestal 100, and the top source 22 and the wafer pedestal 100 are bonded. The top gate 21 is electrically connected to the inscribed portion 711 of the low-side gate pin 71. A first metal connection plate 51 is stacked on the low side MOSFET wafer 20 to form an electrical connection between the bottom electrode 23 of the low side M? SFET chip 2 and the switch pin 74. The control wafer 4 is also disposed on the wafer base 100, and the control wafer 40 and the plurality of control pins 75 and the lead-out portion 71 of the low-side gate pin 71 are realized by connecting wires 8 2、 An electrical connection between the pins 74, the wafer pedestal 100 00 corresponding to the inscribed portion 711 of the low-side gate pin 71, and semi-etched regions 1〇4 and 713 are respectively disposed from the bottom surface upward. The semi-etched regions 1〇4 and 713 are filled with a molding material at the time of packaging. All pins (including the lead-out portion 712 of the low-side gate pin 71), and the bottom portion of the wafer pedestal 100 except the half-corrosion region 丨〇4, are exposed to the bottom surface of the power semiconductor device after packaging. Outside. [〇〇8〇] Please refer to FIG. 3, FIG. 5, and FIG. 7. As shown in FIG. 3, FIG. 5 and FIG. 7, unlike the above embodiment, since the terminal MOSFET wafer 30 is an N-type MOSFET, it is stacked on the first after being flipped. On the metal connecting plate 51, the top source 32 of the high-end shame" wafer 30 and the first metal connecting plate 51 are fixed by an electrically conductive adhesive 91 and electrically connected. At this time, the high-end fairy is electrically connected to the bottom drain 23 of the low-side MOSFET wafer 20 via the top source 32 of the low-side MOSFET wafer 20, and further through the switch pin 7 4 . Electrically connected to the s-control wafer 40 to form the switch terminal Lx of FIG. 3. 100115173 Form No. A0101 Page 16 of 45 1003213894-0 201244052 [0081] The flip-mounted high-side MOSFET wafer 30, The top gate 31 is fixedly disposed on the first metal connecting plate 51 through a first intermediate connecting member 61, and the first intermediate connecting member 61 forms an electrical connection between the top gate 31 and the control wafer 40. Specifically, the top surface of the first metal connecting plate 51 defines a first recess 511, and the first recess 511 is matched in size to the first intermediate connecting member 61, and is mounted to be flipped. The top gate 31 of the high side MOSFET wafer 30 is positioned correspondingly. [0083] The first intermediate junction 61 is insulated from the underlying first metal connection plate 51, and the top of the high side MOSFET wafer 30 above it Electrical connection between gates 31 For example, the first intermediate joint member 61 may be a conductive metal sheet, the lower surface of which is attached to the first recess 511 by an insulating adhesive 92; or the first intermediate joint member 61 may be disposed. The surface is a conductive upper metal layer, and the lower surface is a lower layer of an insulator such as a glass layer. At this time, the bottom surface of the lower layer of the insulator may be fixedly connected to the first groove 511 by a conductive or non-conductive adhesive. C) 1 [0084] The upper surface of the first intermediate connecting member 61 and the top gate 31 of the high-side MOSFET wafer 30 are electrically connected by a conductive adhesive 91. The top gate 31 does not completely cover the first intermediate connecting member. The upper surface of the 61, the control wafer 40 and the first intermediate junction 61 are bonded by the connecting wire 80 to realize the electrical connection between the control wafer 40 and the top gate 31. [0085] The connecting plate 52 is fixedly attached to the high-end MOSFET wafer 30 by a conductive adhesive 91, so that the bottom of the high-side MOSFET wafer 30 is 100115173. Form No. A0101 Page 17/45 pages 1003213894-0 201244052 Bungee 33 and the Second metal connection 52 is electrically connected, and further electrically connected to the high-end drain pin 73 through the second metal connecting plate 52 to form the power input terminal ηn in FIG. 3. The control wafer 4 and the bottom drain 33 The electrical connection is also formed by the bonding wires 8〇. [0086] [0089] Embodiment 2 -1 β month matching is shown in FIG. 2, FIG. 9, and FIG. It is a schematic diagram of the overall structure of the power semiconductor π, and FIG. η is a cross-sectional view of the position of FIG. 9*Β_Β. Corresponding to the circuit schematic shown in Fig. 2, the high-side MOSFET chip 30 of the Ρ type, the low-side MOSFET chip 20 of the Ν type, and the control wafer 40 are jointly packaged in the power semiconductor device. Similar to the embodiment 1, in this embodiment, the control wafer is not disposed at the end of the wafer base of the lead frame, and the inverted low-end MOSFET wafer 20 and the first metal connecting plate are stacked on the other end. 51. A high side MOSFET wafer 30 and a second metal connection plate 52. Wherein, the first metal connecting plate 51 is electrically connected to the bottom drains 23 and 33 of the high-side and low-side M〇SFET chips at its top and bottom surfaces, respectively, and is connected to the switch pin 74, further in the switch The connecting wire 8 of the leg 74 is connected to the control wafer 40 to form an electrical connection with the control wafer 40 to form the switch terminal 1 of FIG. The second metal connection plate 52 is electrically connected to the top source 32 of the high side MOSFET chip 30 and is led out through the high side source pin 72 to form the power input terminal Vin of FIG. The control wafer 40 is also electrically connected to the top gate 31, the top source 32, and the plurality of control pins 75 of the top MOSFET wafer 30 through a plurality of connection wires 8 〇. Different from the structure in the above embodiment 1-1, in the present embodiment, the low-side MOSFET of the [0091] 009 [0092] is installed in the flip-flop 100115173 form number A0101 page 18/45 page 1003213894-0 201244052 [0090] The top gate 21 of the wafer 20 is correspondingly positioned, and a second recess 102 is formed on the top surface of the wafer base 100. A first intermediate coupling member 6 2 is matched with the second recess 102 and is correspondingly fixed in the second recess 102 and remains separated from the wafer base 100 and is insulated. Specifically, similar to the embodiment 1-2, the second intermediate connecting member 6 2 may be a conductive metal piece, and the lower surface thereof is attached to the second groove 1 〇 2 by an insulating bond 92; Alternatively, the second intermediate connecting member 6 2 may be provided with an upper layer of a conductive upper surface and a lower surface of a lower layer of an insulating layer such as a glass layer. At this time, the bottom surface of the lower layer of the insulating layer may pass through a conductive or non-conductive adhesive. The two grooves 102 are fixedly connected. The low-side MOSFET wafer 20 is flipped, and its top gate 21 is electrically connected to the conductive upper surface of the second intermediate link 62 via a conductive adhesive 91. The top gate 21 does not completely cover the second intermediate connecting member 62, so that the control wafer 40 and the upper surface of the second intermediate connecting member 62 are bonded by the connecting wire 80 to realize the control wafer 40 and the top gate. Electrical connection between poles 21. At the same time, the top source 22 of the low-side MOSFET wafer 20 is electrically connected to the top surface of the wafer pedestal 1 through the conductive knees 91, and is connected to the ground through the bottom surface of the wafer pedestal 100. The ground terminal Gnd in Fig. 2 is formed. Since the second intermediate connecting member 62 is disposed in the second recess 102 on the wafer base 100 in this embodiment, the lead portion 712' of the low-side gate pin η in the embodiment 1-1 can be implemented in the present embodiment. In the example, replace it with an additional control guide 100115173 Form No. A0101 Page 19 / Total 45 Page 1003213894-0 [0093] 201244052 Feet 75. Moreover, since it is not necessary to provide the semi-etched regions of the bottom surface of the wafer base and the low-side gate pins 71 in the embodiment i-丨, as shown in FIG. 13, the wafer base 100 in the present embodiment The bottom surface can be completely exposed outside the power semiconductor component after packaging, and the heat dissipation area is larger. [0094] Embodiment 2 - 2 [0095] Please refer to FIG. 3, FIG. 7, FIG. 10, FIG. 11 , wherein FIG. 1 is a schematic diagram of the overall structure of the power semiconductor device, and FIG. 7 is FIG. A cross-sectional view of the middle C position, and Fig. 11 is a cross-sectional view of the BB position in Fig. 1. Corresponding to the schematic of the circuit shown in Fig. 3, the control wafer 40 and the N-type high-side and low-side MOSFET wafers are jointly packaged in the power semiconductor device. [0096] In this embodiment, a control wafer 40 is disposed at the end of the wafer substrate 1 of the lead frame, and the inverted low-side MOSFET wafer 20, the first metal connection plate 51, and the inverted high-side MOSFET are stacked on the other end. Wafer 30 and second metal connection plate 52. [0097] wherein, in the second embodiment, the second intermediate connecting member 62 is fixedly disposed in the second recess 1 〇2 of the top surface of the wafer base 100 in the embodiment. It is separated from the wafer base 1 且 and is insulatively connected. The low-side MOSFET wafer 20' is flip-mounted on the wafer pedestal 1 〇〇 and the second intermediate junction 62 to pass through the conductive adhesive 91, respectively, and the top source 22 of the low-side MOSFET wafer 20 is The top surface of the wafer base 1 is electrically connected. The top gate 21 thereof is electrically connected to the conductive upper surface of the second intermediate joint 62.

[0098] 與實施例卜2中相類似，本實施例中，該第一金屬連接板 51堆疊在該低端MOSFET晶片20上，形成該低端MOSFET 100115173 表單編號A0101 第20頁/共45頁 1003213894-0 201244052 [0099][0098] Similar to the embodiment 2, in the embodiment, the first metal connection plate 51 is stacked on the low-end MOSFET wafer 20 to form the low-side MOSFET 100115173. Form No. A0101 Page 20 of 45 1003213894-0 201244052 [0099]

[0100] [0101] ο [0102] [0103] 晶片20的底部汲極23與該開關引腳74之間的電性連接。 該第一金屬連接板51頂面開設有該第一凹槽511 ;該第一 中間聯結件61絕緣固定在該第一凹槽511内。Ν型的該高 端MOSFET晶片30翻轉後，使其頂部閘極31與該第一中間 聯結件61的導電上表面電性連接。同時，該高端mosfeT 晶片30的頂部源極32與該第一金屬連接板51的頂面電性 連接’並進一步與該低端MOSFET晶片20的底部汲極23實 現電性連接’通過該第一金屬連接板51引至該開關引腳 74 ’形成圖3中的開關端Lx。 s亥南端MOSFET晶片30的底部汲極33，通過其上方的該第 二金屬連接板52與高端汲極引腳73實現電性連接，形成 圖3中的電源接入端Vin。 該控制晶片40 ’分別通過連接導線80鍵合，與該若干控 制引腳75、該第一和第二中間聯結件62的上表面、該開 關引腳74、該高端MOSFET晶片30的底部汲極33形成電性 連接。 如圖13所示，本實施例中晶片基座1〇〇的整個底面在封裝 後可完全暴露在該功率半導體元件外，形成低端MOSFET 晶片20的頂部源極22與地極的電性連接，即圖3中的接地 端Gnd。該外露的晶片基座1〇〇底面，能有效幫助散熱。 比較圖11、圖12所示，其中圖12是本發明實施例2-1、 2-2中所述功率半導體元件的另一種可行的實施結構，其 與上述結構的不同點在於，該晶片基座1〇〇上沒有設置固 疋連接該第二中間聯結件6 2的第二凹槽1 〇 2。該低端 100115173 表單編號A0101 第21頁/共45頁 1003213894-0 201244052 M0SFET晶片20翻轉安裝在該晶片基座1〇〇上時，該第二 中間聯結件62直接絕緣粘接在該晶片基座1〇〇上，第二中 間聯結件62的上表面與該頂部閘極21之間導電枯結並形 成電性連接。同時，該低端M0SFET晶片2〇的頂部源極22 ’通過-加厚的導電難_電性連接在該W基座ι〇〇 上；該加厚的導電枯接膠91厚度，與該晶片基座1〇〇上設 置第二中間聯結件62及其上下方的枯接膝後的厚度相匹 配0 [0104] 實施例3-1 剛請配合參見圖2、圖14、圖16所示，其中圖14是該功率半 導體元件的總體結構示意圖，圖16是圖14中人_人位置的剖 面圖。對應圖2所示的電路原理圖可見，該功率半導體元 件中將P型的南端M0SFET晶片30，N型的低端jjosFET晶 片20和控制晶片40進行了聯合封裝。 [0106]本實施例在該導線架的晶片基座1〇〇上依次向上堆疊了翻 轉的低端M0SFET晶片20、第一金屬連接板η、高端 M0SFET晶片30、第二金屬連接板52。該些晶片與連接板 的佈置位置及相互連接的結構，與上述實施例1_1、2_ι 中類似。現簡述如下： [01〇7]該第一金屬連接板51在其頂面和底面，分別與該高端和 低端M0SFET晶片的底部ί及極23和33電性連接，並進一步 連接至該開關引腳74 ’形成圖2中開關端^乂。第二金屬連 接板52在該南端M0SFET晶片30上，與其頂部源極32電性 連接’並進一步連接至高端源極引腳72，形成圖2中電源 100115173 表單編號Α0101 第22頁/共45頁 1003213894-0 201244052 [0108] [0109] Ο [0110] ο [0111] [0112] 輸入端Vi η。 與上述實婦彳中不同，本實施例中所述晶片基座1〇〇的頂 面半腐姓形成有—晶片凹槽103 ;該晶片凹槽103與該控 制晶片40相匹配，使該控制晶片4〇能夠對應固定在該晶 片凹槽103内’並在其周邊與該晶片基座100相分離且相 絕緣。 例如，控制晶片40高度為4 “m，因而向下半腐蝕4" m形 成晶片凹槽103，使設置在晶片凹槽1〇3内的該控制晶片 40其頂面症與該晶片基座1〇〇的頂面齊平。 該低端MOSFET晶片2 0翻轉後對應覆蓋在控制晶片4〇的一 部分頂面上，使其頂部閘極21和一部分頂部源極22，分 別通過導電的粘接膠91，直接與控制晶片4〇頂面上的其 中一些電極形成電性連接，減少了鍵合的連接導線8〇， 也簡化了封裝技術。同時，低端MOSFET晶片20的其餘頂 部源極22 ’另外設置導電的粘接膠91與晶片凹槽103以外 的該晶片基座100頂面形成電性連接，該晶片基座的 底面在封裝後可完全暴露在該功率半導體元件外（圖13 )，使低端MOSFET晶片20的該部分頂部源極22與地極連 接’形成圖2中的接地端Gnd。該外露的晶片基座1 〇〇底面 ，能有效幫助散熱。 該控制晶片40，還分別通過連接導線8〇鍵合，與該若干 控制引腳75、該開關引腳74、該高端MOSFET晶片30的頂 部閘極31和頂部源極32形成電性連接。 上述各實施例中都將控制晶片40與低端MOSFET晶片20在 100115173 表單編號A0101 第23頁/共45頁 1003213894-0 201244052 晶片基座1 ο 〇的同一平面佈置安裝，與之相比，實施例中 使低端MOSFΕΤ晶片20疊設在晶片凹槽1 〇3内的控制晶片 40上’形成立體的封裝結構。因而，在相同面積的晶片 基座100上’本實施例中低端MOSFET晶片20與控制晶片 40 ’可在不同的平面上，分別擴展其各自的晶片面積， 有效幫助功率半導體元件的性能提升。 [0113] 實施例3-2 [0114] 請配合參見圖3、圖7、圖15、圖16所示，其中圖15是該 功率半導體元件的總體結構示意圖，圖7是圖15tc_c位 置的剖面圖，圖16是圖15中D-D位置的剖面圖。對應圖3 所示的電路原理圖可見，該功率半導體元件中聯合封裝 了控制晶片40以及N型的高端和低端MOSFET晶片。 [0115] 與實施例3-1相類似，本實施例中’該低端jjosFET晶片 20，絕緣設置在該晶片基座1〇〇頂面半腐蝕形成的晶片凹 槽103内’並與該晶片基座1〇〇相分離。 [0116] 該低端MOSFET晶片20翻轉後對應覆蓋在控制晶片4〇的— 部分頂面上’使其頂部閘極21和一部分頂部源極2 2，分 別與控制晶片4 0頂面上的其中一些電極直接形成電性連 接。該立體的封裝結構，可在相同面積的晶片基座1〇〇上 ，分別擴展低端MOSFET晶片2 0與控制晶片40的面積，有 效幫助功率半導體元件的性能提升。 [0117] 同時，低端MOSFET晶片20的其餘頂部源極22，與晶片凹 槽103以外的該晶片基座1〇〇頂面形成電性連接；該晶片 基座10 0的底面在封裝後可完全暴露在該功率半導體元件 100115173 表單編號A0101 第24頁/共45頁 1〇〇3213894-〇 201244052 [0118] [0119]Ο [0120] Ο [0121] 外（圖13) ’使低端MOSFET晶片20的該部分頂部源極22 與地極連接，形成圖3中的接地端Gnd。該外露的晶片基 座100底面，能有效幫助散熱。 本實施例在翻轉的低端MOSFET晶片20上依次向上堆疊第 —金屬連接板51、翻轉的高端MOSFET晶片30、第二金屬 連接板52的結構，與實施例卜2、2-2中相類似。 其中，該第一金屬連接板51在該低端MOSFET晶片20上， 形成該低端MOSFET晶片20的底部汲極23與該開關引腳74 之間的電性連接。該第一金屬連接板51頂面上開設有該 第一凹槽511 ;並在其中絕緣設置有該第一中間聯結件61 〇 N型的該高端MOSFET晶片30翻轉後，使其頂部閘極31與 該第一中間聯結件61的導電上表面電性連接。同時，該 高端MOSFET晶片30的頂部源極32與該第一金屬連接板51 的頂面電性連接，並進一步與該低端MOSFET晶片20的底 部汲極23實現電性連接，通過該第一金屬連接板51引至 該開關引腳74，形成圖3中的開關端Lx。 該高端MOSFET晶片30的底部汲極33，通過其上方的該第 二金屬連接板52與高端汲極引腳73實現電性連接，形成 圖3中的電源接入端Vin。 [0122] 除了該低端MOSFET晶片20的頂部閘極21、頂部源極22是 直接與該控制晶片40電性連接的；該控制晶片40，還分 別通過連接導線80鍵合，實現與若干控制引腳75、該開 關引腳74、該第一中間聯結件61的上表面、該高端 100115173 表單編號A0101 第25頁/共45頁 1003213894-0 201244052 M0SFET晶片30的底部汲極33形成電性連接。 [0123] 比較圖16、圖π所示，其中圖17是本發明實施例31、 3-2中所述功率半導體元件的另一種可行的實施結構，其 與上述結構的不同點在於，該晶片基座1〇〇上沒有設置固 疋連接該控制晶片40的晶片凹槽1〇3。該控制晶片4〇直接 絕緣固定在該晶片基座1〇〇上；該低端M〇SFET晶片2〇翻 轉安裝時直接覆蓋在該控制晶片4〇頂面的一部分，使其 頂部閘極21和一部分頂部源極22，分別與控制晶片4〇頂 面的其中一些電極直接粘結並形成電性連接。同時，該 低端M0SFET晶片20的其餘頂部源極22，通過加厚的導電 粘接膠91電性連接在該晶片基座ι00上；該加厚的導電粘 接膠91厚度’與該晶片基座1〇〇上設置控制晶片4〇及其上 下方的粘接膠後的厚度相匹配。 [0124] 比較圖7、圖18所示，其中圖18是本發明實施例1-2、 2-2、3-2中所述功率半導體元件的另一種可行的實施結 構，其與上文所述結構的不同點在於，該第一金屬連接 板51的上表面沒有設置固定連接第一中間聯結件61的該 第一凹槽511。此時，該高端M0SFET晶片30翻轉安裝在 該第一金屬連接板51上時，該第一中間聯結件61直接絕 緣粘接在該第一金屬連接板51上，第一中間聯結件61的 上表面與該頂部閘極31導電粘結並形成電性連接。同時 ，該高端M0SFET晶片30的頂部源極32 ’通過一加厚的導 電粘接膠91電性連接在該第一金屬連接板51上；該加厚 的導電粘接膠91厚度，與該第一金屬連接板51上設置第 一中間聯結件61及其上下方的粘接膠後的厚度相匹配。 100115173 表單編號A0101 第26頁/共45頁 1003213894-0 201244052 [0125] [0126] Ο [0127][0102] [0103] The electrical connection between the bottom drain 23 of the wafer 20 and the switch pin 74. The first metal connecting plate 51 is provided with the first recess 511 on the top surface thereof; the first intermediate connecting member 61 is insulated and fixed in the first recess 511. After the flip-type of the high-side MOSFET wafer 30 is turned over, the top gate 31 is electrically connected to the conductive upper surface of the first intermediate link 61. At the same time, the top source 32 of the high-end mosfeT chip 30 is electrically connected to the top surface of the first metal connecting plate 51 and further electrically connected to the bottom drain 23 of the low-side MOSFET wafer 20 through the first The metal connection plate 51 leads to the switch pin 74' to form the switch terminal Lx in FIG. The bottom drain 33 of the south end MOSFET chip 30 is electrically connected to the high side drain pin 73 through the second metal connecting plate 52 above it to form the power supply terminal Vin in FIG. The control wafers 40' are respectively bonded by connecting wires 80, and the plurality of control pins 75, the upper surface of the first and second intermediate links 62, the switch pins 74, and the bottom bungee of the high-side MOSFET wafer 30. 33 forms an electrical connection. As shown in FIG. 13, in the embodiment, the entire bottom surface of the wafer pedestal 1 可 can be completely exposed outside the power semiconductor component after packaging, and the top source 22 of the low-side MOSFET wafer 20 is electrically connected to the ground. That is, the ground terminal Gnd in FIG. The exposed wafer base 1 has a bottom surface that can effectively help dissipate heat. 11 and FIG. 12, wherein FIG. 12 is another possible implementation structure of the power semiconductor device according to Embodiments 2-1 and 2-2 of the present invention, which is different from the above structure in that the wafer base The second recess 1 〇 2 of the second intermediate joint member 6 2 is not disposed on the seat 1 . The low end 100115173 Form No. A0101 Page 21 / Total 45 page 1003213894-0 201244052 When the M0SFET wafer 20 is flipped over the wafer base 1 , the second intermediate connecting member 62 is directly insulated and bonded to the wafer base 1 ,, the upper surface of the second intermediate connecting member 62 and the top gate 21 are electrically connected and formed an electrical connection. At the same time, the top source 22' of the low-side MOSFET wafer 2 is electrically connected to the W pedestal via a thickened conductive; the thickened conductive adhesive 91 has a thickness, and the wafer The thickness of the second intermediate joint 62 and the upper and lower knees of the base 1 are matched to each other. [0104] Embodiment 3-1 is just as shown in FIG. 2, FIG. 14 and FIG. 14 is a schematic view showing the overall structure of the power semiconductor device, and FIG. 16 is a cross-sectional view showing the position of the person in FIG. Corresponding to the circuit schematic shown in Fig. 2, the P-type south-end MOSFET wafer 30, the N-type low-side jjosFET wafer 20 and the control wafer 40 are jointly packaged in the power semiconductor device. In this embodiment, the flipped low-side MOSFET wafer 20, the first metal connection plate η, the high-side MOSFET wafer 30, and the second metal connection plate 52 are sequentially stacked upward on the wafer pedestal 1 of the lead frame. The arrangement positions and interconnection structures of the wafers and the connecting plates are similar to those in the above embodiments 1_1 and 2_ι. The following is briefly described as follows: [01〇7] The first metal connecting plate 51 is electrically connected to the bottom and bottom electrodes 23 and 33 of the high-end and low-side MOSFET wafers at its top and bottom surfaces, respectively, and is further connected to the Switch pin 74' forms the switch terminal of Figure 2. The second metal connection plate 52 is electrically connected to the top source 32 of the south end MOSFET wafer 30 and further connected to the high side source pin 72 to form the power supply 100115173 of FIG. 2 Form No. 1010101 Page 22 of 45 1003213894-0 201244052 [0109] 01 [0110] [0112] Input Vi η. Different from the above, in the embodiment, the top surface of the wafer base 1 is formed with a wafer recess 103; the wafer recess 103 is matched with the control wafer 40, so that the control is performed. The wafer 4 can be correspondingly fixed in the wafer recess 103 and is separated from and insulated from the wafer base 100 at its periphery. For example, the height of the control wafer 40 is 4"m, so that the lower half etching 4" m forms the wafer recess 103, so that the top surface of the control wafer 40 disposed in the wafer recess 1〇3 and the wafer base 1 The top surface of the crucible is flushed. The low-end MOSFET wafer 20 is overturned to cover a portion of the top surface of the control wafer 4, such that the top gate 21 and a portion of the top source 22 pass through the conductive adhesive. 91, directly electrically connected to some of the electrodes on the top surface of the control wafer 4, reducing the bonding of the bonding wires 8 〇, and simplifying the packaging technology. Meanwhile, the remaining top source 22 ' of the low-side MOSFET wafer 20 In addition, the conductive adhesive 91 is electrically connected to the top surface of the wafer base 100 other than the wafer recess 103. The bottom surface of the wafer base can be completely exposed outside the power semiconductor component after packaging (FIG. 13). The portion of the top source 22 of the low-side MOSFET wafer 20 is connected to the ground to form a ground terminal Gnd in FIG. 2. The exposed wafer substrate 1 has a bottom surface that can effectively help dissipate heat. The control wafer 40 is also separately By connecting the wire 8 〇 And electrically connecting the plurality of control pins 75, the switch pins 74, the top gate 31 and the top source 32 of the high side MOSFET wafer 30. The wafer 40 and the low side MOSFET are controlled in each of the above embodiments. 20 at 100115173 Form No. A0101, page 23/45 pages 1003213894-0 201244052 Wafer pedestal 1 ο 同一 The same planar arrangement is mounted, in contrast to the embodiment in which the low-end MOSF ΕΤ wafer 20 is stacked on the wafer recess 1 The control wafer 40 in the crucible 3 is formed on a three-dimensional package structure. Thus, on the wafer base 100 of the same area, the low-side MOSFET wafer 20 and the control wafer 40' can be expanded on different planes in this embodiment. The respective wafer area effectively contributes to the performance improvement of the power semiconductor component. [0113] Embodiment 3-2 [0114] Please refer to FIG. 3, FIG. 7, FIG. 15, FIG. 16, wherein FIG. 15 is the power semiconductor FIG. 7 is a cross-sectional view of the position of FIG. 15tc_c, and FIG. 16 is a cross-sectional view of the DD position of FIG. 15. Corresponding to the circuit schematic shown in FIG. 3, the power semiconductor component is jointly packaged with control. The chip 40 and the N-type high-end and low-side MOSFET chips. [0115] Similar to Embodiment 3-1, in the present embodiment, the low-end jjosFET wafer 20 is insulated from the top surface of the wafer substrate 1 The wafer recess 103 formed by etching is 'disconnected from the wafer substrate 1'. [0116] The low-side MOSFET wafer 20 is flipped over to cover the top surface of the control wafer 4' The pole 21 and a portion of the top source 22 are electrically connected directly to some of the electrodes on the top surface of the control wafer 40, respectively. The three-dimensional package structure can expand the area of the low-side MOSFET wafer 20 and the control wafer 40 on the wafer substrate 1 of the same area, and effectively improve the performance of the power semiconductor device. [0117] At the same time, the remaining top source 22 of the low-side MOSFET wafer 20 is electrically connected to the top surface of the wafer pedestal 1 other than the wafer recess 103; the bottom surface of the wafer pedestal 10 0 is Fully exposed to the power semiconductor component 100115173 Form No. A0101 Page 24/Total 45 Page 1〇〇3213894-〇201244052 [0118] [0119]Ο [0120] Ο [0121] Outside (Fig. 13) 'Make low-side MOSFET chips The top source 22 of this portion of 20 is connected to the ground to form the ground terminal Gnd in FIG. The exposed bottom surface of the wafer base 100 can effectively help to dissipate heat. In this embodiment, the structures of the first metal connecting plate 51, the inverted high-side MOSFET chip 30, and the second metal connecting plate 52 are sequentially stacked on the inverted low-end MOSFET wafer 20, which are similar to those in the embodiments 2 and 2-2. . The first metal connection plate 51 forms an electrical connection between the bottom drain 23 of the low-side MOSFET wafer 20 and the switch pin 74 on the low-side MOSFET wafer 20. The first recess 511 is opened on the top surface of the first metal connecting plate 51; and the top gate 31 is turned over after the high-side MOSFET wafer 30 in which the first intermediate connecting member 61 〇N is insulated is turned over. It is electrically connected to the conductive upper surface of the first intermediate connecting member 61. At the same time, the top source 32 of the high-side MOSFET chip 30 is electrically connected to the top surface of the first metal connecting plate 51, and further electrically connected to the bottom drain 23 of the low-side MOSFET wafer 20, through the first The metal connection plate 51 leads to the switch pin 74 to form the switch terminal Lx of FIG. The bottom drain 33 of the high-side MOSFET chip 30 is electrically connected to the high-side drain pin 73 through the second metal connecting plate 52 above it to form the power supply terminal Vin in FIG. [0122] The top gate 21 and the top source 22 of the low-side MOSFET wafer 20 are directly electrically connected to the control wafer 40. The control wafer 40 is also bonded by a connecting wire 80, and is controlled by several Pin 75, the switch pin 74, the upper surface of the first intermediate link 61, the high end 100115173 Form No. A0101 Page 25 / Total 45 page 1003213894-0 201244052 The bottom drain 33 of the M0SFET wafer 30 is electrically connected . [0123] Comparing FIG. 16 and FIG. π, FIG. 17 is another feasible implementation structure of the power semiconductor device according to Embodiments 31 and 3-2 of the present invention, which is different from the above structure in that the wafer The wafer recess 1 〇 3 to which the control wafer 40 is fixed is not disposed on the susceptor 1 . The control wafer 4 is directly insulated and fixed on the wafer base 1; the low-end M〇SFET wafer 2 is directly overlaid on a portion of the top surface of the control wafer 4 when the flip-chip is mounted, such that the top gate 21 and A portion of the top source 22 is directly bonded to and electrically connected to some of the electrodes of the top surface of the control wafer 4. At the same time, the remaining top source 22 of the low-side MOSFET wafer 20 is electrically connected to the wafer base ι00 by a thick conductive adhesive 91; the thick conductive adhesive 91 has a thickness 'and the wafer base The thickness of the control wafer 4〇 and the adhesive tape above and below it is matched on the holder. [0124] Comparing FIG. 7 and FIG. 18, wherein FIG. 18 is another feasible implementation structure of the power semiconductor device according to Embodiments 1-2, 2-2, and 3-2 of the present invention, which is the same as The structure is different in that the first surface of the first metal connecting plate 51 is not provided with the first groove 511 fixedly connected to the first intermediate connecting member 61. At this time, when the high-end MOSFET wafer 30 is flipped over the first metal connecting plate 51, the first intermediate connecting member 61 is directly insulatively bonded to the first metal connecting plate 51, and the first intermediate connecting member 61 is upper. The surface is electrically bonded to the top gate 31 and forms an electrical connection. At the same time, the top source 32' of the high-side MOSFET wafer 30 is electrically connected to the first metal connecting plate 51 through a thick conductive adhesive 91; the thickness of the thick conductive adhesive 91 is A metal connecting plate 51 is provided with a thickness matching the first intermediate connecting member 61 and the adhesive tape thereon. 100115173 Form No. A0101 Page 26 of 45 1003213894-0 201244052 [0125] [0126] Ο [0127]

[0128] 综上所述，本發明所述聯合封裝的功率半導體元件，在 晶片基座上依次向上堆疊設置了低端MOSFET晶片、第一 金屬連接板、南端MOSFET晶片和第二金屬連接板，實現 了該些半導體晶片在同一封裝體中的立體封裝，減小了 功率半導體元件的整體尺寸。 在上述一些較佳的實施例中，分別描述了在第一金屬連 接板的頂面上，和/或晶片基座的頂面上，分別開設有第 一、第二凹槽的結構’使第一、第二中間聯結件能夠絕 緣設置在對應凹槽内，分別將翻轉安裝的高端和低端 MOSFET晶片的頂部閘極引出，繼而通過連接引線鍵合實 現與其他晶片或元器件的電性連接。 在另一些較佳實施例中，還描述了在晶片基座的頂面開 設晶片凹槽的結構，其與上述第二凹槽的結構可同時或 分別設置。絕緣固定在該晶片凹槽内的控制晶片，與其 上方的低端MOSFET晶片的頂部源極、頂部閘極可直接對 應電性粘接，節省連接導線，也簡化了封裝技術。而且 ，該結構將控制晶片也進行了立體封裝，進一步減小了 功率半導體元件的整體厚度。 本發明所述翻轉安裝的低端M〇SFET晶片，其至少一部分 頂部源極，與晶片基座電性連接，並通過該晶片基座外 露的底面與地極連接的同時，有效進行散熱。 在-些實施例巾’還可以在該低端閘極引腳的内聯部分 ，以及晶片基座上與之對應的側邊，從底面向上分別設 置半腐㈣；該半腐邮在封裝時被塑封材料填充，增 100115173 表單編號A0101 第27頁/共45頁 1003213894-0 [0129] 201244052 加元件的連接強度同時，還能夠使該晶片基座的外露底 面結構簡單美觀。 [0130] 本發明上述使多個晶片堆疊設置，且使晶片基座底面外 露的面積最大的實施結構，可以方便地擴展至其他多個 半導體晶片、控制器等其他各種元器件的立體封裝，形 成各種半導體元件。相比現有半導體元件的封裝結構， 本發明在同樣大的導線架上可充分擴展各晶片的尺寸， 有效提高半導體元件的產品性能。 [0131] 儘管本發明的内容已經通過上述較佳實施例作了詳細介 紹，但應當認識到上述的描述不應被認為是對本發明的 限制。在本領域技術人員閱讀了上述内容後，對於本發 明的多種修改和替代都將是顯而易見的。因此，本發明 的保護範圍應由所附的申請專利範圍來限定。 【圖式簡單說明】 [0132] 圖1 係為現有功率半導體元件的封裝結構示意圖； 圖2 係為本發明中將N型和P型MOSFET晶片與控制晶片 封裝的電路原理框圖； 圖3 係為本發明中將N型和N型MOSFET晶片與控制晶片 封裝的電路原理框圖； 圖4 係為本發明所述功率半導體元件在實施例卜1中對 應圖2的總體結構示意圖； 圖5 係為本發明所述功率半導體元件在實施例1 -2中對 應圖3的總體結構不意圖； 圖6 係為圖4或圖5中A-A位置的剖面圖； 圖7 係為圖5或圖10或圖15中C-C位置的剖面圖； 100115173 表單編號A0101 第28頁/共45頁 1003213894-0 201244052 圖8 係為圖4或圖5所述功率半導體元件封裝後外露的引 腳示意圖； 圖9 係為本發明所述功率半導體元件在實施例2-1中對 應圖2的總體結構示意圖； 圖10 係為本發明所述功率半導體元件在實施例2-2中對 應圖3的總體結構示意圖； 圖11係為圖9或圖10中B-B位置的剖面圖； 圖12 係為對應實施例2-1、2-2的另一種功率半導體元 件的封裝結構在B’ -B’位置的剖面圖；In summary, the jointly packaged power semiconductor component of the present invention has a low-side MOSFET chip, a first metal connection plate, a south-end MOSFET chip, and a second metal connection plate stacked on the wafer substrate in sequence. The three-dimensional packaging of the semiconductor wafers in the same package is realized, and the overall size of the power semiconductor components is reduced. In some of the above preferred embodiments, the structure of the first and second recesses is respectively formed on the top surface of the first metal connecting plate and/or the top surface of the wafer base. 1. The second intermediate connecting member can be insulated and disposed in the corresponding groove, respectively extracting the top gates of the flip-mounted high-end and low-end MOSFET chips, and then electrically connecting with other wafers or components through connection wire bonding. . In still other preferred embodiments, a structure in which a groove of the wafer is formed on the top surface of the wafer base is described, and the structure of the second groove may be provided simultaneously or separately. The control wafer, which is insulated and fixed in the groove of the wafer, can directly electrically bond the top source and the top gate of the low-side MOSFET chip above it, saves the connection wires, and simplifies the packaging technology. Moreover, the structure also performs a three-dimensional encapsulation of the control wafer, further reducing the overall thickness of the power semiconductor device. The flip-mounted low-side M〇SFET chip of the present invention has at least a portion of the top source electrically connected to the wafer pedestal and is thermally coupled to the ground via the exposed bottom surface of the wafer pedestal. In some embodiments, the towel may also be provided with a semi-corrosion (four) from the bottom surface in the inline portion of the low-side gate pin and the corresponding side on the wafer base; Filled with plastic material, add 100115173 Form No. A0101 Page 27 / Total 45 Page 1003213894-0 [0129] 201244052 The connection strength of the component is also able to make the exposed bottom surface structure of the wafer base simple and beautiful. [0130] The above-described embodiment in which a plurality of wafers are stacked and the exposed area of the bottom surface of the wafer base is maximized can be easily extended to three-dimensional packages of other semiconductor chips, controllers, and the like. Various semiconductor components. Compared with the package structure of the conventional semiconductor device, the present invention can sufficiently expand the size of each wafer on the same large lead frame, and effectively improve the product performance of the semiconductor device. While the present invention has been described in detail by the foregoing preferred embodiments, it should be understood that Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0132] FIG. 1 is a schematic diagram of a package structure of a conventional power semiconductor device; FIG. 2 is a circuit block diagram of an N-type and P-type MOSFET wafer and a control chip package in the present invention; The circuit block diagram of the N-type and N-type MOSFET wafers and the control chip package in the present invention; FIG. 4 is a schematic diagram of the overall structure of the power semiconductor device according to the present invention corresponding to FIG. 2 in the embodiment 1; The power semiconductor device according to the present invention is not intended to correspond to the overall structure of FIG. 3 in Embodiment 1-2; FIG. 6 is a cross-sectional view taken at the AA position in FIG. 4 or FIG. 5; FIG. 7 is FIG. 5 or FIG. Figure 15 is a cross-sectional view of the CC position; 100115173 Form No. A0101 Page 28 of 45 1003213894-0 201244052 Figure 8 is a schematic diagram of the exposed pins of the power semiconductor component illustrated in Figure 4 or Figure 5; Figure 9 is The power semiconductor device of the present invention corresponds to the overall structure of FIG. 2 in the embodiment 2-1; FIG. 10 is a schematic diagram of the overall structure of the power semiconductor device according to the present invention corresponding to FIG. 3 in the embodiment 2-2; Is shown in Figure 9 or Figure 10. A cross-sectional view of the B-B position; Fig. 12 is a cross-sectional view of the package structure of another power semiconductor element corresponding to Embodiments 2-1 and 2-2 at the B'-B' position;

❹ [0133] 100115173 圖13 係為圖9或圖10或圖14或圖15所述功率半導體元 件封裝後外露的引腳示意圖； 圖14 係為本發明所述功率半導體元件在實施例3-1中對 應圖2的總體結構示意圖； 圖15係為本發明所述功率半導體元件在實施例3-2中對 應圖3的總體結構示意圖； 圖16係為圖14或圖15中D-D位置的剖面圖； 圖17 係為對應實施例3-1、3-2的另一種功率半導體元 件的封裝結構在D’ -D’位置的剖面圖；以及 圖18 係為對應實施例卜2、2-2、3-2的另一種功率半 導體元件的封裝結構在C’ -C’位置的剖面圖。 【主要元件符號說明】 HS(P型）：高端P型M0SFET晶片 HS(N型）：高端N型MOSFET晶片 LS(N型）：低端N型MOSFET晶片 G1 :高端P型MOSFET晶片的閘極 G2 :低端N型MOSFET晶片的閘極 表單編號A0101 第29頁/共45頁 1003213894-0 201244052 G3 :高端N型M0SFET晶片的閘極 51 :高端P型M0SFET晶片的源極 52 :低端N型M0SFET晶片的源極 53 :高端N型M0SFET晶片的源極 D1 :高端P型M0SFET晶片的汲極 D2 :低端N型M0SFET晶片的汲極 D3 :高端N型M0SFET晶片的汲極 Vin :電源接入端115 [0133] FIG. 13 is a schematic diagram of a lead exposed after the power semiconductor device of FIG. 9 or FIG. 10 or FIG. 14 or FIG. 15 is packaged; FIG. 14 is a power semiconductor device according to the present invention in Embodiment 3-1. FIG. 15 is a schematic view of the overall structure of the power semiconductor device of the present invention corresponding to FIG. 3 in the embodiment 3-2; FIG. 16 is a cross-sectional view of the DD position in FIG. 14 or FIG. Figure 17 is a cross-sectional view showing the package structure of another power semiconductor element corresponding to Embodiments 3-1 and 3-2 at a position D' - D'; and Figure 18 is a corresponding embodiment 2, 2-2. A cross-sectional view of the package structure of another power semiconductor component of 3-2 at the C'-C' position. [Main component symbol description] HS (P type): High-end P-type MOSFET wafer HS (N type): High-end N-type MOSFET chip LS (N type): Low-end N-type MOSFET chip G1: Gate of high-end P-type MOSFET chip G2: Gate Form No. A0101 of Low-End N-Type MOSFET Wafer Page 29/Total 45 Page 1003213894-0 201244052 G3: Gate 51 of High-End N-Type MOSFET Chip: Source 52 of High-Pattern P-Type MOSFET Chip: Low-End N Source 53 of the MOSFET type: source D1 of the high-end N-type MOSFET wafer: drain D2 of the high-end P-type MOSFET wafer: drain D3 of the low-side N-type MOSFET wafer: drain of the high-side N-type MOSFET wafer Vin: power supply Access side

Gnd :接地端 Lx :開關端 1C控制晶片：1C控制晶片 20 :低端M0SFET晶片 21 :低端M0SFET晶片頂部閘極 22 :低端M0SFET晶片頂部源極 23 :低端M0SFET晶片底部汲極 30 :高端M0SFET晶片 31 :高端M0SFET晶片頂部閘極 32 :高端M0SFET晶片頂部源極 33 :高端M0SFET晶片底部汲極 40 :控制晶片 51 :第一金屬連接板 511 :第一凹槽 52 :第二金屬連接板 61 :第一中間聯結件 62 :第二中間聯結件 71 :低端閘極引腳 100115173 表單編號A0101 第30頁/共45頁 1003213894-0 201244052 711 :内聯部分 712 :引出部分 713、104 :半腐蝕區 72 :高端源極引腳 73 :高端汲極引腳 74 :開關引腳 75 :控制引腳 80 :連接導線 91 :導電型的粘接膠Gnd: ground terminal Lx: switch terminal 1C control wafer: 1C control wafer 20: low-side MOSFET chip 21: low-side MOSFET wafer top gate 22: low-side MOSFET wafer top source 23: low-side MOSFET wafer bottom drain 30: High-end MOSFET chip 31: high-end MOSFET top gate 32: high-side MOSFET top source 33: high-side MOSFET wafer bottom drain 40: control wafer 51: first metal connection plate 511: first recess 52: second metal connection Plate 61: First intermediate link 62: Second intermediate link 71: Low-end gate pin 100115173 Form number A0101 Page 30/45 pages 1003213894-0 201244052 711: Inline portion 712: Lead-out portion 713, 104 : Semi-corrosion zone 72: High-side source pin 73: High-end drain pin 74: Switch pin 75: Control pin 80: Connecting wire 91: Conductive adhesive

92 :絕緣的粘接膠 100 :晶片基座 101 :缺口 102 :第二凹槽 103 :晶片凹槽 ❹ 100115173 表單編號A0101 第31頁/共45頁 1003213894-092: Insulating adhesive 100: Wafer base 101: Notch 102: Second groove 103: Wafer groove ❹ 100115173 Form No. A0101 Page 31 of 45 1003213894-0

Claims (1)

201244052 七、申請專利範圍： 1 . 一種聯合封裝的功率半導體元件，其中，包含：一高端 M0SFET晶片和一低端M0SFET晶片’係分別具有一底部汲 極、一頂部閘極和一頂部源極；一導線架，其設置有一晶 片基座，以及與該晶片基座分隔且無電性連接的若干引腳 ;該低端M0SFET晶片翻轉粘接在該晶片基座上，使其該 頂部源極與該晶片基座的頂面形成電性連接；該頂部源極 ，還通過與該晶片基座封裝後外露的底面電極電性連接， 並進行散熱；一第一金屬連接板，堆疊粘接在該低端 M0SFET晶片的該底部没極上；該高端M0SFET晶片直接堆 疊或翻轉後堆疊枯接在該第一金屬連接板上，使該高端 M0SFET晶片的該底部没極或者翻轉後的該頂部源極，通 過該第一金屬連接板與該低端M0SFET晶片的該底部漏極 形成電性連接；一第二金屬連接板，堆疊粘接並電性連接 在該高端M0SFET晶片的該頂部源極，或翻轉後的該底部 汲·極上，·一控制晶片’也設置在該晶片基座上，其設置的 若干電極，分別與該若干引腳之間，以及與該高端和低端 的M0SFET晶片的該電極之間，對應形成電性連接。 2 .如申請專利範圍第1項所述之的聯合封裝的功率半導體元 件，其中，該若干引腳包含一低端閘極引腳，其設置有一 引出部分及一内聯部分； 對應該内聯部分的位置，在該晶片基座上開設有一相匹配 的一缺口，使該低端閘極引腳在該缺口内，與該晶片基座 之間形成相互分離的對應設置； 翻轉設置的該低端M0SFET晶片，其該頂部閘極粘接在該 100115173 表單編號A0101 第32頁/共45頁 1003213894-0 201244052201244052 VII. Patent application scope: 1. A jointly packaged power semiconductor device, comprising: a high-end MOSFET chip and a low-side MOSFET wafer system having a bottom drain, a top gate and a top source, respectively; a lead frame provided with a wafer base and a plurality of pins separated from the wafer base and electrically connected; the low-side MOSFET wafer is flip-bonded to the wafer base such that the top source and the The top surface of the wafer base is electrically connected; the top source is electrically connected to the exposed bottom electrode after the wafer base is packaged, and heat is dissipated; a first metal connection plate is stacked and bonded at the low The bottom MOSFET of the terminal MOSFET wafer is directly stacked or flipped, and the stack is pasted on the first metal connection board, so that the bottom of the high-side MOSFET wafer is poleless or flipped after the top source passes through The first metal connection plate is electrically connected to the bottom drain of the low-end MOSFET chip; a second metal connection plate is stacked and electrically connected to the high-end MOSFE The top source of the T-wafer, or the inverted bottom electrode, a control wafer ′ is also disposed on the wafer pedestal, the plurality of electrodes disposed therebetween, and the plurality of pins, and An electrical connection is formed between the electrodes of the high-end and low-side MOSFETs. 2. The jointly packaged power semiconductor device of claim 1, wherein the plurality of pins comprise a low-side gate pin provided with a lead-out portion and an in-line portion; Part of the position, a matching gap is formed on the base of the wafer, so that the low-end gate pin is in the gap, and a corresponding setting is formed between the wafer base and the wafer base; End MOSFET wafer with the top gate bonded to the 100115173 Form No. A0101 Page 32 / Total 45 Page 1003213894-0 201244052 6 .6 . 内聯部分上，與該低端閘極引腳形成電性連接。 如申請專利範圍第2項所述之的聯合封裝的功率半導_ 件，其中，該低端閘極引腳的該内聯部分由底面η體元 置有-半脑區；該半腐敍區在封裝時被塑封材設 如申請專利制第3項所述之的聯合封|的功率半導體I 件’其中’在與該内聯部分相對應的該晶片基座側邊體70 底面向上也設置有-半腐贿；該半腐#區，其寬产與由 内聯部分的寬度相匹配，並在封裝時被塑封材料填充。、该 如申請專利範圍第2項所述之的聯合封裝的功率半導體元 件，其中，該控制晶片通過一連接導線鍵合，形成與嗲低 端閘極引腳的該引出部分的電性連接。 — 如申請專利範圍第1項所述之的聯合封裝的功率半導體元 件’其中，還包含-第二中間聯結件；翻轉安裝的該低端 M0SFET晶片，其該頂部閘極與該第二中間聯結件的導電 的上表面對應粘接並形成電性連接；該第二中間聯結件， 其下表面粘接在該晶片基座上，並與該晶片基座相絕緣。 如申請專利範圍第6項所述之的聯合封裝的功率半導體元 件’其中，s亥低端M0SFET晶片，其該頂部源極通過一加 厚的導電粘接膠’電性連接在該晶片基座上；該加厚的導 電粘接膠的厚度，與該晶片基座上設置該第二中間聯結件 及其上下方的钻接膠後的厚度相匹配。 8 .如申請專利範圍第6項所述之的聯合封裝的功率半導體元 件，其中’對應該低端M0SFET晶片的該頂部閘極位置， 在該晶片基座的頂面上形成有一第二凹槽；該第二中間聯 結件，對應粘接在相匹配的該第二凹槽内，並在其周邊與 該晶片基座分離且相絕緣。 100115173 表單編號Α0101 第33頁/共45頁 1003213894-0 201244052 9 ·如申請專利範圍第6項至第8項之任一項所述之的聯合封裝 的功率半導體元件，其中，該第二中間聯結件是一導電金 屬片，其下表面通過一絕緣的粘接膠，固定貼附在該晶片 基座上或該第二凹槽内。 10 如申請專利範圍第6項至第8項之任一項所述之的聯合封裝 的功率半導體元件，其中，該第二中間聯結件設置有一導 電的金屬上層和一絕緣體下層；該絕緣體下層的底面通過 一導電或不導電的粘接膠，固定貼附在該晶片基座上或該 第二凹槽内。 11 .如申請專利範圍第6項至第8項之任一項所述之的聯合封裝 的功率半導體元件，其中，該控制晶片與該第二中間聯結 件的上表面電性連接，以形成其與翻轉安裝的該低端 MOSFET晶片的該頂部閘極的電性連接。 12 .如申請專利範圍第丨項所述之的聯合封裝的功率半導體元 件，其中，該控制晶片，其底面絕緣粘接在該晶片基座上 ;翻轉安裝的該低端MOSFET晶片，覆蓋在該控制晶片頂 面的部分，該被覆蓋頂面上的其中一些電極，與該低端 MOSFET晶片的該頂部閘極和一部分該頂部源極直接枯接 ’形成電性連接。 13 . 14 . 100115173 如申請專利_第12項所社的聯合封裝的功率半導體元 件’其中’該低端MGSm晶片的其餘該頂部源極，通過 加厚的導電枯接膠，電性連接在該晶片基座上；該加厚 的導電枯接膠的厚度’與該晶片基座上設置該控制晶片及 其上下方的粘接膠後的厚度相匹配。 如申請專利範圍第12項所述之的聯合封裝的功率半導體元 件，其中，該晶片基座的頂面形成一晶片凹槽；該控制曰 表單編號細01 第34頁/共45頁 日日 1003213894-0 201244052 片對應粘接在相匹配的該晶片凹槽内，並在其周邊與該晶 片基座相分離且相絕緣。 15 .如申請專利範圍第1項所述之的聯合封裝的功率半導體元 件，其中，還包含一第一中間聯結件；翻轉安裝的該高端 M0SFET晶片，其該頂部閘極與該第一中間聯結件的導電 的上表面對應粘接並形成電性連接；該第一中間聯結件， 其下表面粘接在該第一金屬連接板上，並與該第一金屬連 接板相絕緣。 16 .如申請專利範圍第15項所述之的聯合封裝的功率半導體元 件，其中，該高端M0SFET晶片，其該頂部源極通過一加 厚的導電粘接膠，電性連接在該第一金屬連接板上； 該加厚的導電粘接膠的厚度，與該第一金屬連接板上設置 該第一中間聯結件及其上下方的粘接膠後的厚度相匹配。 17 .如申請專利範圍第15項所述之的聯合封裝的功率半導體元 件，其中，對應該高端M0SFET晶片的該頂部閘極位置， 在該第一金屬連接板的頂面上形成有一第一凹槽； 該第一中間聯結件，對應粘接在相匹配的該第一凹槽内， 並在其周邊與該第一金屬連接板分離且相絕緣。 18 .如申請專利範圍第15項至第17項之任一項所述之的聯合 封裝的功率半導體元件，其中，該第一中間聯結件是一導 電金屬片，其下表面通過一絕緣的粘接膠，固定貼附在該 第一金屬連接板上或該第一凹槽内。 19 .如申請專利範圍第15項至第17項之任一項所述之的聯合 封裝的功率半導體元件，其中，該第一中間聯結件設置有 一導電的金屬上層和一絕緣體下層；該絕緣體下層的底面 通過一導電或不導電的粘接膠，固定貼附在該第一金屬連 100115173 表單編號A0101 第35頁/共45頁 1003213894-0 201244052 接板上或該第一凹槽内。 20 .如申請專利範圍第15項至第17項之任一項所述之的聯合 封裝的功率半導體元件，其中，該控制晶片與該第一中間 聯結件的上表面電性連接，以形成其與翻轉安裝的該高端 M0SFET晶片的該頂部閘極的電性連接。 21 .如申請專利範圍第1項所述之的聯合封裝的功率半導體元 件，其中，該高端MOSFET晶片的該頂部源極及該頂部閘 極，或者翻轉安裝的該高端MOSFET晶片的該底部汲極， 分別與該控制晶片通過一連接導線鍵合形成電性連接。 22 .如申請專利範圍第1項所述之的聯合封裝的功率半導體元 件，其中，該若干引腳包含一開關引腳，其與該第一金屬 連接板電性連接；該控制晶片，與該開關引腳通過連接導 線鍵合，形成其與該第一金屬連接板的電性連接。 23 .如申請專利範圍第1項所述之的聯合封裝的功率半導體元 件，其中，該若干引腳包含一高端源極引腳；該高端 MOSFET晶片的該頂部源極，通過該第二金屬連接板，與 該高端源極引腳形成電性連接。 24 .如申請專利範圍第1項所述之的聯合封裝的功率半導體元 件，其中，該若干引腳包含一高端汲極引腳；翻轉安裝的 該高端MOSFET晶片的該底部汲極，通過該第二金屬連接 板與該高端汲極引腳形成電性連接。 100115173 表單編號A0101 第36頁/共45頁 1003213894-0The inline portion is electrically connected to the low-side gate pin. The jointly packaged power semiconductor device according to claim 2, wherein the inscribed portion of the low-side gate pin is provided with a half-brain region by a bottom η body element; The power semiconductor I piece of the joint sealing material is packaged at the time of encapsulation, and the bottom surface of the wafer base side body 70 corresponding to the inline portion is also There is a semi-corruption bribe; the semi-corrosion # zone has a wide yield that matches the width of the inline portion and is filled with the molding material during packaging. The co-packaged power semiconductor device of claim 2, wherein the control wafer is bonded by a connecting wire to form an electrical connection with the lead-out portion of the lower-side gate pin. - the jointly packaged power semiconductor component of claim 1, wherein the second intermediate junction is further included; the low side MOSFET wafer is flipped mounted, the top gate and the second intermediate junction The conductive upper surface of the member is bonded and electrically connected; the second intermediate connecting member has a lower surface bonded to the wafer base and insulated from the wafer base. The jointly packaged power semiconductor device of claim 6, wherein the top source of the MOSFET is electrically connected to the wafer pedestal via a thick conductive adhesive. The thickness of the thickened conductive adhesive matches the thickness of the wafer base on which the second intermediate joint member and the drilled rubber thereon are applied. 8. The jointly packaged power semiconductor component of claim 6, wherein the top gate position corresponding to the low side MOSFET wafer is formed with a second recess on the top surface of the wafer pedestal The second intermediate coupling member is correspondingly bonded in the matching second recess and is separated and insulated from the wafer base at its periphery. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The member is a conductive metal sheet, the lower surface of which is fixedly attached to the wafer base or the second recess by an insulating adhesive. The co-packaged power semiconductor component of any one of clauses 6 to 8, wherein the second intermediate junction is provided with a conductive metal upper layer and an insulator lower layer; the insulator lower layer The bottom surface is fixedly attached to the wafer base or the second recess by a conductive or non-conductive adhesive. The jointly packaged power semiconductor component of any one of claims 6 to 8, wherein the control wafer is electrically connected to an upper surface of the second intermediate junction to form An electrical connection to the top gate of the low side MOSFET chip mounted overturned. 12. The co-packaged power semiconductor component of claim 2, wherein the control wafer has a bottom surface that is insulatively bonded to the wafer pedestal; and the low-side MOSFET wafer is flipped over to cover the A portion of the top surface of the wafer is controlled, and some of the electrodes on the covered top surface are electrically connected to the top gate of the low side MOSFET wafer and a portion of the top source directly. 13 . 14 . 100115173 The jointly packaged power semiconductor component of the invention of claim 12, wherein the remaining top source of the low-end MGSm wafer is electrically connected by a thick conductive paste The thickness of the thickened conductive paste is matched to the thickness of the wafer base on which the control wafer and the adhesive thereon are applied. The jointly packaged power semiconductor device of claim 12, wherein the top surface of the wafer base forms a wafer groove; the control 曰 form number is fine 01 page 34 / 45 pages daily 1003213894 - 0 201244052 The sheet is bonded in the matching groove of the wafer and is separated from and insulated from the wafer base at its periphery. The co-packaged power semiconductor device of claim 1, further comprising a first intermediate junction; the high-end MOSFET wafer flip-mounted, the top gate being coupled to the first intermediate The electrically conductive upper surface of the piece is bonded and electrically connected; the first intermediate connecting member has a lower surface bonded to the first metal connecting plate and insulated from the first metal connecting plate. The co-packaged power semiconductor device of claim 15, wherein the high-side MOSFET wafer has the top source electrically connected to the first metal through a thick conductive adhesive. The thickness of the thick conductive adhesive is matched with the thickness of the first metal connecting plate after the first intermediate connecting member and the adhesive thereon. The co-packaged power semiconductor device of claim 15, wherein a top recess is formed on a top surface of the first metal connecting plate corresponding to the top gate position of the high-side MOSFET chip The first intermediate connecting member is correspondingly bonded in the matching first recess and is separated from and insulated from the first metal connecting plate at a periphery thereof. The jointly packaged power semiconductor component of any one of clauses 15 to 17, wherein the first intermediate joint member is a conductive metal sheet, the lower surface of which is passed through an insulating paste. The glue is fixedly attached to the first metal connecting plate or the first groove. The jointly packaged power semiconductor component of any one of clauses 15 to 17, wherein the first intermediate junction is provided with a conductive metal upper layer and an insulator lower layer; the insulator lower layer The bottom surface is fixedly attached to the first metal joint 100115173 Form No. A0101, page 35/45, 1003213894-0 201244052, or in the first recess by a conductive or non-conductive adhesive. The co-packaged power semiconductor component of any one of clauses 15 to 17, wherein the control wafer is electrically connected to an upper surface of the first intermediate junction to form Electrical connection to the top gate of the high-side MOSFET wafer mounted by flipping. The jointly packaged power semiconductor device of claim 1, wherein the top source and the top gate of the high side MOSFET chip, or the bottom buck of the high side MOSFET chip mounted overturned And electrically connecting the control wafer through a connecting wire to form an electrical connection. The jointly packaged power semiconductor component of claim 1, wherein the plurality of pins comprise a switch pin electrically connected to the first metal connection plate; the control chip, and the The switch pin is bonded by a connecting wire to form an electrical connection with the first metal connecting plate. The co-packaged power semiconductor device of claim 1, wherein the plurality of pins comprise a high side source pin; the top source of the high side MOSFET chip is connected through the second metal The board is electrically connected to the high side source pin. The co-packaged power semiconductor device of claim 1, wherein the plurality of pins comprise a high-side drain pin; and the bottom drain of the high-side MOSFET chip is flipped through the first The two metal connection plate is electrically connected to the high-end drain pin. 100115173 Form No. A0101 Page 36 of 45 1003213894-0
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US11335627B2 (en) 2017-02-20 2022-05-17 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
TWI773732B (en) * 2017-02-20 2022-08-11 新加坡商西拉娜亞洲私人有限公司 Electronic apparatus and method for packaging a semiconductor device

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US7265448B2 (en) * 2004-01-26 2007-09-04 Marvell World Trade Ltd. Interconnect structure for power transistors
JP2005302951A (en) * 2004-04-09 2005-10-27 Toshiba Corp Semiconductor device package for power
US7388280B2 (en) * 2005-02-22 2008-06-17 Stats Chippac Ltd. Package stacking lead frame system
US7800208B2 (en) * 2007-10-26 2010-09-21 Infineon Technologies Ag Device with a plurality of semiconductor chips
US8164199B2 (en) * 2009-07-31 2012-04-24 Alpha and Omega Semiconductor Incorporation Multi-die package

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Publication number Priority date Publication date Assignee Title
US11335627B2 (en) 2017-02-20 2022-05-17 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
TWI773732B (en) * 2017-02-20 2022-08-11 新加坡商西拉娜亞洲私人有限公司 Electronic apparatus and method for packaging a semiconductor device

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