TWI469311B - A combined packaged power semiconductor device - Google Patents

Description

Joint packaged power semiconductor components

The present invention relates to a power semiconductor device, and more particularly to a structure in which a plurality of components such as a wafer are collectively packaged in the same power semiconductor device.

At present, in a typical power semiconductor device, a MOSFET wafer (a metal oxide semiconductor field effect transistor) and a control wafer are usually packaged in the same package to reduce the number of peripheral components and improve the utilization efficiency of the power source and the like.

For a DMOSFET (Double-Diffused Metal Oxide Semiconductor Field Effect Transistor) wafer, if the source disposed on the upper surface of the wafer can be connected to the wafer substrate of the lead frame, the bottom surface of the wafer base can be exposed as Ground and heat dissipation.

The implementation of the above package structure requires that the wafer be flipped over and mounted on the wafer pedestal, which will face problems such as how to make the exposed wafer pedestal of the lead frame have as large and simple shape as possible, and make the wafer source The pole has the largest connection with the wafer base for better heat dissipation performance; how to make the electrical connection between the gate provided on the upper surface of the wafer and the control wafer reliable when flipping and mounting the wafer to the wafer base connection.

However, the prior art specific semiconductor device shown in FIG. 1 is provided corresponding to the circuit principle of FIG. 2, and includes a P-type high-side MOSFET (HS), an N-type low-side MOSFET (LS), and a control chip. The lead frame is mounted on the same plane. Then seal The mounting space of the package largely limits the size of the high-side MOSFET, low-side MOSFET, and control wafer, which has a large impact on the performance improvement of power semiconductor components.

Moreover, in the above-mentioned planar arrangement of the package structure, electrodes on the upper surface of the wafer such as a low-side MOSFET are directly connected to other wafers by wire bonding, or are connected to the pins by wires, and then connected to other wafers connected to the same pin. Or external components are connected. Therefore, such a package structure is difficult to flip the wafer, and the source of the upper surface is connected to the wafer base, so that the exposed wafer base can be obtained as a ground electrode and help heat dissipation.

It is an object of the present invention to provide a jointly packaged power semiconductor component capable of three-dimensionally packaging a plurality of semiconductor wafers in the same package to reduce the overall size of the semiconductor component and to increase the wafer size in the same size package. Dimensions to effectively improve the performance of semiconductor components. Further, the top source of the underlying wafer that is flipped can be connected to the wafer base, and the maximum area of the bottom surface of the wafer base is exposed and connected to the ground electrode to help dissipate heat.

In order to achieve the above object, the technical means of the present invention is to provide a jointly packaged power semiconductor device comprising: a high side MOSFET chip and a low side MOSFET chip having a bottom drain, a top gate and a top source, respectively; a lead frame, the setting thereof a wafer pedestal, and a plurality of pins separated from the wafer pedestal and electrically connected; the low-end MOSFET wafer is flip-bonded to the wafer pedestal to have its top source and the The top surface of the wafer base is electrically connected; the top source is electrically connected to the exposed bottom electrode after the wafer base is packaged, and the heat is dissipated; the first metal connecting plate is stacked and bonded at the low end. a bottom drain of the MOSFET chip; the high-side MOSFET wafer is directly stacked or flipped and then stacked and bonded on the first metal connection board, so that the bottom of the high-side MOSFET wafer is flipped or the top source is turned over, through the first metal connection The board is electrically connected to the bottom drain of the low-end MOSFET chip; the second metal connection board is stacked and electrically connected to the top source of the high-side MOSFET wafer, or the inverted bottom drain; the control chip It is also disposed on the wafer base, and a plurality of electrodes disposed therebetween are respectively electrically connected with the plurality of pins and between the electrodes of the high-side and low-side MOSFET wafers.

In a preferred embodiment, the plurality of pins comprise a low-side gate pin provided with a lead-out portion and an in-line portion; and corresponding to the position of the in-line portion, a matching gap is formed on the wafer base. Having the low-side gate pin in the gap, and forming a corresponding arrangement with the wafer base; and flipping the low-end MOSFET chip with the top gate bonded to the inscribed portion, and The low side gate pins form an electrical connection.

The inscribed portion of the low-side gate pin is provided with a half-etched region from the bottom surface; the semi-etched region is filled with a molding material during packaging.

On the side of the wafer base corresponding to the inline portion, half is also provided from the bottom surface Corrosion zone; the semi-etched zone has a width that matches the width of the inscribed portion and is filled with a molding material during packaging.

The control wafer is bonded by a connecting wire to form an electrical connection with the lead-out portion of the low-side gate pin.

In another preferred embodiment, the jointly packaged power semiconductor component further includes a second intermediate junction; the low-end MOSFET wafer flip-mounted, the top gate of which is corresponding to the conductive upper surface of the second intermediate junction And forming an electrical connection, the second intermediate connecting member has a lower surface adhered to the wafer base and insulated from the wafer base.

The low-side MOSFET chip has a top source electrically connected to the wafer base through a thick conductive adhesive; the thickness of the thick conductive adhesive is set to a second intermediate portion of the wafer base The thickness of the coupling member and the adhesive layer above and below it is matched.

In a modified structure of the embodiment, corresponding to the top gate position of the low-end MOSFET chip, a second recess is formed on the top surface of the wafer base; the second intermediate joint member is correspondingly bonded to match The second recess is separated from and insulated from the wafer base at its periphery.

The second intermediate joint member is a conductive metal sheet, and the lower surface thereof is fixedly attached to the wafer base or the second recess by an insulating adhesive.

Or the second intermediate connecting member is provided with a conductive upper metal layer and a lower insulating layer; The bottom surface of the lower layer of the insulator is fixedly attached to the wafer base or the second recess by a conductive or non-conductive adhesive.

The control wafer is electrically connected to the upper surface of the second intermediate link to form an electrical connection with the top gate of the flip-mounted low-side MOSFET.

In another preferred embodiment, the control wafer has a bottom surface that is insulatively bonded to the wafer base; the low-end MOSFET wafer that is flipped over covers a portion of the top surface of the control wafer; and the covered top surface Some of the electrodes are directly bonded to the top gate and a portion of the top source of the low-side MOSFET chip to form an electrical connection.

The remaining top source of the low-side MOSFET chip is electrically connected to the wafer base through a thick conductive adhesive; the thickness of the thick conductive adhesive is set on the wafer base The thickness of the adhesive after it is matched above and below.

In a modified structure of the embodiment, the top surface of the wafer base is formed with a wafer groove; the control wafer is correspondingly bonded in the matching groove of the wafer, and is separated from the wafer base at the periphery thereof Phase insulation.

In addition, the jointly packaged power semiconductor component further includes a first intermediate bonding member; the high-side MOSFET wafer is flip-mounted, and a top gate thereof is bonded to the conductive upper surface of the first intermediate bonding component and electrically connected The first intermediate connecting member has a lower surface adhered to the first metal connecting plate, and The first metal connecting plate is insulated.

The high-end MOSFET chip has a top source electrically connected to the first metal connecting plate through a thick conductive adhesive; the thickness of the thick conductive adhesive is set on the first metal connecting plate The thickness of the first intermediate joint member and its upper and lower adhesives are matched.

In a modified structure of the embodiment, corresponding to the top gate position of the high-side MOSFET chip, a first recess is formed on the top surface of the first metal connecting plate; the first intermediate connecting member is correspondingly bonded to the phase The matching first recess is separated from and insulated from the first metal connecting plate at its periphery.

The first intermediate connecting member is a conductive metal sheet, and the lower surface thereof is fixedly attached to the first metal connecting plate or the first recess by an insulating adhesive.

Or the first intermediate connecting member is provided with a conductive upper metal layer and a lower insulating layer; the bottom surface of the lower layer of the insulating layer is fixedly attached to the first metal connecting plate or the first groove by a conductive or non-conductive adhesive. Inside.

The control wafer is electrically connected to the upper surface of the first intermediate junction to form an electrical connection with the top gate of the flip-mounted high-side MOSFET.

The top source and the top gate of the high-side MOSFET chip, or the bottom drain of the high-side MOSFET chip that is flipped mounted, are respectively electrically connected to the control wafer through a connection wire bond.

The plurality of pins include a switch pin electrically connected to the first metal connecting plate; the control chip is bonded to the switch pin through a connecting wire to form an electrical connection with the first metal connecting plate.

The plurality of pins include a high-side source pin; a top source of the high-side MOSFET chip is electrically connected to the high-side source pin through the second metal connection plate.

The plurality of pins comprise a high-side drain pin; the bottom drain of the high-side MOSFET chip that is flipped mounted is electrically connected to the high-side drain pin through the second metal connection plate.

The joint packaged power semiconductor device of the present invention has the advantages that the present invention realizes that the low-side MOSFET chip, the first metal connection plate, the high-side MOSFET chip and the second metal connection plate are sequentially stacked on the wafer base. The three-dimensional packaging of the semiconductor wafers in the same package reduces the overall size of the power semiconductor components.

In some of the above preferred embodiments, the first and second recesses are respectively formed on the top surface of the first metal connecting plate and/or the top surface of the wafer base. 1. The second intermediate connecting member can be insulated and disposed in the corresponding groove, respectively extracting the top gates of the flip-mounted high-end and low-end MOSFET chips, and then electrically connecting with other wafers or components through connecting wire bonding. .

In still other preferred embodiments, a structure in which a groove of a wafer is formed on a top surface of the wafer base is described, and the structure of the second groove may be simultaneously or separately provided. The control wafer insulated and fixed in the groove of the wafer can directly correspond to the top source and the top gate of the low-side MOSFET chip above it, thereby saving the connection wire and simplifying the packaging technology. Moreover, the structure also performs a three-dimensional encapsulation of the control wafer, further reducing the overall thickness of the power semiconductor component.

The flip-mounted low-end MOSFET chip of the present invention has at least a part of the top source electrically connected to the wafer base and connected to the ground through the exposed bottom surface of the wafer base At the same time, it can effectively dissipate heat.

In some embodiments, a semi-etched region may also be disposed from the bottom surface to the inscribed portion of the low-side gate pin and the corresponding side of the wafer base; the semi-etched region is The filling of the molding material increases the connection strength of the component, and also enables the exposed bottom surface structure of the wafer base to be simple and beautiful.

According to the present invention, the embodiment in which a plurality of wafers are stacked and the exposed area of the bottom surface of the wafer base is as large as possible can be easily extended to three-dimensional packages of other semiconductor chips, controllers, and the like, and various types of components are formed. Semiconductor component. Compared with the package structure of the existing semiconductor element, the present invention can sufficiently expand the size of each wafer on the same large lead frame, and effectively improve the product performance of the semiconductor element.

HS (P type) ‧‧‧High-end P-type MOSFET chip

HS (N type) ‧‧‧ high-end N-type MOSFET chip

LS (N type) ‧‧‧ low-end N-type MOSFET chip

G1‧‧‧ Gate of high-end P-type MOSFET chip

Gate of G2‧‧‧ low-end N-type MOSFET

G3‧‧‧ Gate of high-end N-type MOSFET chip

Source of S1‧‧‧ high-end P-type MOSFET chip

Source of S2‧‧‧ low-end N-type MOSFET chip

Source of S3‧‧‧ high-end N-type MOSFET chip

D1‧‧‧Bungee of high-end P-type MOSFET

D2‧‧‧Bottom of low-end N-type MOSFET wafer

D3‧‧‧Bottom of high-end N-type MOSFET wafer

Vin‧‧‧Power access

Gnd‧‧‧ Grounding

Lx‧‧‧ switch end

IC control chip ‧‧‧IC control chip

20‧‧‧Low-end MOSFET chip

21‧‧‧ Low-end MOSFET chip top gate

22‧‧‧ low-end MOSFET chip top source

23‧‧‧ Low-end MOSFET wafer bottom bungee

30‧‧‧High-end MOSFET chip

31‧‧‧ High-end MOSFET chip top gate

32‧‧‧High-end MOSFET chip top source

33‧‧‧ High-end MOSFET wafer bottom bungee

40‧‧‧Control chip

51‧‧‧First metal connecting plate

511‧‧‧first groove

52‧‧‧Second metal connection plate

61‧‧‧First intermediate joint

62‧‧‧Second intermediate joint

71‧‧‧Low-end gate pin

711‧‧‧Inline part

712‧‧‧ lead-out

713, 104‧‧‧ semi-corrosive zone

72‧‧‧High-end source pin

73‧‧‧High-end bungee pin

74‧‧‧Switch pin

75‧‧‧Control pin

80‧‧‧Connecting wires

91‧‧‧Conductive adhesive

92‧‧‧Insulated adhesive

100‧‧‧ wafer base

101‧‧‧ gap

102‧‧‧second groove

103‧‧‧ wafer groove

1 is a schematic diagram of a package structure of a conventional power semiconductor device; FIG. 2 is a circuit block diagram of an N-type and P-type MOSFET wafer and a control chip package in the present invention; FIG. 3 is a N-type and a N-type in the present invention. FIG. 4 is a schematic diagram of the overall structure of the power semiconductor device of the present invention corresponding to FIG. 2 in the embodiment 1-1; FIG. 5 is a power semiconductor device according to the present invention. Figure 1-2 is a schematic view of the overall structure of Figure 3; Figure 6 is a cross-sectional view of the AA position of Figure 4 or Figure 5; Figure 7 is a cross-sectional view of the CC position of Figure 5 or Figure 10 or Figure 15; FIG. 8 is a schematic diagram of the exposed lead of the power semiconductor device of FIG. 4 or FIG. 5; FIG. 9 is a schematic diagram of the overall structure of the power semiconductor device according to the present invention in FIG. 2 in FIG. 2; FIG. FIG. 11 is a cross-sectional view of the power semiconductor device of the present invention corresponding to FIG. 3 in the embodiment 2-2; FIG. 11 is a cross-sectional view of the BB position in FIG. 9 or FIG. 10; FIG. 12 is a corresponding embodiment 2-1. 2-2 is a cross-sectional view of a package structure of another power semiconductor device at a position B'-B'; FIG. 13 is an exposed pin of the power semiconductor device package illustrated in FIG. 9 or FIG. 10 or FIG. 14 or FIG. Figure 14 is a schematic diagram of the overall structure of the power semiconductor device of the present invention corresponding to Figure 2 in the embodiment 3-1; Figure 15 is a power semiconductor device according to the present invention in the embodiment 3-2 corresponding to Figure 3 FIG. 16 is a cross-sectional view of the DD position in FIG. 14 or FIG. 15; FIG. 17 is a package structure of another power semiconductor device corresponding to Embodiments 3-1 and 3-2 at the D'-D' position. Sectional view; and Figure 18 is another work corresponding to Examples 1-2, 2-2, 3-2 Sectional view C'-C 'position of the package structure of the semiconductor element.

The preferred embodiments of the present invention will be described in detail below with reference to FIGS. 2 through 18 for a better understanding of the technical means and advantages of the present invention.

In the following embodiments, two MOSFET chips are connected as a high-side MOSFET chip and a low-side MOSFET chip to a control chip, and the three are collectively packaged in the same package to form an independent power semiconductor device. It should be noted, however, that the specific description and examples are not intended to limit the scope of the invention.

As shown in FIG. 2, the low-side MOSFET (LS) is an N-type MOSFET chip, and the high-side MOSFET (HS) is a P-type MOSFET chip. The high-side and low-side MOSFET chips each have a bottom drain, a top source, and a top gate; wherein the gate G1 of the high side MOSFET (HS) and the gate G2 of the low side MOSFET (LS) are connected to the control chip; The source S1 of the high-side MOSFET (HS) is connected to the power supply terminal Vin, and the drain D1 is connected to the drain D2 of the low-side MOSFET (LS), and is connected to the control chip as the switch terminal Lx; and the source of the low-side MOSFET S2 is connected to the ground terminal Gnd to form the power semiconductor element.

As shown in FIG. 3, the low-side MOSFET (LS) is an N-type MOSFET chip, and the high-side MOSFET (HS) is also an N-type MOSFET chip. The high-side and low-side MOSFET chips each have a bottom drain, a top source, and a top gate; wherein the gate G3 of the high side MOSFET (HS) and the gate G2 of the low side MOSFET (LS) are connected to the control chip; The drain D3 of the high-side MOSFET (HS) is connected to the power supply terminal Vin, and the source S3 is connected to the drain D2 of the low-side MOSFET (LS), and is connected to the control chip as the switch terminal Lx; and the source of the low-side MOSFET S2 is connected to the ground terminal Gnd to form the power semiconductor element.

Example 1-1

Referring to FIG. 2, FIG. 4, and FIG. 6, an implementation structure of the power semiconductor device of the present invention is shown in FIG. 4, which is a schematic structural view of the power semiconductor device, and FIG. 6 is a cross-sectional view of the AA position in FIG. Figure. Corresponding to the circuit schematic shown in FIG. 2, the P-type high-side MOSFET wafer 30, the N-type low-side MOSFET wafer 20 and the control wafer 40 are jointly packaged in the power semiconductor device.

The power semiconductor device includes a lead frame, and the lead frame is provided with a wafer base 100 and a plurality of pins separated from the wafer base 100 and electrically connected.

The high-side and low-side MOSFET chips are respectively provided with a bottom drain, a top source and a top gate; correspondingly, the plurality of pins include a high-side source pin 72, a low-side gate pin 71, and a switch pin. 74 and a number of control pins 75.

The wafer pedestal 100 is shaped to at least correspond to the shape of the low-side MOSFET wafer 20 and the control wafer 40 in the same plane.

One end of the low-side gate pin 71 serves as the lead-out portion 712, and the other end serves as the in-line portion 711. Corresponding to the position of the inscribed portion 711, a matching notch 101 (see FIG. 5) is formed on the side of the wafer base 100 to form a gap between the low-side gate pin 71 and the wafer base 100. Corresponding settings that are separated from each other.

After the low-side MOSFET wafer 20 is turned over, it is fixedly attached to the wafer pedestal 100 by a conductive adhesive 91. The main body of the low-end MOSFET wafer 20 covers the top surface of the wafer pedestal 100 to make the top thereof. The source 22 is electrically connected to the wafer base 100; at the same time, the top gate 21 thereof covers the inscribed portion 711 of the low-side gate pin 71, and passes through the conductive adhesive 91 and the low end. The gate pins 71 are bonded to form an electrical connection.

The inscribed portion 711 of the low-side gate pin 71 is formed by the bottom surface of the low-side gate pin 71 Above, a half etching region 713 is provided which is filled with a molding material at the time of packaging to increase the connection strength of the inscribed portion 711 and the low side MOSFET wafer 20. On the side of the wafer base 100 corresponding to the inscribed portion 711, a semi-etched region 104 is also disposed upward from the bottom surface of the wafer base 100 according to the width of the inscribed portion 711; the semi-etched region 104 is also packaged It is filled with a molding material to make the exposed bottom surface shape of the wafer susceptor 100 simple.

Since all of the above-mentioned pins including the lead-out portion 712 of the low-side gate pin 71 and the bottom portion of the wafer pedestal 100 other than the half-etched region 104 are exposed to the package as shown in FIG. Outside the bottom surface of the power semiconductor component. The top source 22 of the low-side MOSFET wafer 20 is connected to the ground through the bottom surface of the wafer pedestal 100 to form the ground terminal Gnd in FIG. At the same time, most of the bottom surface of the wafer pedestal 100 is exposed outside the package body, and has a good heat dissipation effect.

The control wafer 40 is fixedly disposed at the other end of the top surface of the wafer susceptor 100. The control chip 40 is provided with a plurality of electrodes on the top surface thereof, and the plurality of control pins 75 and the lead portions 712 of the low-side gate pins 71 are respectively electrically connected to the control wafer 40 through a plurality of wire bonds. .

The first metal connecting plate 51 (or a metal connecting body such as a metal connecting tape) is fixedly attached to the low-end MOSFET wafer 20 through a conductive adhesive 91 to make the bottom of the low-side MOSFET wafer 20 The drain 23 is electrically connected to the bottom surface of the first metal connecting plate 51, and is further electrically connected to the switch pin 74 through the first metal connecting plate 51.

The high-side MOSFET wafer 30 is fixedly attached to the first metal connecting plate 51 by a conductive adhesive 91, and has a bottom datum 33 and a top surface of the first metal connecting plate 51. The electrical connection is electrically connected to the bottom drain 23 of the low-side MOSFET wafer 20 and the switch pin 74 via the first metal connection plate 51. The switch pin 74 is electrically connected to the electrode of the control wafer 40 by a bonding wire 80 bonding to form a circuit connection of the switch terminal Lx of FIG.

The top gate 31 and the top source 32 of the high-side MOSFET wafer 30 are also electrically connected to the control wafer 40 by bonding wires 80.

The second metal connecting plate 52 is fixedly attached to the high-side MOSFET wafer 30 by a conductive adhesive 91, so that the top source 32 of the high-side MOSFET wafer 30 is electrically connected to the second metal connecting plate 52, and The second metal connecting plate 52 is further electrically connected to the high side source pin 72 to form the power receiving terminal Vin in FIG. 2 .

Example 1-2

Please refer to FIG. 3, FIG. 5, FIG. 6, and FIG. 7. FIG. 5 is a schematic view showing the overall structure of the power semiconductor device, FIG. 6 is a cross-sectional view taken along line AA of FIG. 5, and FIG. 7 is a CC position of FIG. Sectional view. Corresponding to the circuit schematic shown in FIG. 3, the control wafer 40 and the N-type high-side and low-side MOSFET chips are jointly packaged in the power semiconductor device.

In the embodiment, the wafer pedestal 100 and the lead frame structure of the plurality of pins separated therefrom are the same as those in the above embodiment; the structure of the control wafer 40 and the low-end MOSFET wafer 20 connected to the wafer pedestal 100 is as described above. The same is true in the examples. Referring to FIG. 5, FIG. 6 and FIG. 8 , the low-end MOSFET chip 20 is flipped and bonded to the wafer pedestal 100 , and the top source 22 is electrically connected to the wafer pedestal 100 . its The top gate 21 is electrically connected to the inscribed portion 711 of the low-side gate pin 71. A first metal connection plate 51 is stacked on the low side MOSFET wafer 20 to form an electrical connection between the bottom drain 23 of the low side MOSFET wafer 20 and the switch pin 74. The control wafer 40 is also disposed on the wafer pedestal 100. The control wafer 40 and the plurality of control pins 75, the lead-out portion 712 of the low-side gate pin 71, and the switch pin 74 are realized by bonding wires 80. Electrical connection between. The wafer pedestal 100 is disposed at a position corresponding to the inscribed portion 711 of the low-side gate pin 71, and semi-etched regions 104 and 713 are respectively disposed from the bottom surface upward, and the semi-corroded region 104 is filled with a molding material at the time of packaging. And 713. All of the leads (including the lead-out portion 712 of the low-side gate pin 71), and the bottom portion of the wafer pedestal 100 except the half-etched region 104, are exposed outside the bottom surface of the power semiconductor device after packaging.

Referring to FIG. 3, FIG. 5, and FIG. 7, the high-side MOSFET chip 30 is an N-type MOSFET which is stacked on the first metal connecting plate 51 after being turned over, as shown in FIG. 3, FIG. 5, and FIG. The top source 32 of the high-side MOSFET wafer 30 and the first metal connecting plate 51 are fixed by an electrically conductive adhesive 91 and electrically connected. At this time, the top source 32 of the high-side MOSFET wafer 30 and the bottom drain 23 of the low-side MOSFET wafer 20 are electrically connected via the first metal connecting plate 51, and further pass through the switch pin 74 and the control. The wafer 40 is electrically connected to form the switch terminal Lx of FIG.

The top gate 31 of the high-side MOSFET wafer 30 is flip-mounted, and the top gate 31 is fixedly disposed on the first metal connecting plate 51 through a first intermediate connecting member 61, and the top gate is formed by the first intermediate connecting member 61. 31 is electrically connected to the control wafer 40.

Specifically, the top surface of the first metal connecting plate 51 defines a first recess 511, and the first recess 511 is matched in shape to the first intermediate connecting member 61, and is turned over. The top gate 31 of the high-side MOSFET wafer 30 that is rotatably mounted corresponds to the position.

The first intermediate connecting member 61 is insulated from the underlying first metal connecting plate 51 and electrically connected to the top gate 31 of the high side MOSFET wafer 30 above it. For example, the first intermediate connecting member 61 may be a conductive metal sheet, the lower surface of which is attached by the insulating adhesive 92 in the first recess 511; or the first intermediate connecting member 61 may also be provided with the upper surface. The upper surface of the conductive metal layer is a lower layer of the insulator such as a glass layer. At this time, the bottom surface of the lower layer of the insulator can be fixedly connected to the first groove 511 through a conductive or non-conductive adhesive.

The upper surface of the first intermediate connecting member 61 and the top gate 31 of the high-side MOSFET wafer 30 are electrically connected by a conductive adhesive 91. The top gate 31 does not completely cover the upper surface of the first intermediate connecting member 61, so that the control wafer 40 and the first intermediate connecting member 61 are bonded by the connecting wire 80 to realize the control wafer 40 and the top gate. Electrical connection between 31.

The second metal connecting plate 52 is fixedly attached to the high-side MOSFET wafer 30 by a conductive adhesive 91, so that the bottom drain 33 of the high-side MOSFET wafer 30 is electrically connected to the second metal connecting plate 52, and The second metal connecting plate 52 is further electrically connected to the high-end drain pin 73 to form the power receiving terminal Vin in FIG. The control wafer 40 and the bottom drain 33 are also electrically connected by bonding wires 80 to form an electrical connection.

Example 2-1

Referring to FIG. 2, FIG. 9, and FIG. 11, FIG. 9 is a schematic view showing the overall structure of the power semiconductor device, and FIG. 11 is a cross-sectional view taken along line B-B of FIG. Corresponding to the circuit schematic shown in FIG. 2, a P-type high-side MOSFET is included in the power semiconductor device. Wafer 30, N-type low-side MOSFET wafer 20 and control wafer 40 are jointly packaged.

Similar to the embodiment 1-1, the embodiment is provided with a control wafer 40 at one end of the wafer pedestal 100 of the lead frame, and a flipped low-end MOSFET wafer 20, a first metal connecting plate 51, and the upper end are stacked upward. High side MOSFET wafer 30 and second metal connection plate 52. Wherein, the first metal connecting plate 51 is electrically connected to the bottom drains 23 and 33 of the high-end and low-side MOSFET wafers at its top and bottom surfaces, respectively, and is connected to the switch pin 74; further at the switch pin 74 The upper bonding connection wire 80 is electrically connected to the control wafer 40 to form the switch terminal Lx of FIG. The second metal connection plate 52 is electrically connected to the top source 32 of the high side MOSFET chip 30 and is led out through the high side source pin 72 to form the power input terminal Vin of FIG. The control wafer 40 is also bonded to the top gate 31, the top source 32, and the plurality of control pins 75 of the high-side MOSFET wafer 30 by a plurality of connection wires 80.

Different from the structure in the above embodiment 1-1, in this embodiment, corresponding to the position of the top gate 21 of the flip-chip mounted low-side MOSFET wafer 20, a second portion is formed on the top surface of the wafer pedestal 100. Groove 102. A second intermediate link 62 is mated with the second recess 102 and correspondingly secured within the second recess 102 and remains separate and insulated from the wafer base 100.

Specifically, similar to the embodiment 1-2, the second intermediate connecting member 62 may be a conductive metal piece, and the lower surface thereof is attached to the second groove 102 through an insulating adhesive 92; or the first The second intermediate connecting member 62 may also be provided with a conductive upper layer on the upper surface, and the lower surface is a lower layer of the insulator such as a glass layer. At this time, the bottom surface of the lower layer of the insulator may pass through the conductive or non-conductive adhesive and the second recess 102. Fixed connection.

The low-side MOSFET wafer 20 is flipped, and the top gate 21 is electrically connected to the conductive upper surface of the second intermediate link 62 via a conductive adhesive 91. The top gate 21 does not completely cover the second intermediate connecting member 62, so that the control wafer 40 and the upper surface of the second intermediate connecting member 62 are bonded by the connecting wire 80 to realize the control wafer 40 and the top gate. Electrical connection between poles 21.

At the same time, the top source 22 of the low-side MOSFET chip 20 is electrically connected to the top surface of the wafer pedestal 100 through the conductive adhesive 91, and is connected to the ground through the bottom surface of the wafer pedestal 100. Ground terminal Gnd in Figure 2.

Since the second intermediate connecting member 62 is disposed in the second recess 102 on the wafer base 100 in this embodiment, the lead portion 712 of the low-side gate pin 71 in Embodiment 1-1 can be implemented in the present embodiment. In the example, an additional control pin 75 is replaced. Moreover, since it is not necessary to provide the semi-etched region in the bottom surface of the wafer pedestal 100 and the low-side gate pin 71 in Embodiment 1-1, as shown in FIG. 13, the bottom surface of the wafer susceptor 100 in this embodiment is After packaging, it can be completely exposed outside the power semiconductor component, and the heat dissipation area is larger.

Example 2-2

Referring to FIG. 3, FIG. 7, FIG. 10, FIG. 11, FIG. 10 is a schematic view showing the overall structure of the power semiconductor device, FIG. 7 is a cross-sectional view of the CC position in FIG. 10, and FIG. 11 is a BB position in FIG. Sectional view. Corresponding to the circuit schematic shown in FIG. 3, the control wafer 40 and the N-type high-side and low-side MOSFET chips are jointly packaged in the power semiconductor device.

In this embodiment, a control wafer 40 is disposed at one end of the wafer pedestal 100 of the lead frame, and a flipped low-side MOSFET wafer 20, a first metal connection plate 51, a flipped high-side MOSFET wafer 30, and a second metal are stacked on the other end. Connecting plate 52.

The second intermediate connecting member 62 is fixedly disposed in the second recess 102 on the top surface of the wafer base 100 in the embodiment, which is similar to the wafer base 100. Separate and insulated connections. The low-side MOSFET chip 20 is flip-mounted on the wafer pedestal 100 and the second intermediate junction 62, and the top source 22 of the low-side MOSFET wafer 20 and the wafer are respectively passed through the conductive adhesive 91. The top surface of the susceptor 100 is electrically connected, and the top gate 21 is electrically connected to the conductive upper surface of the second intermediate connecting member 62.

Similar to the embodiment 1-2, in the embodiment, the first metal connection plate 51 is stacked on the low-end MOSFET wafer 20 to form the bottom drain 23 of the low-side MOSFET wafer 20 and the switch pin 74. Electrical connection between.

The first metal connecting plate 51 defines the first recess 511 on the top surface of the first metal connecting plate 51. The first intermediate connecting member 61 is insulated and fixed in the first recess 511. After the N-type high-side MOSFET wafer 30 is turned over, its top gate 31 is electrically connected to the conductive upper surface of the first intermediate link 61. At the same time, the top source 32 of the high-side MOSFET chip 30 is electrically connected to the top surface of the first metal connection board 51, and further electrically connected to the bottom drain 23 of the low-side MOSFET wafer 20, through the first The metal connection plate 51 leads to the switch pin 74 to form the switch terminal Lx of FIG.

The bottom drain 33 of the high-side MOSFET wafer 30 is electrically connected to the high-side drain pin 73 through the second metal connecting plate 52 above it to form the power supply terminal Vin in FIG.

The control wafer 40 is bonded by a connecting wire 80, and the plurality of control pins 75, the upper surface of the first and second intermediate connecting members 62, the switch pin 74, and the bottom bungee of the high-side MOSFET wafer 30. 33 forms an electrical connection.

As shown in FIG. 13, in the embodiment, the entire bottom surface of the wafer pedestal 100 can be completely exposed outside the power semiconductor component after packaging, and the top source 22 of the low-side MOSFET wafer 20 is electrically connected to the ground. Ground terminal Gnd in Figure 3. The exposed bottom surface of the wafer base 100 can effectively help to dissipate heat.

11 and FIG. 12, wherein FIG. 12 is another possible implementation structure of the power semiconductor device according to Embodiments 2-1 and 2-2 of the present invention, which is different from the above structure in that the wafer base The second recess 102 fixedly connected to the second intermediate link 62 is not provided on the seat 100. When the low-side MOSFET wafer 20 is flip-mounted on the wafer pedestal 100, the second intermediate connecting member 62 is directly insulatively bonded to the wafer pedestal 100, and the upper surface of the second intermediate connecting member 62 and the top gate 21 is electrically conductively bonded and forms an electrical connection. At the same time, the top source 22 of the low-side MOSFET wafer 20 is electrically connected to the wafer base 100 through a thick conductive adhesive 91; the thickness of the thick conductive adhesive 91 is compared with the wafer base. The thickness of the second intermediate joint member 62 and the adhesive tape thereon is matched on the seat 100.

Example 3-1

Referring to FIG. 2, FIG. 14, and FIG. 16, FIG. 14 is a schematic overall structural view of the power semiconductor device, and FIG. 16 is a cross-sectional view taken along line A-A of FIG. Corresponding to the circuit schematic shown in FIG. 2, the P-type high-side MOSFET wafer 30, the N-type low-side MOSFET wafer 20 and the control wafer 40 are jointly packaged in the power semiconductor device.

In this embodiment, the inverted low-end MOSFET wafer 20, the first metal connection plate 51, the high-side MOSFET wafer 30, and the second metal connection plate 52 are sequentially stacked on the wafer base 100 of the lead frame. Arrangement position and interconnection structure of the wafers and the connection plates Similar to the above embodiments 1-1 and 2-1. The first metal connecting plate 51 is electrically connected to the bottom and bottom electrodes 23 and 33 of the high-end and low-side MOSFET chips respectively on the top and bottom surfaces thereof, and is further connected to the switch pin 74 to form a first metal connecting plate 51. Figure 2 is the switch terminal Lx. The second metal connection plate 52 is electrically connected to the top source 32 of the high side MOSFET chip 30 and further connected to the high side source pin 72 to form the power input terminal Vin of FIG.

Different from the above embodiment, in the embodiment, the top surface of the wafer pedestal 100 is semi-etched to form a wafer recess 103; the wafer recess 103 is matched with the control wafer 40, so that the control wafer 40 can be correspondingly fixed. The wafer recess 103 is separated from and insulated from the wafer base 100 at its periphery.

For example, the height of the control wafer 40 is 4 μm, so that the wafer recess 103 is formed by etching 4 μm downward, so that the top surface of the control wafer 40 disposed in the wafer recess 103 can be flush with the top surface of the wafer base 100. .

The low-side MOSFET wafer 20 is overturned to cover a portion of the top surface of the control wafer 40 such that the top gate 21 and a portion of the top source 22 are directly connected to the top surface of the control wafer 40 through the conductive adhesive 91. Some of the electrodes form an electrical connection that reduces the bonded connecting wires 80 and simplifies the packaging technique. At the same time, the remaining top source 22 of the low-side MOSFET wafer 20 is additionally provided with a conductive adhesive 91 electrically connected to the top surface of the wafer base 100 other than the wafer recess 103. The bottom surface of the wafer base 100 is packaged. Thereafter, it can be completely exposed outside the power semiconductor component (FIG. 13), and the portion of the top source 22 of the low-side MOSFET wafer 20 is connected to the ground to form the ground terminal Gnd of FIG. The exposed bottom surface of the wafer base 100 can effectively help to dissipate heat.

The control wafer 40 is also electrically connected to the plurality of control pins 75, the switch pins 74, the top gate 31 and the top source 32 of the high side MOSFET wafer 30 by bonding wires 80, respectively.

In each of the above embodiments, the control wafer 40 and the low-side MOSFET wafer 20 are arranged in the same plane of the wafer pedestal 100. In contrast, in the embodiment, the low-side MOSFET wafer 20 is stacked in the wafer recess 103. On the control wafer 40, a three-dimensional package structure is formed. Therefore, on the wafer base 100 of the same area, the low-side MOSFET wafer 20 and the control wafer 40 in this embodiment can respectively expand their respective wafer areas on different planes, thereby effectively improving the performance of the power semiconductor element.

Example 3-2

Referring to FIG. 3, FIG. 7, FIG. 15, and FIG. 16, FIG. 15 is a schematic structural view of the power semiconductor device, FIG. 7 is a cross-sectional view of the CC position in FIG. 15, and FIG. 16 is a DD position in FIG. Sectional view. Corresponding to the circuit schematic shown in FIG. 3, the control wafer 40 and the N-type high-side and low-side MOSFET chips are jointly packaged in the power semiconductor device.

Similar to the embodiment 3-1, in the embodiment, the low-end MOSFET wafer 20 is insulated and disposed in the wafer recess 103 formed by the top surface of the wafer pedestal 100 and is separated from the wafer pedestal 100. .

The low-side MOSFET wafer 20 is overturned to cover a portion of the top surface of the control wafer 40 such that the top gate 21 and a portion of the top source 22 are electrically connected to some of the electrodes on the top surface of the control wafer 40, respectively. . The three-dimensional package structure can expand the area of the low-end MOSFET wafer 20 and the control wafer 40 on the wafer base 100 of the same area, thereby effectively improving the performance of the power semiconductor component.

At the same time, the remaining top source 22 of the low-side MOSFET wafer 20 is electrically connected to the top surface of the wafer pedestal 100 other than the wafer recess 103; the bottom surface of the wafer pedestal 100 can be completely exposed to the power semiconductor after packaging. Outside the component (Fig. 13), the portion of the top source 22 of the low side MOSFET wafer 20 is connected to the ground to form the ground terminal Gnd of FIG. The exposed bottom surface of the wafer base 100 can effectively help to dissipate heat.

In this embodiment, the structures of the first metal connecting plate 51, the inverted high-side MOSFET chip 30, and the second metal connecting plate 52 are sequentially stacked on the inverted low-end MOSFET wafer 20, and the embodiments are in the same manner as in the embodiments 1-2 and 2-2. similar.

The first metal connection plate 51 forms an electrical connection between the bottom drain 23 of the low-side MOSFET wafer 20 and the switch pin 74 on the low-side MOSFET wafer 20. The first groove 511 is opened on the top surface of the first metal connecting plate 51; and the first intermediate connecting member 61 is insulated therein.

After the N-type high-side MOSFET wafer 30 is turned over, its top gate 31 is electrically connected to the conductive upper surface of the first intermediate link 61. At the same time, the top source 32 of the high-side MOSFET chip 30 is electrically connected to the top surface of the first metal connection board 51, and further electrically connected to the bottom drain 23 of the low-side MOSFET wafer 20, through the first The metal connection plate 51 leads to the switch pin 74 to form the switch terminal Lx of FIG.

The bottom drain 33 of the high-side MOSFET wafer 30 is electrically connected to the high-side drain pin 73 through the second metal connecting plate 52 above it to form the power supply terminal Vin in FIG.

The top gate 21 and the top source 22 of the low-side MOSFET wafer 20 are directly electrically connected to the control wafer 40. The control wafer 40 is also bonded to the plurality of control pins 75 by connecting wires 80, respectively. The switch pin 74, the first intermediate junction The upper surface of the member 61 and the bottom drain 33 of the high side MOSFET wafer 30 are electrically connected.

16 and FIG. 17, wherein FIG. 17 is another possible implementation structure of the power semiconductor device according to Embodiments 3-1 and 3-2 of the present invention, which is different from the above structure in that the wafer base The wafer recess 103 to which the control wafer 40 is fixed is not disposed on the holder 100. The control wafer 40 is directly insulated and fixed on the wafer base 100; the low-end MOSFET wafer 20 is directly overlaid on a portion of the top surface of the control wafer 40 when flipped over, such that the top gate 21 and a portion of the top source 22 are respectively Some of the electrodes on the top surface of the control wafer 40 are bonded directly and form an electrical connection. At the same time, the remaining top source 22 of the low-side MOSFET wafer 20 is electrically connected to the wafer pedestal 100 through a thick conductive adhesive 91; the thickness of the thick conductive adhesive 91 is compared with the wafer base. The thickness of the control wafer 40 and the adhesive tape above and below it is set on the holder 100 to match.

7 and FIG. 18, wherein FIG. 18 is another possible implementation structure of the power semiconductor device according to Embodiments 1-2, 2-2, and 3-2 of the present invention, which is the same as the structure described above. The difference is that the first surface of the first metal connecting plate 51 is not provided with the first groove 511 fixedly connected to the first intermediate connecting member 61. At this time, when the high-side MOSFET wafer 30 is flipped over the first metal connecting plate 51, the first intermediate connecting member 61 is directly insulatively bonded to the first metal connecting plate 51, and the first intermediate connecting member 61 is upper. The surface is electrically bonded to the top gate 31 and forms an electrical connection. At the same time, the top source 32 of the high-side MOSFET wafer 30 is electrically connected to the first metal connecting plate 51 through a thick conductive adhesive 91; the thickness of the thick conductive adhesive 91 is The thickness of the first intermediate connecting member 61 on the metal connecting plate 51 and the adhesive tape on the upper and lower sides thereof are matched.

In summary, the jointly packaged power semiconductor component of the present invention has a low-side MOSFET chip, a first metal connection plate, a high-side MOSFET chip, and a second metal connection plate stacked on the wafer substrate in sequence, thereby realizing the The three-dimensional packaging of the semiconductor wafers in the same package reduces the overall size of the power semiconductor components.

In some of the above preferred embodiments, the first and second recesses are respectively formed on the top surface of the first metal connecting plate and/or the top surface of the wafer base. 1. The second intermediate connecting member can be insulated and disposed in the corresponding groove, respectively extracting the top gates of the flip-mounted high-end and low-end MOSFET chips, and then electrically connecting with other wafers or components through connection wire bonding. .

In still other preferred embodiments, a structure in which a groove of a wafer is formed on a top surface of the wafer base is described, and the structure of the second groove may be simultaneously or separately provided. The control wafer insulated and fixed in the groove of the wafer can directly correspond to the top source and the top gate of the low-side MOSFET chip above it, thereby saving the connection wire and simplifying the packaging technology. Moreover, the structure also performs a three-dimensional encapsulation of the control wafer, further reducing the overall thickness of the power semiconductor component.

The flip-mounted low-end MOSFET chip of the present invention has at least a part of the top source electrically connected to the wafer base, and is effectively cooled by connecting the exposed bottom surface of the wafer base to the ground.

In some embodiments, a semi-etched region may also be disposed from the bottom surface to the inscribed portion of the low-side gate pin and the corresponding side of the wafer base; the semi-etched region is The filling of the molding material increases the connection strength of the component, and also enables the exposed bottom surface structure of the wafer base to be simple and beautiful.

The above-mentioned area for stacking a plurality of wafers and exposing the bottom surface of the wafer base of the present invention The largest implementation structure can be easily extended to three-dimensional packages of other semiconductor chips, controllers, and the like to form various semiconductor components. Compared with the package structure of the existing semiconductor element, the present invention can sufficiently expand the size of each wafer on the same large lead frame, and effectively improve the product performance of the semiconductor element.

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

20‧‧‧Low-end MOSFET chip

30‧‧‧High-end MOSFET chip

33‧‧‧ High-end MOSFET wafer bottom bungee

40‧‧‧Control chip

51‧‧‧First metal connecting plate

511‧‧‧first groove

52‧‧‧Second metal connection plate

61‧‧‧First intermediate joint

71‧‧‧Low-end gate pin

713, 104‧‧‧ semi-corrosive zone

73‧‧‧High-end bungee pin

74‧‧‧Switch pin

75‧‧‧Control pin

80‧‧‧Connecting wires

100‧‧‧ wafer base

101‧‧‧ gap

Claims (23)

A jointly packaged power semiconductor device, comprising: a high side MOSFET chip and a low side MOSFET chip, each having a bottom drain, a top gate and a top source; a lead frame provided with a wafer base And a plurality of pins separated from the wafer base and electrically connected; the low-end MOSFET chip is flip-bonded on the wafer base such that the top source and the top surface of the wafer base form an electrical property The top source is electrically connected to the exposed bottom electrode after the wafer base is packaged, and is cooled; a first metal connection plate is stacked and adhered to the bottom drain of the low-end MOSFET chip; The high-side MOSFET wafer is directly stacked or flipped and stacked and bonded on the first metal connection board, so that the bottom drain of the high-side MOSFET wafer or the flipped top source passes through the first metal connection board and the low The bottom drain of the terminal MOSFET chip is electrically connected; a second metal connection board is stacked and electrically connected to the top source of the high side MOSFET chip, or the bottom portion after the flipping a control wafer is also disposed on the wafer base, and a plurality of electrodes are disposed between the plurality of pins and the electrodes of the high-side and low-side MOSFET wafers to form an electrical property. Connecting, wherein the plurality of pins comprise a low-side gate pin, and a lead portion and an in-line portion are disposed; Corresponding to the position of the in-line portion, a matching notch is formed on the base of the wafer, so that the low-end gate pin is in the notch, and a corresponding setting is formed between the wafer base and the wafer base; The low-side MOSFET chip is disposed, and the top gate is bonded to the in-line portion to form an electrical connection with the low-side gate pin. The jointly packaged power semiconductor device of claim 1, wherein the inscribed portion of the low-side gate pin is provided with a semi-etched region from the bottom surface; the semi-etched region is encapsulated Filled with plastic material. The jointly packaged power semiconductor device of claim 2, wherein a half of the corrosion region is disposed from the bottom surface to the side of the wafer base corresponding to the inline portion; The width matches the width of the inscribed portion and is filled with the molding material during packaging. The jointly packaged power semiconductor device of claim 1, wherein the control wafer is bonded to the lead portion of the low-side gate pin by a bonding wire bond. A jointly packaged power semiconductor device, comprising: a high side MOSFET chip and a low side MOSFET chip, each having a bottom drain, a top gate and a top source; a lead frame provided with a wafer base And a plurality of pins separated from the wafer base and electrically connected; the low-end MOSFET chip is flip-bonded on the wafer base such that the top source and the top surface of the wafer base form an electrical property The top source is electrically connected to the exposed bottom electrode after the wafer base is packaged, and is cooled; a first metal connection plate is stacked and adhered to the bottom drain of the low-end MOSFET chip; The high-side MOSFET wafer is directly stacked or flipped and stacked and bonded on the first metal connection board, so that the bottom drain of the high-side MOSFET wafer or the flipped top source passes through the first metal connection board and the low The bottom drain of the terminal MOSFET chip is electrically connected; a second metal connection board is stacked and electrically connected to the top source of the high side MOSFET chip, or the inverted bottom drain; a control chip And disposed on the wafer base, the plurality of electrodes disposed therebetween, and the electrodes of the high-side and low-side MOSFET wafers are electrically connected to each other; and a second An intermediate connecting member; the low-end MOSFET chip is flip-mounted, and the top gate is bonded to the conductive upper surface of the second intermediate connecting member and electrically connected; the second intermediate connecting member has a lower surface adhered It is connected to the wafer base and insulated from the wafer base. The jointly packaged power semiconductor device of claim 5, wherein the low-side MOSFET chip has the top source electrically connected to the wafer pedestal via a thick conductive adhesive. The thickness of the thickened conductive adhesive is matched to the thickness of the second intermediate joint on the wafer base and the adhesive on the upper and lower sides thereof. The jointly packaged power semiconductor device of claim 5, wherein the top gate position of the low-side MOSFET wafer is formed with a second recess on a top surface of the wafer base; The second intermediate connecting member is correspondingly bonded in the matching second recess and is separated and insulated from the wafer base at the periphery thereof. The power of the joint package as described in any one of claims 5 to 7 The semiconductor component, wherein the second intermediate bonding component is a conductive metal piece, the lower surface of which is fixedly attached to the wafer base or the second recess by an insulating adhesive. The jointly packaged power semiconductor device according to any one of claims 5 to 7, wherein the second intermediate connecting member is provided with a conductive metal upper layer and an insulator lower layer; a bottom surface of the insulator lower layer Attached to the wafer base or the second recess by a conductive or non-conductive adhesive. The jointly packaged power semiconductor component of any one of clauses 5 to 7, wherein the control wafer is electrically connected to the upper surface of the second intermediate connector to form and flip An electrical connection of the top gate of the low side MOSFET chip is mounted. A jointly packaged power semiconductor device, comprising: a high side MOSFET chip and a low side MOSFET chip, each having a bottom drain, a top gate and a top source; a lead frame provided with a wafer base And a plurality of pins separated from the wafer base and electrically connected; the low-end MOSFET chip is flip-bonded on the wafer base such that the top source and the top surface of the wafer base form an electrical property The top source is electrically connected to the exposed bottom electrode after the wafer base is packaged, and is cooled; a first metal connection plate is stacked and adhered to the bottom drain of the low-end MOSFET chip; The high-side MOSFET wafer is directly stacked or flipped and stacked and bonded on the first metal connection board, so that the bottom drain of the high-side MOSFET wafer or the flipped top source passes through the first metal connection board and the low The bottom drain of the terminal MOSFET chip is electrically connected; a second metal connection plate, which is stacked and electrically connected to the top source of the high-side MOSFET chip or to the inverted bottom drain; a control wafer is also disposed on the wafer base, and the set is Correspondingly, an electrical connection is formed between the plurality of electrodes and the plurality of pins, and the electrode of the high-side and low-side MOSFET wafers; wherein the control wafer has a bottom surface that is insulatively bonded to the wafer base Upside down; mounting the low-end MOSFET wafer over a portion of the top surface of the control wafer; covering some of the electrodes on the top surface of the control wafer, and the top gate and a portion of the top of the low-side MOSFET wafer The source is directly bonded to form an electrical connection. The jointly packaged power semiconductor device of claim 11, wherein the remaining top source of the low-side MOSFET wafer is electrically connected to the wafer base through a thick conductive adhesive. The thickness of the thickened conductive adhesive is matched to the thickness of the wafer on the wafer base after the control wafer and the adhesive thereon. The jointly packaged power semiconductor device of claim 11, wherein a top surface of the wafer base forms a wafer recess; the control wafer is correspondingly bonded in the matching groove of the wafer, and It is separated from and insulated from the wafer base at its periphery. A jointly packaged power semiconductor device, comprising: a high side MOSFET chip and a low side MOSFET chip, each having a bottom drain, a top gate and a top source; a lead frame provided with a wafer base a socket, and a plurality of pins separated from the wafer base and electrically connected; the low-end MOSFET chip is flip-bonded to the wafer base to make the top source and The top surface of the wafer base is electrically connected; the top source is further electrically connected to the exposed bottom electrode after the wafer base is packaged, and heat is dissipated; a first metal connection plate is stacked and bonded thereto. The bottom drain of the low-side MOSFET chip; the high-side MOSFET wafer is directly stacked or flipped and stacked and bonded on the first metal connection board to make the bottom drain of the high-side MOSFET wafer or the top source after the flipping, The first metal connection plate is electrically connected to the bottom drain of the low-end MOSFET chip; a second metal connection plate is stacked and electrically connected to the top source of the high-side MOSFET chip, or flipped a rear bottom drain; a control wafer, also disposed on the wafer base, between the plurality of electrodes disposed between the plurality of pins, and between the electrodes of the high-side and low-side MOSFET wafers Corresponding to form an electrical connection; a first intermediate connecting member; the high-side MOSFET chip flipped and mounted, the top gate and the conductive upper surface of the first intermediate connecting member are correspondingly bonded and electrically connected ; The first intermediate coupling member, its lower surface on the first bonding metal fitting plate, and insulated from the first metal web. The co-packaged power semiconductor device of claim 14, wherein the top source is electrically connected to the first metal connection via a thick conductive adhesive. The thickness of the thick conductive adhesive is matched with the thickness of the first metal connecting plate on which the first intermediate connecting member and the adhesive on the upper and lower sides are disposed. The jointly packaged power semiconductor component of claim 14, wherein the top gate position of the high side MOSFET wafer is in the first metal connection A first groove is formed on the top surface of the plate; the first intermediate connecting member is correspondingly bonded in the matching first groove, and is separated and insulated from the first metal connecting plate at a periphery thereof. The jointly packaged power semiconductor component of any one of claims 14 to 16, wherein the first intermediate junction is a conductive metal sheet, the lower surface of which is passed through an insulating adhesive. And fixedly attached to the first metal connecting plate or the first groove. The jointly packaged power semiconductor device according to any one of claims 14 to 16, wherein the first intermediate connecting member is provided with a conductive metal upper layer and an insulator lower layer; a bottom surface of the insulator lower layer Attached to the first metal connecting plate or the first recess by a conductive or non-conductive adhesive. The jointly packaged power semiconductor component of any one of clauses 14 to 16, wherein the control wafer is electrically connected to an upper surface of the first intermediate junction to form and flip An electrical connection of the top gate of the high side MOSFET chip is mounted. A jointly packaged power semiconductor device, comprising: a high side MOSFET chip and a low side MOSFET chip, each having a bottom drain, a top gate and a top source; a lead frame provided with a wafer base And a plurality of pins separated from the wafer base and electrically connected; the low-end MOSFET chip is flip-bonded on the wafer base such that the top source and the top surface of the wafer base form an electrical property The top source is electrically connected to the exposed bottom electrode after the wafer base is packaged, and is cooled; a first metal connection plate is stacked and adhered to the bottom drain of the low-end MOSFET chip; The high-side MOSFET wafer is directly stacked or flipped and stacked and bonded on the first metal connection board, so that the bottom drain of the high-side MOSFET wafer or the flipped top source passes through the first metal connection board and the low The bottom drain of the terminal MOSFET chip is electrically connected; a second metal connection board is stacked and electrically connected to the top source of the high side MOSFET chip, or the inverted bottom drain; a control chip And disposed on the wafer base, the plurality of electrodes disposed therebetween, and the electrodes, and the electrodes of the high-side and low-side MOSFET wafers respectively form an electrical connection; wherein The top source and the top gate of the high-side MOSFET chip, or the bottom drain of the high-side MOSFET chip that is flipped mounted, are respectively electrically connected to the control wafer through a connecting wire bond. The jointly packaged power semiconductor device of claim 20, wherein the plurality of pins comprise a switch pin electrically connected to the first metal connection plate; the control chip, and the switch The foot is bonded by a connecting wire to form an electrical connection with the first metal connecting plate. The jointly packaged power semiconductor device of claim 20, wherein the plurality of pins comprise a high side source pin; the top source of the high side MOSFET chip passes through the second metal connection plate, Electrically connected to the high side source pin. The co-packaged power semiconductor device of claim 20, wherein the plurality of pins comprise a high-side drain pin; the bottom drain of the high-side MOSFET chip flipped through the second metal The connection board is electrically connected to the high-end drain pin.