CN113629016A - Gallium nitride HEMT chip integration packaging structure and manufacturing method thereof - Google Patents

Gallium nitride HEMT chip integration packaging structure and manufacturing method thereof Download PDF

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Publication number
CN113629016A
CN113629016A CN202110903905.XA CN202110903905A CN113629016A CN 113629016 A CN113629016 A CN 113629016A CN 202110903905 A CN202110903905 A CN 202110903905A CN 113629016 A CN113629016 A CN 113629016A
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chip
island
gallium nitride
source
pad
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谢文华
任炜强
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Shenzhen Zhenmaojia Semiconductor Co ltd
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Shenzhen Zhenmaojia Semiconductor Co ltd
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Abstract

The structure sequentially comprises a heat dissipation slide glass, a gallium nitride HEMT chip, a first packaging adhesive layer, a fan-out circuit layer, an MOSFET chip, a second packaging adhesive layer and a metal island layer according to packaging procedures. The source electrode inner island of the fan-out circuit layer is formed in a block deviating from the gallium nitride HEMT chip, one end of the drain electrode circuit extends in a fan-out mode to be far away from the gallium nitride HEMT chip, the gate electrode circuit is located between the source electrode inner island and the drain electrode circuit, the MOSFET chip is arranged on the source electrode inner island, the drain electrode of the MOSFET chip is connected to the source electrode of the gallium nitride HEMT chip at intervals, the source electrode outer island of the metal island layer conducts and interconnects a second source electrode pad of the MOSFET chip and the gate electrode circuit, the source electrode short-circuit path of the MOSFET chip is connected with the gate electrode of the gallium nitride HEMT chip, and the MOSFET chip is located in a packaging adhesive layer different from the gallium nitride HEMT chip. The integrated packaging structure of the gallium nitride HEMT chip has the effects of reducing parasitic inductance generated at the positions of the internal gate electrode and the internal source electrode of the gallium nitride HEMT chip and improving the response sensitivity of the MOSFET chip.

Description

Gallium nitride HEMT chip integration packaging structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of packaging of gallium nitride HEMT chips, in particular to an integrated packaging structure of a gallium nitride HEMT chip and a manufacturing method thereof.
Background
The base material of the working layer of a gallium nitride HEMT (high electron mobility transistor) chip is gallium nitride (GaN), and the base material of the working layer of a MOSFET chip is silicon (Si). Due to the material characteristics, a PN junction cannot be arranged in the gallium nitride HEMT chip, the conduction between the source electrode and the drain electrode is conducted through the middle electronic layer, and the gallium nitride HEMT chip can be turned off only by applying a sufficient negative voltage on the gate electrode. Therefore, the gan HEMT chip has the advantage of fast switching speed compared to a MOSFET (metal oxide semiconductor field effect transistor) chip, but based on the structural characteristics, the switching on operation of the gate needs to be within the working range of negative voltage, when the gate is grounded or the voltage is 0V, the gan HEMT chip is turned on, and a sufficiently large negative voltage needs to be given, so that the source and the drain of the gan HEMT chip are turned off, and thus, the risk of power consumption and leakage current exists. Therefore, the power device of the gan HEMT mainly solves the problem of how to switch on the switch in the working range of positive voltage (including voltage 0V) to realize that the gate is grounded or the gan HEMT chip is turned off under the voltage 0V, and various prior arts are available at present.
The invention patent publication No. CN103872119A discloses a high electron mobility transistor and a method of manufacturing the same, the HEMT includes: the device comprises a substrate, a first gallium nitride layer, a P-type gallium nitride layer, a second gallium nitride layer, a barrier layer, a grid, a source and a drain. The first gallium nitride layer is formed on the substrate, viewed from a cross section, the first gallium nitride layer has a step profile, and the P-type gallium nitride layer is formed on the upper step surface of the step profile and is provided with an enhanced side wall; the second gallium nitride layer is formed on the P-type gallium nitride layer, and the barrier layer is formed on the second gallium nitride layer, so that a two-dimensional electron cloud (2-delctron gas,2DEG) is formed between the barrier layer and the second gallium nitride layer. The grid is formed outside the enhanced side wall and used for receiving grid voltage so as to conduct or not conduct the HEMT. That is to say, the technical scheme for realizing the gate switch conduction in the positive voltage working range is to perform the step-shaped process change in the chip structure, that is, the internal chip structure of the existing gallium nitride HEMT chip needs to be changed, and the reliability and other characteristics of the chip need to be verified again.
The invention patent publication No. CN112768427A discloses a packaging structure and a packaging method of a gallium nitride HEMT, and a gallium nitride HEMT chip has high switch-on speed but high heat generation in use. In order to improve the heat dissipation performance of the packaging structure, the to-be-packaged gallium nitride HEMT chip is fixed and electrically connected in the heat dissipation area, the grid electrode of the to-be-packaged gallium nitride HEMT chip is positioned between the source electrode and the drain electrode, the parasitic inductance of the driving loop is reduced, and the source electrode and the second conductive bonding pad are electrically connected through the fourth electric connection component to form the Kelvin source electrode. In the prior art, a gan HEMT chip is usually a single chip package structure, and a pin-less lead frame is used to increase heat dissipation performance, but the technical problem of gate switch conduction in a positive voltage working range cannot be solved.
The invention discloses a high-current cascade enhanced GaN full-bridge power module packaging structure and a packaging method, wherein the structure comprises a packaging shell, a metal lead frame and pins, and the packaging shell also comprises: the HEMT device comprises a first cascade enhancement type GaN HEMT device, a second cascade enhancement type GaN HEMT device, a third cascade enhancement type GaN HEMT device, a fourth cascade enhancement type GaN HEMT device and a full-bridge gate driving circuit. Any cascade enhancement mode GaN HEMT device in the module provided by the prior patent realizes large current by connecting a plurality of GaN HEMT devices in parallel; in addition, a voltage regulation circuit is required to be added to ensure that the internal high-voltage depletion type GaN device works in a safe region state. In the prior patent, a plurality of GaN HEMTs are connected in parallel to achieve the purpose of large current; it is not specifically disclosed how the additional voltage regulator circuit is integrated into the package structure, and it can be seen from the figure that the conventional way of connecting the chips side by side and the wire bonding is still adopted. Among the relevant prior art, the setting of a large amount of routing binding lines must produce great parasitic inductance in packaging structure, is unfavorable for improving gallium nitride HEMT power device's operating frequency, and the lead wire mode of binding lines has the encapsulation internal resistance simultaneously, also can cause the electrical loss to need great encapsulation size just can seal two above chips down, be unfavorable for packaging structure's miniaturization. In order to reduce the inductance, an additional DBC insulating sheet is required inside another type of similar package structure, and the insulating sheet is a poor thermal conductor, which is not favorable for heat dissipation of the package structure.
Disclosure of Invention
The invention mainly aims to provide a gallium nitride HEMT chip integrated packaging structure, which has the effect of switching on and off a gate electrode of the packaging structure in a positive voltage working range so as to close the gallium nitride HEMT chip under grounding or 0V, does not need to change the internal chip structure of the existing gallium nitride HEMT chip, and solves the problem of power consumption and leakage current caused by the fact that the gate electrode in the existing gallium nitride HEMT chip packaging structure can be switched off in a negative voltage working range. In a practical application, the package structure can be turned off by 0V of the surface gate and turned on by 5V of the gallium nitride HEMT chip.
The second objective of the present invention is to provide a method for manufacturing an integrated package structure of a gallium nitride HEMT chip, which effectively integrates the gallium nitride HEMT chip and the MOSFET chip in a structure conforming to the preferential heat dissipation of the gallium nitride HEMT chip, thereby reducing the difficulty of integrating a heterogeneous chip in semiconductor package manufacturing and improving the production smoothness of the package process flow.
The third objective of the present invention is to provide an electronic device, which can rapidly derive the internal heat of the gallium nitride HEMT chip, thereby reducing the influence of the heat generated by the gallium nitride HEMT chip on the electrical performance of the MOSFET chip.
The main purpose of the invention is realized by the following technical scheme:
a gallium nitride HEMT chip integration packaging structure is provided, which comprises:
the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and the front surface of the gallium nitride HEMT chip is provided with a first source pad, a first gate pad and a first drain pad;
the first packaging adhesive layer is formed on the heat dissipation carrier to seal the gallium nitride HEMT chip, the first packaging adhesive layer has a first molding height on the gallium nitride HEMT chip, and the first packaging adhesive layer is provided with a first through hole to expose the first source pad, the first gate pad and the first drain pad;
a fan-out wiring layer formed on the first encapsulation glue layer, the fan-out wiring layer including: the source electrode inner island is communicated with the first source electrode pad through a through hole, the gate electrode line is communicated with the first gate electrode pad through the through hole, and the drain electrode line is communicated with the first drain electrode pad through the through hole;
the MOSFET chip is arranged on the source inner island, so that a drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad, and a second source pad and a second gate pad are arranged on the front surface of the MOSFET chip;
a second packaging adhesive layer formed on the first packaging adhesive layer and the fan-out circuit layer, wherein the second packaging adhesive layer has a second molding height on the MOSFET chip, and the second packaging adhesive layer is provided with a second through hole to expose the second source pad and the second gate pad;
a metal island layer formed on the second encapsulation glue layer, the metal island layer comprising: the through hole is communicated with and interconnects the second source electrode pad and the source electrode outer island of the gate electrode circuit, the gate electrode island communicated to the second gate electrode pad through the through hole and the drain electrode island communicated to the fan-out end of the drain electrode circuit through the through hole;
with the gate island being turned on or off in the positive and negative voltage working range (the negative voltage working range includes 0V), the potential of the first source pad of the gallium nitride HEMT chip can be synchronously turned down or turned up so as to synchronously turn on or turn off the gallium nitride HEMT chip.
By adopting the technical scheme, the second source pad of the MOSFET chip is short-circuited to the first gate pad of the gallium nitride HEMT chip by utilizing the source outer island to be used as a source connection of the whole packaging structure, the second gate pad of the MOSFET chip can be used as a gate connection of the whole packaging structure, the working voltage from the turn-off to the turn-on of the gate can be increased to 0V negative voltage turn-off and 0V positive voltage turn-on, the gate voltage on the packaging surface is grounded or 0V potential, and the power-saving constant-off state is still maintained. The gallium nitride HEMT chip and the MOSFET chip are efficiently integrated under an FOPLP (Fan-Out Panel Level Package) packaging framework, the MOSFET chip is arranged on the source inner island on the first packaging adhesive layer, so that the drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad of the gallium nitride HEMT chip, the MOSFET chip is relatively deviated from the gallium nitride HEMT chip, the gallium nitride HEMT chip is arranged on the heat dissipation carrier, the gallium nitride HEMT chip has higher external heat conductivity than the MOSFET chip, the gallium nitride HEMT chip is not directly thermally coupled with the MOSFET chip, and a faster external heat dissipation conduction path is provided for high-temperature energy of the gallium nitride HEMT chip than that of the MOSFET chip.
The invention may in a preferred example be further configured to: the off working voltage of the first drain pad of the gallium nitride HEMT chip is between 100 and 600V through the drain island, the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip are in short circuit through the source outer island, the off working voltage and the on working voltage of the first gate pad of the gallium nitride HEMT chip are both smaller than 0V, and when the source and the drain of the MOSFET chip are closed under negative voltage (including 0V), the voltage of the first source pad of the gallium nitride HEMT chip is passively raised through the gate island, and the voltage of ≦ 0V of the first gate pad of the gallium nitride HEMT chip is still not enough to turn on the gallium nitride HEMT chip.
By adopting the preferable technical characteristics, the second gate electrode pad of the MOSFET chip is connected as the gate electrode of the whole packaging structure by utilizing the gate electrode island, the second source electrode pad of the MOSFET chip is short-circuited to the first gate electrode pad of the gallium nitride HEMT chip by utilizing the source electrode outer island in a matching way, and the second gate electrode pad is also connected as the source electrode of the whole packaging structure, so that the gate electrode working voltage of the gallium nitride HEMT chip integrated packaging structure is changed, the interference of parasitic inductance is avoided, and the gallium nitride HEMT chip integrated packaging structure can be turned off at the ground or 0 potential. The source and drain electrode arrangement from the gallium nitride HEMT chip to the package bottom surface is changed, the turn-off working voltage of the first drain electrode pad of the gallium nitride HEMT chip can be operated at a high voltage of 100-600V, namely, the turn-off and turn-on working voltages of the first gate electrode pad of the gallium nitride HEMT chip are both smaller than 0V, when the MOSFET chip is turned off at the source and drain electrodes, the voltage of the first source electrode pad of the gallium nitride HEMT chip is passively raised, the voltage of ≦ 0V of the first gate electrode pad of the gallium nitride HEMT chip is not enough to turn on the gallium nitride HEMT chip, and the switching operation of synchronous turn-on and synchronous turn-off of the gallium nitride HEMT chip by the MOSFET chip is realized.
The invention may in a preferred example be further configured to: the turn-off working voltage of the gate island is less than or equal to 0V, the turn-on working voltage of the gate island is 3-20V, and a Schottky diode is reversely arranged in the MOSFET chip.
By adopting the preferable technical characteristics, the turn-off working voltage of the gate island is less than or equal to 0V, the source-drain connection of the MOSFET chip is still turned off under the ground or 0V, the gallium nitride HEMT chip is also synchronously turned off, when the power switch is switched and used, the voltage of the outer island of the source is stabilized at a negative voltage, the voltage change of the drain island does not influence the voltage relatively far away from the gate island, and the turn-on working voltage of the gate island can be in a relatively stable value with small fluctuation between 3 and 20V. And a Schottky diode is reversely arranged in the MOSFET chip and is used for eliminating the parasitic capacitance of the MOSFET chip which takes silicon as a base material.
The invention may in a preferred example be further configured to: the source inner island is relatively deviated from the gallium nitride HEMT chip and is larger than the first source pad, and the size of the source inner island is larger than and the outline of the source inner island corresponds to the back surface of the MOSFET chip, so that the drain layer is substantially combined with the source inner island.
By adopting the preferable technical characteristics, the integrated packaging structure utilizes the fact that the source electrode inner island on the first packaging adhesive layer is relatively deviated from the gallium nitride HEMT chip and has the size larger than the first source electrode pad, so that the MOSFET chip does not need to be directly placed on the first source electrode pad of the gallium nitride HEMT chip, the size of the MOSFET chip can be larger than the first source electrode pad of the gallium nitride HEMT chip, the size of the MOSFET chip is not limited, and the on-resistance of a wire bonding lead in packaging does not rise, so that the current performance of the MOSFET chip can be maintained.
The invention may in a preferred example be further configured to: the source electrode outer island is relatively deviated and larger than the source electrode inner island in size, the through hole of the first packaging adhesive layer and the through hole of the second packaging adhesive layer which are electrically connected with the source electrode outer island correspond to each other in a straight-through mode so as to shorten a conducting path to be less than 100um, and the packaging internal resistance of the gallium nitride HEMT chip integrated packaging structure is less than 0.2 milliohm.
By adopting the preferable technical characteristics, the source outer island is relatively deviated and has a size larger than that of the source inner island, the through hole of the first packaging adhesive layer electrically connected with the source outer island on the first gate pad of the gallium nitride HEMT chip corresponds to the through hole of the second packaging adhesive layer in a straight-through manner so as to shorten the conduction path to be less than 100um, the internal resistance of the package of the integrated packaging structure of the gallium nitride HEMT chip can also reach below 0.2 milliohm, therefore, the transmission path of the first gate pad and the first source pad on the gallium nitride HEMT chip is short, the configuration relationship of the chip and the packaging structure between the gate and the source is interchanged, and the state that the source of the chip is relatively far away from the drain is changed into the state that the gate of the package is relatively far away from the drain.
The main purpose of the invention can also be realized by another technical scheme as follows:
a gallium nitride HEMT chip integration packaging structure is provided, which comprises: the field-effect transistor (FOPLP) circuit structure comprises an inner source island and an outer source island, wherein the inner source island is positioned in the FOPLP Packaging adhesive layer and connected with a source electrode of the gallium nitride HEMT chip and a drain electrode of the MOSFET chip in an interlayer mode, and the outer source island is positioned on one surface of the FOPLP Packaging adhesive layer and short-circuits a grid electrode of the gallium nitride HEMT chip and a source electrode of the MOSFET chip in a long and short through hole mode.
By adopting the technical scheme, the source electrode of the gallium nitride HEMT chip and the drain electrode of the MOSFET chip are connected in a manner of a source electrode inner island interlayer in the FOPLP packaging adhesive layer, and the gate electrode of the gallium nitride HEMT chip and the source electrode of the MOSFET chip are in short circuit by a source electrode outer island at the bottom surface of the package in a manner of penetrating through the FOPLP packaging adhesive layer by a long through hole and a short through hole, so that the integrated package of the heterogeneous chip with the circuit structure with the gate electrode being grounded or having a voltage of 0V and taking the gallium nitride HEMT chip as a closing effect is realized, the parasitic inductance is greatly reduced, and the heat dissipation of the gallium nitride HEMT chip is improved.
The invention may in a preferred example be further configured to: the FOPLP circuit structure further comprises a drain island and a gate island, wherein the drain island and the gate island are located on the same surface of the FOPLP packaging adhesive layer, the drain island is originally connected with the drain of the gallium nitride HEMT chip, and the gate island is originally connected with the gate of the MOSFET chip.
By adopting the preferable technical characteristics, the drain electrode of the gallium nitride HEMT chip and the gate electrode of the MOSFET chip are originally connected by the drain electrode island and the gate electrode island on the same surface of the FOPLP packaging adhesive layer, other active devices are not connected between the drain electrode island and the drain electrode of the gallium nitride HEMT chip, other active devices are not connected between the gate electrode island and the gate electrode of the MOSFET chip, the external lead-in path of the chip inside the package is shortened, the complicated and long routing length is not needed, and the gate electrode function of the MOSFET chip is used as the gate electrode function of the whole gallium nitride HEMT chip integrated packaging structure.
The main purpose of the invention is realized by the following technical scheme:
a method for manufacturing a gallium nitride HEMT chip integrated package structure is provided, which is used for manufacturing the gallium nitride HEMT chip integrated package structure which can be combined by any technical scheme, and the manufacturing method comprises the following steps:
providing a heat dissipation slide;
arranging a gallium nitride HEMT chip on the heat dissipation carrier, so that the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and the front surface of the gallium nitride HEMT chip is provided with a first source pad, a first gate pad and a first drain pad;
forming a first packaging adhesive layer on the heat dissipation chip in a flat plate molding manner so as to seal the gallium nitride HEMT chip, wherein the first packaging adhesive layer has a first molding height on the gallium nitride HEMT chip, and the first packaging adhesive layer is provided with a first through hole so as to expose the first source pad, the first gate pad and the first drain pad;
forming a fan-out wiring layer on the first encapsulation glue layer, the fan-out wiring layer comprising: the source electrode inner island is communicated with the first source electrode pad through a through hole, the gate electrode line is communicated with the first gate electrode pad through the through hole, and the drain electrode line is communicated with the first drain electrode pad through the through hole;
arranging an MOSFET chip on the source inner island, so that a drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad, and a second source pad and a second gate pad are arranged on the front surface of the MOSFET chip;
forming a second packaging adhesive layer on the first packaging adhesive layer and the fan-out circuit layer in a flat plate molding manner, wherein the second packaging adhesive layer has a second molding height on the MOSFET chip, and a second through hole is formed in the second packaging adhesive layer so as to expose the second source pad and the second gate pad;
forming a metal island layer on the second encapsulation glue layer, wherein the metal island layer comprises: the through hole is communicated with and interconnected with the second source electrode pad and the source electrode outer island of the gate electrode circuit, the gate electrode island communicated to the second gate electrode pad through the through hole and the drain electrode island communicated to the fan-out end of the drain electrode circuit through the through hole.
By adopting the technical scheme, FOPLP layer-by-layer packaging is utilized, a main heat dissipation path of the gallium nitride HEMT chip is firstly established, first layer packaging is carried out, then an electric path for interconnecting the MOSFET chip and second layer packaging are established, the fan-out circuit layer is arranged on the first packaging adhesive layer, the fan-out circuit layer comprises a source electrode inner island which is communicated with the first source electrode pad through a through hole, the source electrode inner island is formed in a block deviating from the gallium nitride HEMT chip, and when the MOSFET chip is arranged, the back drain electrode layer of the MOSFET chip can be electrically connected with the first source electrode pad of the gallium nitride HEMT chip. The metal island layer comprises a source outer island which is communicated and interconnected with the second source pad and the gate electrode circuit through a through hole, the voltage difference of a source electrode and a drain electrode of the gallium nitride HEMT chip is changed through the operation of a second gate electrode switch of the MOSFET chip, and then the source electrode and the drain electrode of the gallium nitride HEMT chip are synchronously opened and synchronously closed, the gallium nitride HEMT chip and the MOSFET chip do not need to be connected through an external circuit, and the heat dissipation type heterogeneous chip is miniaturized, packaged and integrated.
The invention may in a preferred example be further configured to:
in the step of forming the metal island layer, the outer source island is configured between the drain island and the gate island;
or/and in the step of forming the first packaging adhesive layer in a flat plate molding manner, the first packaging adhesive layer also covers the peripheral side edges of the heat dissipation slide glass;
or/and in the step of forming the fan-out line layer, the source inner island is relatively deviated from the gallium nitride HEMT chip and has a larger size than the first source pad, and the size of the source inner island is larger than and the outline of the source inner island corresponds to the back surface of the MOSFET chip;
or/and, in the step of disposing the MOSFET chip on the source inner island, the drain layer is fully and substantially bonded to the source inner island;
or/and, in the step of forming the metal island layer, the source outer island is relatively deviated and has a size larger than that of the source inner island, and the through hole of the first packaging adhesive layer electrically connected with the source outer island corresponds to the through hole of the second packaging adhesive layer in a through way, so as to shorten the conduction path to be less than 100um, and further enable the packaging internal resistance of the gallium nitride HEMT chip integrated packaging structure to be controlled to be less than 0.2 milliohm;
or/and the manufacturing method further comprises a step of packaging and separating to obtain a separated gallium nitride HEMT chip integrated packaging structure, wherein the turn-off working voltage of the first drain pad of the gallium nitride HEMT chip is between 100 and 600V through the drain island, the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip are in short circuit through the source outer island, the turn-off and turn-on working voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0V, when the MOSFET chip is in source and drain turn-off, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised, the voltage of the first gate pad of the gallium nitride HEMT chip is not more than 0V, preferably, the turn-off working voltage of the gate island is less than 0V, the turn-on working voltage of the gate island is 3-20V, and a Schottky diode is arranged in the MOSFET chip in a reverse direction.
The technical result corresponding to the characteristics of the device described above can be achieved by using the above-mentioned preferred technical features, with the corresponding structural features or possible combinations of structural features described above.
The main purpose of the invention is realized by the following technical scheme:
an electronic device is proposed, comprising: the integrated packaging structure comprises a printed circuit board and a gallium nitride HEMT chip which is jointed on the printed circuit board and can be combined with the printed circuit board according to any technical scheme, wherein in the packaging bottom surface of the integrated packaging structure of the gallium nitride HEMT chip, a source outer island, a gate island and a drain island which are positioned on the same surface are respectively welded to corresponding pins of the printed circuit board, the heat dissipation slide or the back surface of the gallium nitride HEMT chip is exposed in the packaging top surface of the integrated packaging structure of the gallium nitride HEMT chip, the back surface of the MOSFET chip is not directly thermally coupled with the gallium nitride HEMT chip under the obstruction of a packaging adhesive layer, and the horizontal electric connection path between the drain electrode of the MOSFET chip and the source electrode of the gallium nitride HEMT chip does not exceed the projection area of the MOSFET chip on the packaging top surface.
By adopting the technical scheme, the electronic device can more quickly transfer the heat of the gallium nitride HEMT chip, and the heat dissipation slide is only directly thermally coupled with the gallium nitride HEMT chip, so that the MOSFET chip receives less heat from the gallium nitride HEMT chip.
In summary, the technical solution of the present invention includes at least one of the following technical effects that contribute to the prior art:
1. the first source electrode pad of the gallium nitride HEMT chip is connected with the drain electrode layer of the MOSFET chip through the source electrode inner island on the first through hole of the first packaging adhesive layer, the second source electrode pad of the MOSFET chip is led out to the source electrode outer island on the packaging surface through the second through hole of the second packaging adhesive layer, the connection length of each layer of through hole can be smaller than or equal to 50um (the first molding height of the first packaging adhesive layer is less than or equal to 50um, the second molding height of the second packaging adhesive layer is less than or equal to 50um), and the traditional routing connection length is 1000-2000 um, compared with a routing mode, the interconnection length of the chips in the packaging is greatly reduced, and the parasitic inductance is one order of magnitude smaller than that of the traditional packaging;
2. because the second source electrode pad of the MOSFET chip is connected with the source electrode outer island on the packaging surface through the second through hole of the second packaging adhesive layer, the metal island layer comprising the source electrode outer island can be welded with an external Printed Circuit Board (PCB), so that both the electric conduction path and the heat conduction path are very short, and when the external connection length of the second source electrode pad of the MOSFET chip passing through the source electrode outer island is below 100um, the electric conduction effect and the heat conduction effect of the gallium nitride HEMT chip integrated packaging structure can be optimized;
3. the packaging internal resistance of the gallium nitride HEMT chip integrated packaging structure can be reduced to below 0.2 milliohm, while the existing GaN HEMT packaging structure is above 1 milliohm;
4. the size area of the MOSFET chip is not limited by the area size of the first source electrode pad of the gallium nitride HEMT chip any more, and the MOSFET chip can be larger than the first source electrode pad of the gallium nitride HEMT chip, and the MOSFET chip with better conduction performance can be integrated in a packaging structure, so that the internal resistance of a device of the gallium nitride HEMT chip integrated packaging structure is further reduced;
5. under the structural design, the integrated packaging structure of the gallium nitride HEMT chip has no limitation on the position and arrangement of the electrodes of the gallium nitride HEMT chip, can be flexibly arranged and is convenient to design according to the layout with optimal performance;
6. the back of the gallium nitride HEMT chip of the invention example forms the thermal coupling with the heat-dissipating slide through the adhesive bonding, the heat resistance of the outer casing of the encapsulated junction can be smaller, the heat produced by the gallium nitride HEMT chip is radiated directly through the heat-dissipating slide, can also transmit the heat to the external printed circuit board through the outer island of the source electrode, the heat-dissipating performance is better;
7. the back surface of the gallium nitride HEMT chip and the whole radiating slide are directly thermally coupled together by welding or heat conduction adhesion in the packaging process, the heat generated by the gallium nitride HEMT chip is conducted to the radiating slide covering more than 80% of the top surface of the package, so that the internal thermal resistance of the package is low, the radiating slide can be removed or kept in a product, if higher radiating requirements exist, a radiator can be externally arranged on the top surface of the package, the top surface of the package is made of heat conduction metal, the exposed back surface of the gallium nitride HEMT chip or the outer surface of the radiating slide provides a horizontal mounting reference, and the external radiator is more convenient to install.
Drawings
FIG. 1 is a cross-sectional view of a gallium nitride HEMT chip integrated package structure according to some preferred embodiments of the present invention;
FIG. 2 is a bottom view of a gallium nitride HEMT chip integrated package structure according to some preferred embodiments of the present invention;
FIG. 3 is a circuit diagram of an integrated package structure of a GaN HEMT chip according to some embodiments of the present invention;
fig. 4 is a schematic view of a gallium nitride HEMT chip integrated package method of the present invention, with the gallium nitride HEMT chip disposed on a heat sink slide;
fig. 5 is a schematic view illustrating a first packaging adhesive layer formed on a heat sink chip by a flat mold sealing method in a gallium nitride HEMT chip integrated package method according to some preferred embodiments of the present invention;
fig. 6 is a schematic view illustrating a first through hole is formed in a first packaging adhesive layer in the integrated packaging method for a gallium nitride HEMT chip according to some preferred embodiments of the present invention;
fig. 7 is a schematic view showing a first deposited metal layer forming a fan-out wiring layer formed on a first packaging adhesive layer in a gallium nitride HEMT chip integrated package method according to some preferred embodiments of the present invention;
FIG. 8 is a schematic diagram illustrating the fan-out wiring layer formed in the integrated packaging method for a gallium nitride HEMT chip according to some preferred embodiments of the present invention;
FIG. 9 is a cross-sectional view of a MOSFET chip disposed on an inner island of a source in a gallium nitride HEMT chip integrated package method according to some preferred embodiments of the present invention;
fig. 10 is a schematic view illustrating a second packaging adhesive layer formed on a first packaging adhesive layer by a flat mold method in a gallium nitride HEMT chip integrated package method according to some preferred embodiments of the present invention;
fig. 11 is a schematic view illustrating a second through hole is formed in a second packaging adhesive layer in the integrated packaging method for a gallium nitride HEMT chip according to some preferred embodiments of the present invention;
fig. 12 is a schematic view showing a second deposited metal layer forming a metal island layer formed on a second packaging adhesive layer in the integrated packaging method for a gallium nitride HEMT chip according to some preferred embodiments of the present invention;
fig. 13 is a cross-sectional view of a gallium nitride HEMT chip integrated package structure in accordance with still other embodiments of the present invention.
The LED chip comprises a heat dissipation carrier sheet 10, a gallium nitride HEMT chip 20, a gallium nitride HEMT chip 21, a first source pad 22, a first gate pad 23, a first drain pad 30, a first packaging adhesive layer 31, a first through hole 40, a fan-out circuit layer 40A, a first deposited metal layer 41, an inner source island 42, a gate circuit 43, a drain circuit 50, a MOSFET chip 51, a second source pad 52, a second gate pad 53, a drain layer 54, a Schottky diode 60, a second packaging adhesive layer 61, a second through hole 70, a metal island layer 70A, a second deposited metal layer 71, an outer source island 72, a gate island 73 and a drain island.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of embodiments for understanding the inventive concept of the present invention, and do not represent all embodiments, nor do they explain only embodiments. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention under the understanding of the inventive concept of the present invention are within the protection scope of the present invention.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture, and if the specific posture is changed, the directional indications are changed accordingly. In order to facilitate understanding of the technical solution of the present invention, the gallium nitride HEMT chip integrated package structure of the present invention and the method for manufacturing the same are described and explained in further detail below, but the present invention is not limited to the scope of protection.
The term "heat dissipation carrier" as used herein refers to a heat dissipation exposed area of a heat dissipation object corresponding to the surface of a package, which is 60% or more, particularly 80% or more (as shown in fig. 1), and usually does not exceed 100% of the area of the top surface of the package.
The term "offset" as used herein means that the top and bottom surfaces of the package projected from the bottom surface of the package to the top surface of the package are not aligned with each other at a central point. The term "fan-out" as used herein refers to the extension of an object to fan-out in a direction away from the center of the gallium nitride HEMT chip. The "island" described in the specification is a metal pad layer having an electrical function of the "pad" but having a larger area than the pad, and the shape of the island may be more irregular than the pad, and the island is usually not provided on the surface of the chip. The term "native connection" as used herein refers to an electrical connection path between two electrically connected components in a package without adding any active device, and specifically, the electrical connection path is simply formed by a circuit formed in a wafer level package, and does not include a wire bonding connection nor other devices disposed therebetween.
The accompanying drawings illustrate various embodiments having a common component, and the various embodiments having differences or differences will be described with particularity. Therefore, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features or any combination of a plurality of the technical features described below can be characterized in the same embodiment or whether a plurality of technical features mutually exclusive can be respectively characterized in different variant embodiments.
Fig. 1 is a cross-sectional view of a gallium nitride HEMT chip integrated package structure according to some preferred embodiments of the present invention, fig. 2 is a bottom view of a package of the gallium nitride HEMT chip integrated package structure, fig. 3 is a circuit diagram of the gallium nitride HEMT chip integrated package structure, and fig. 4 to 12 are schematic component section views of the gallium nitride HEMT chip integrated package structure in a packaging process. In the figure, "S" is a Source (Source), "G" is a Gate (Gate), "D" is a Drain (Drain), and in the example, the Source is a carrier start point and the Drain is a carrier end point.
Referring to fig. 1, fig. 2 and fig. 3, in some preferred embodiments of the present invention, an integrated package structure of a gan HEMT chip is provided, including: the structure of the semiconductor device includes a gallium nitride HEMT chip 20, a first packaging adhesive layer 30, a fan-out line layer 40, a MOSFET chip 50, a second packaging adhesive layer 60, and a metal island layer 70. One of the important effects of the invention is that the on-state working voltage for driving the gallium nitride HEMT chip 20 is increased to a positive voltage not containing 0V, the grounding or reference potential of 0V is off (one specific application is 0V off and 5V on), the parasitic inductance is greatly reduced in the packaging structure, and the technical effect of realizing the source and drain off of the gallium nitride HEMT chip 20 without applying a negative voltage is stably achieved.
Referring to fig. 1, a gallium nitride HEMT chip 20 is disposed on a heat sink chip 10 such that the back surface of the gallium nitride HEMT chip 20 is thermally coupled to the heat sink chip 10, and the front surface of the gallium nitride HEMT chip 20 is provided with a first source pad 21, a first gate pad 22 and a first drain pad 23. The semiconductor substrate of the gallium nitride HEMT chip 20 is gallium nitride, and in this example the first gate pad 22 can be located between the first source pad 21 and the first drain pad 23. The heat dissipation carrier 10 is made of a high thermal conductivity metal such as copper.
The first encapsulant layer 30 is formed on the heat dissipation chip 10 to seal the gallium nitride HEMT chip 20, the first encapsulant layer 30 has a first molding height, in an example ≦ 50um, on the gallium nitride HEMT chip 20, the first encapsulant layer 30 is formed with a first through hole 31 to expose the first source pad 21, the first gate pad 22, and the first drain pad 23, and specifically, a plurality of first through holes 31 may be formed on one first source pad 21 or one first drain pad 23. In an example, the outer surface of the heat sink chip 10 may be slightly smaller than the top surface of the package (the top surface of the package is the outward surface of the package product bonded to the printed circuit board, the top surface of the package in fig. 1 is downward and includes the exposed surface of the heat sink chip 10, and the bottom surface of the package in fig. 1 is upward, as shown in fig. 2), and the first encapsulant layer 30 may cover the peripheral side of the heat sink chip 10, so as to more stably hold the heat sink chip 10.
A fan-out wiring layer 40 is formed on the first encapsulation glue layer 30, the fan-out wiring layer 40 including: a source inner island 41 through a via to the first source pad 21, a gate line 42 through a via to the first gate pad 22, and a drain line 43 through a via to the first drain pad 23, wherein the source inner island 41 is formed in a section offset from the gan HEMT chip 20, one end of the drain line 43 is fanned out and extended away from the gan HEMT chip 20, and the gate line 42 is located between the source inner island 41 and the drain line 43. The fan-out wiring layer 40 is typically a wiring formed during wafer level packaging, and the in-source island 41 may be equal to or slightly larger than the MOSFET chip 50. The source inner island 41, the gate line 42 and the drain line 43 of the fan-out line layer 40 can be integrally filled into the first via hole 31 under the corresponding cover region of the first encapsulant 30 to electrically connect the corresponding first source pad 21, first gate pad 22 and first drain pad 23, respectively.
The MOSFET chip 50 is disposed on the source inner island 41, so that the back drain layer 53 of the MOSFET chip 50 is electrically connected to the first source pad 21, and the front surface of the MOSFET chip 50 is provided with a second source pad 51 and a second gate pad 52. The semiconductor substrate of the MOSFET die 50 can be silicon or other non-gallium nitride silicon based semiconductor, such as silicon carbide, with the back drain layer 53 illustratively being located on a different die back surface than the die front surface of the second source pad 51 and the second gate pad 52. The back drain layer 53 may completely cover the back side of the MOSFET chip 50. The size of the intra-source island 41 may be slightly larger than the backside of the MOSFET chip 50.
The second encapsulant layer 60 is formed on the first encapsulant layer 30 and the fan-out line layer 40, the second encapsulant layer 60 has a second encapsulant height, in an example ≦ 50um, on the MOSFET chip 50, the second encapsulant layer 60 is formed with a second through hole 61 to expose the second source pad 51 and the second gate pad 52. The first encapsulant layer 30 and the second encapsulant layer 60 are electrically insulating materials with low expansion coefficients, and may be the same material or different materials with expansion coefficients within a suitable adjustment range.
A metal island layer 70 is formed on the second encapsulation glue layer 60, the metal island layer 70 including: the via through interconnects the second source pad 51 and the source outer island 71 of the gate line 42, the gate island 72 of the via through to the second gate pad 52, and the drain island 73 of the via through to the fan-out end of the drain line 43. One specific arrangement of the source outer island 71, gate island 72 and drain island 73 can be seen in FIG. 2. One circuit structure of the gallium nitride HEMT chip integrated package structure can be seen in fig. 3.
With the gate island 72 turned on or off in the positive and negative voltage operating ranges (the negative voltage operating range includes 0V), the potential of the first source pad 21 of the gallium nitride HEMT chip 20 can also be synchronously turned down or up to synchronously turn on or off the gallium nitride HEMT chip 20.
The basic principle of the embodiment is as follows: the second source pad 51 of the MOSFET chip 50 is shorted to the first gate pad 22 of the gan HEMT chip 20 by the source outer island 71 to serve as a source connection of the whole package structure, and no wire bonding connection is needed, the second gate pad 52 of the MOSFET chip 50 can serve as a gate connection of the whole package structure through the gate island 72, so that the gate can be turned off to an on working voltage and can be increased to a negative voltage turn-off including 0V and a positive voltage turn-on not including 0V (in the prior art, the gan HEMT product is operated to a negative voltage turn-on turn-off not including 0V and a positive voltage turn-on not including 0V), and when the gate voltage at the bottom surface of the package is ground or 0V, the embodiment of the invention still maintains a power-saving constant turn-on state. In a practical application, the package structure can be turned off by 0V and turned on by 5V of the surface gate of the GaN HEMT chip 20. Under a FOPLP (Fan-Out Panel Level Package) packaging framework, the gallium nitride HEMT chip 20 and the MOSFET chip 50 are efficiently integrated, and the MOSFET chip 50 is arranged on the source inner island 41 on the first packaging adhesive layer 30, so that the back drain layer 53 of the MOSFET chip 50 is electrically connected with the first source pad 21 of the gallium nitride HEMT chip 20, parasitic inductance can be reduced, and the size of the back drain layer 53 does not need to be matched to a degree smaller than that of the first source pad 21 of the gallium nitride HEMT chip 20; the MOSFET chip 50 is relatively deviated from the gallium nitride HEMT chip 20, the gallium nitride HEMT chip 20 is arranged on the heat dissipation slide 10, the gallium nitride HEMT chip 20 has higher external heat conductivity than the MOSFET chip 50, and the gallium nitride HEMT chip 20 is not directly thermally coupled with the MOSFET chip 50, providing a faster conduction path for dissipating heat to the outside for the high temperature energy of the gallium nitride HEMT chip 20 than through the MOSFET chip 50.
In a preferred example, the off-state operating voltage of the first drain pad 23 of the gallium nitride HEMT chip 20 is between 100-600V through the drain island 73, the first gate pad 22 of the gallium nitride HEMT chip 20 and the second source pad 51 of the MOSFET chip 50 are shorted through the source outer island 71, the off-state and on-state operating voltages of the first gate pad 22 of the gallium nitride HEMT chip 20 are both less than 0V, when the first gate pad 22 is 0V, the gallium nitride HEMT chip 20 is turned on for source and drain, and when the MOSFET chip 50 is turned off at a lower source and drain voltage of less than or equal to 0V through the source island 72, the voltage of the first source pad 21 of the gallium nitride HEMT chip 20 is passively raised, and the voltage of ≦ 0V of the first gate pad 22 of the gallium nitride chip 20 is still insufficient to turn on the gallium nitride chip 20.
Therefore, the gate island 72 is used to connect the second gate pad 52 of the MOSFET chip 50 to the gate of the entire package structure, and the outer source island 71 is used to connect the second source pad 51 of the MOSFET chip 50 to the first gate pad 22 of the gan HEMT chip 20, and also used as the source of the entire package structure, so as to change the gate operating voltage of the integrated package structure of the gan HEMT chip, without the interference of parasitic inductance, and to turn off the integrated package structure of the gan HEMT chip at ground or 0 potential. The arrangement of the source and drain electrodes from the gallium nitride HEMT chip 20 to the bottom surface of the package is changed, the turn-off working voltage of the first drain electrode pad 23 of the gallium nitride HEMT chip 20 can be operated at a high voltage of 100-600V, even if the turn-off and turn-on working voltages of the first drain electrode pad 22 of the gallium nitride HEMT chip 20 are both less than 0V, when the MOSFET chip 50 is turned off at the source and drain electrodes, the voltage of the first source electrode pad 21 of the gallium nitride HEMT chip 20 is passively raised, the voltage ≦ 0V of the first gate electrode pad 22 of the gallium nitride HEMT chip 20 is not enough to turn on the gallium nitride HEMT chip 20, and the switching operation of the MOSFET chip 50 to the synchronous turn-on and synchronous turn-off of the gallium nitride HEMT chip 20 is realized.
The invention may in a preferred example be further configured to: the turn-off working voltage of the gate island 72 is ≦ 0V, the turn-on working voltage of the gate island 72 is 3-20V, and the Schottky diode 54 is reversely arranged in the MOSFET chip 50. When the power switch is switched and used, the voltage of the source outer island 71 is stabilized at a negative voltage, the voltage change of the drain island 73 does not influence the voltage relatively far from the gate island 72, and the switching-on working voltage of the gate island 72 can be a relatively stable value with small fluctuation between 3V and 20V. A schottky diode 54 (shown in fig. 3) is disposed in the reverse direction in the MOSFET die 50 for eliminating the parasitic capacitance of the MOSFET die 50 based on silicon.
In a preferred example, the source inner island 41 is relatively offset from the gallium nitride HEMT chip 20 and has a size larger than the first source pad 21, and the source inner island 41 is also larger in size and has a profile corresponding to the backside of the MOSFET chip 50, so that the drain layer 53 is substantially bonded to the source inner island 41. The source inner island 41 on the first packaging adhesive layer 30 is relatively deviated from the gallium nitride HEMT chip 20 in the integrated packaging structure and has a larger size than the first source pad 21, so that the MOSFET chip 50 does not need to be directly placed on the first source pad 21 of the gallium nitride HEMT chip 20, the MOSFET chip 50 can be larger than the first source pad 21 of the gallium nitride HEMT chip 20 in size, the size of the MOSFET chip 50 is not limited, and the on-resistance of wire bonding wires in the packaging does not rise, so that the current performance of the MOSFET chip 50 can be maintained.
In a preferred example, the source outer island 71 is relatively deviated and has a size larger than that of the source inner island 41, and the through hole of the first packaging adhesive layer 30 electrically connected with the source outer island 71 corresponds to the through hole of the second packaging adhesive layer 60 so as to shorten the conduction path to be less than 100um, and the in-package resistance of the gallium nitride HEMT chip integrated packaging structure is less than 0.2 milliohm. The source outer island 71 is deviated relatively and has a size larger than that of the source inner island 41, the through hole of the first packaging adhesive layer 30 electrically connected with the source outer island 71 on the first gate pad 22 of the gallium nitride HEMT chip 20 corresponds to the through hole of the second packaging adhesive layer 60 in a straight-through manner so as to shorten a conduction path to be less than 100um, the internal package resistance of the integrated packaging structure of the gallium nitride HEMT chip can also reach less than 0.2 milliohm, therefore, the transmission path of the first gate pad 22 on the gallium nitride HEMT chip 20 and the first source pad 21 is short, the configuration relationship of the chip and the packaging structure between a gate electrode and a source electrode is interchanged, and the state that the source electrode of the chip is relatively far away from the drain electrode is changed into the state that the gate electrode of the package is relatively far away from the drain electrode.
Referring to fig. 4 to 12, the present invention further provides a method for manufacturing a gallium nitride HEMT chip integrated package structure, which is used to manufacture the gallium nitride HEMT chip integrated package structure capable of being combined according to any of the above-mentioned technical solutions, and the method includes the following steps.
Referring to fig. 4, a heat sink chip 10 is provided, and the heat sink chip 10 may be formed in, for example, a leadless lead frame or a motherboard having pre-cut grooves.
Referring to fig. 4, the gallium nitride HEMT chip 20 is disposed on the heat sink chip 10, such that the back surface of the gallium nitride HEMT chip 20 is thermally coupled to the heat sink chip 10, the front surface of the gallium nitride HEMT chip 20 is disposed with a first source pad 21, a first gate pad 22 and a first drain pad 23, in a preferred example, in the step of disposing the gallium nitride HEMT chip 20, the first gate pad 22 is disposed between the first source pad 21 and the first drain pad 23, and in the subsequent step of forming the metal island layer 70, the source outer island 71 is disposed between the drain island 73 and the gate island 72.
Referring to fig. 5 and 6, a first encapsulant layer 30 is formed on the heat sink chip 10 by flat molding to seal the gan HEMT chip 20, the first encapsulant layer 30 has a first molding height on the gan HEMT chip 20, and the first encapsulant layer 30 is formed with a first through hole 31 to expose the first source pad 21, the first gate pad 22 and the first drain pad 23. In a preferred example, in the step of forming the first encapsulating adhesive layer 30 by flat molding, the first encapsulating adhesive layer 30 further covers the peripheral side of the heat dissipation chip 10. In the step of forming the first through hole 31, the first through hole 31 is formed by laser or patterned etching.
Referring to fig. 7 and 8, a fan-out circuit layer 40 is formed on the first encapsulant layer 30, where the fan-out circuit layer 40 includes: a source inner island 41 through a via to the first source pad 21, a gate line 42 through a via to the first gate pad 22, and a drain line 43 through a via to the first drain pad 23, wherein the source inner island 41 is formed in a section offset from the gan HEMT chip 20, one end of the drain line 43 is fanned out and extended away from the gan HEMT chip 20, and the gate line 42 is located between the source inner island 41 and the drain line 43. Referring to fig. 7, a precursor layer for forming the fan-out line layer 40 is a first deposited metal layer 40A, the first deposited metal layer 40A includes a metal body layer, such as a metal foil, formed on the first package adhesive layer 30 in advance before the first via hole 31 is opened, and a hole filling metal (not shown) formed by metal deposition after the first via hole 31 is opened, the metal body layer can protect contamination residues forming the first via hole 31 from adhering to the first package adhesive layer 30 and has an additional function of a hard mask, the fan-out line layer 40 is obtained by metal etching the first deposited metal layer 40A, and the source inner island 41 serves as an island block for bonding the MOSFET chip 50. In a preferred example, in the step of forming the fan-out wiring layer 40, the source inner island 41 is relatively offset from the gallium nitride HEMT chip 20 and has a size larger than the first source pad 21, and the source inner island 41 also has a size larger than and a profile corresponding to the back surface of the MOSFET chip 50.
Referring to fig. 9, a MOSFET chip 50 is disposed on the source inner island 41, such that the back drain layer 53 of the MOSFET chip 50 is electrically connected to the first source pad 21, the front surface of the MOSFET chip 50 is provided with a second source pad 51 and a second gate pad 52, and in the step of disposing the MOSFET chip 50 on the source inner island 41, the drain layer 53 is fully and substantially bonded to the source inner island 41.
Referring to fig. 10 and 11, a second encapsulant layer 60 is formed on the first encapsulant layer 30 and the fan-out trace layer 40 by flat molding, the second encapsulant layer 60 has a second molding height on the MOSFET die 50, and the second encapsulant layer 60 is opened with a second via hole 61 to expose the second source pad 51 and the second gate pad 52.
Referring to fig. 12 and fig. 1, a metal island layer 70 is formed on the second encapsulation glue layer 60, wherein the metal island layer 70 includes: the via through interconnects the second source pad 51 and the source outer island 71 of the gate line 42, the gate island 72 of the via through to the second gate pad 52, and the drain island 73 of the via through to the fan-out end of the drain line 43. In a preferred example, referring to fig. 12, the precursor layer of the metal island layer 70 is formed as a second deposition metal layer 70A, the second deposition metal layer 70A includes a metal body layer, such as a metal foil, formed on the first package adhesive layer 30 in advance before the second via 61 is opened, and a hole filling metal (not shown) formed by metal deposition after the second via 61 is opened, the metal body layer can protect contamination residues forming the second via 61 from adhering to the second package adhesive layer 60, and has an additional function of a hard mask, and the metal island layer 70 is formed by metal etching the second deposition metal layer 70A. In a preferred example, in the step of forming the metal island layer 70, the source outer island 71 is relatively deviated and has a size larger than that of the source inner island 41, and the through hole of the first encapsulant layer 30 electrically connected to the source outer island 71 corresponds to the through hole of the second encapsulant layer 60, so as to shorten the conduction path to less than 100um, thereby controlling the package internal resistance of the gallium nitride HEMT chip integrated package structure to less than 0.2 milliohm.
In a preferred example, the manufacturing method further includes a step of packaging a single gan HEMT chip integrated package structure to obtain a single gan HEMT chip integrated package structure, wherein the off-state operating voltage of the first drain pad 23 of the gan HEMT chip 20 is between 100V and 600V through the drain island 73, the first gate pad 22 of the gan HEMT chip 20 is short-circuited with the second source pad 51 of the MOSFET chip 50 through the source outer island 71, the off-state and on-state operating voltages of the first gate pad 22 of the gan HEMT chip 20 are both less than 0V, the voltage of the first source pad 21 of the gan HEMT chip 20 is passively raised by the MOSFET chip 50 when the source and drain of the MOSFET chip 50 are turned off through the gate island 72, and the voltage of the first gate pad 22 of the gan HEMT chip 20 is less than or equal to 0V and is not enough to turn on the gan HEMT chip 20, preferably, the turn-off working voltage of the gate island 72 is ≦ 0V, the turn-on working voltage of the gate island 72 is 3-20V, and the schottky diode 54 is reversely arranged in the MOSFET chip 50 (as shown in fig. 3). The steps described above with respect to fig. 4-12 are specifically a FOPLP packaging process. In an example, the gan HEMT chip integrated package structure after packaging separation may have package sizes corresponding to DFN 4 × 4, DFN 5 × 6, DFN 8 × 8, and the like.
The basic principle of the embodiment is as follows: the FOPLP is used for layer-by-layer packaging, a main heat dissipation path of the gallium nitride HEMT chip 20 is firstly established, first layer packaging is carried out, then an electric path for interconnecting the MOSFET chip 50 and second layer packaging are established, the fan-out circuit layer 40 is arranged on the first packaging adhesive layer 30, the fan-out circuit layer 40 comprises a source inner island 41 which is communicated with the first source pad 21 through a through hole, the source inner island 41 is formed in a block deviating from the gallium nitride HEMT chip 20, and when the MOSFET chip 50 is arranged, the back drain layer 53 of the MOSFET chip 50 can be electrically connected with the first source pad 21 of the gallium nitride HEMT chip 20. The metal island layer 70 includes a source outer island 71 which is interconnected with the second source pad 51 and the gate line 42 by a through hole conduction, and the voltage difference between the source and the drain of the gallium nitride HEMT chip 20 is changed by the second gate switch operation of the MOSFET chip 50, so as to realize the synchronous opening and synchronous closing of the source and the drain of the gallium nitride HEMT chip 20, without connecting the gallium nitride HEMT chip 20 and the MOSFET chip 50 by an external circuit, and has the effect of heat dissipation type heterogeneous chip miniaturization package integration.
Referring to fig. 13, another embodiment of the present invention further provides an integrated package structure of a gan HEMT chip, including: the field-effect transistor (HEMT) chip comprises a gallium nitride HEMT chip 20 capable of establishing an external heat dissipation path, a metal-oxide-semiconductor field effect transistor (MOSFET) chip 50 sealed in a FOPLP (Fan-Out Panel Level Packaging) Packaging adhesive layer and a FOPLP line structure, wherein the FOPLP line structure comprises an inner source island 41 and an outer source island 71, the inner source island 41 is positioned in the FOPLP Packaging adhesive layer and is connected with a source electrode of the gallium nitride HEMT chip 20 and a drain electrode of the MOSFET chip 50 in an interlayer mode, the outer source island 71 is positioned on one surface of the FOPLP Packaging adhesive layer and is short-circuited with a grid electrode of the gallium nitride HEMT chip 20 and the source electrode of the MOSFET chip 50 in a long-short through hole mode.
The basic principle of the embodiment is as follows: the source electrode of the gallium nitride HEMT chip 20 and the drain electrode of the MOSFET chip 50 are connected in an interlayer mode by using the source electrode inner island 41 in the FOPLP packaging adhesive layer, and the source electrode outer island 71 at the bottom surface of the package is in short circuit with the grid electrode of the gallium nitride HEMT chip 20 and the source electrode of the MOSFET chip 50 by using a mode of penetrating through the FOPLP packaging adhesive layer by using long and short through holes, so that the integrated package of the heterogeneous chip with the circuit structure with the grid electrode being grounded or under the voltage of 0V and taking the gallium nitride HEMT chip 20 as a closing effect is realized, the parasitic inductance is greatly reduced, and the heat dissipation of the gallium nitride HEMT chip 20 is improved.
In a preferred example, the FOPLP circuit structure further includes a drain island 73 and a gate island 72, which are located on the same surface of the FOPLP package adhesive layer, the drain island 73 is originally connected to the drain of the gallium nitride HEMT chip 20, and the gate island 72 is originally connected to the gate of the MOSFET chip 50.
By adopting the preferable technical characteristics, the drain electrode 73 of the gallium nitride HEMT chip 20 and the gate electrode 72 of the gallium nitride HEMT chip 20 are originally connected by the drain electrode island 73 and the gate electrode island 72 on the same surface of the FOPLP packaging adhesive layer, other active devices are not connected between the drain electrode island 73 and the drain electrode of the gallium nitride HEMT chip 20, other active devices are not connected between the gate electrode island 72 and the gate electrode of the MOSFET chip 50, the external lead-out path of the chip inside the package is shortened, the complicated and long routing length is not needed, and the gate electrode function of the MOSFET chip 50 is used as the gate electrode function of the integrated packaging structure of the gallium nitride HEMT chip of the whole gallium nitride HEMT chip integrated packaging structure.
Other examples of the present invention also provide an electronic apparatus including: a printed circuit board and a gallium nitride HEMT chip integrated package structure (an example structure is shown in FIG. 1 or FIG. 13) which is bonded on the printed circuit board and can be combined according to any technical scheme, in the bottom surface of the integrated package structure of the gan HEMT chip, the source outer island 71, the gate island 72 and the drain island 73 on the same surface are respectively soldered to corresponding pins of the printed circuit board; the gallium nitride HEMT chip is integrated in the top surface of the package structure, and the back surface of the heat dissipation slide 10 or the gallium nitride HEMT chip 20 is exposed; the back surface of the MOSFET chip 50 is not directly thermally coupled with the gallium nitride HEMT chip 20 under the obstruction of a packaging adhesive layer; the horizontal electric connection path between the drain electrode of the MOSFET chip 50 and the source electrode of the gallium nitride HEMT chip 20 does not exceed the projection area of the MOSFET chip 50 on the top surface of the package. Therefore, the electronic device can more quickly transfer heat out of the gallium nitride HEMT chip 20, and the heat sink 10 is only thermally coupled directly to the gallium nitride HEMT chip 20, so that the MOSFET chip 50 receives less heat from the gallium nitride HEMT chip 20.
The embodiments of the present invention are merely preferred embodiments for easy understanding or implementing of the technical solutions of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes in structure, shape and principle of the present invention should be covered by the claims of the present invention.

Claims (10)

1. A gallium nitride HEMT chip integration packaging structure is characterized in that, includes:
the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and the front surface of the gallium nitride HEMT chip is provided with a first source pad, a first gate pad and a first drain pad;
the first packaging adhesive layer is formed on the heat dissipation carrier to seal the gallium nitride HEMT chip, the first packaging adhesive layer has a first molding height on the gallium nitride HEMT chip, and the first packaging adhesive layer is provided with a first through hole to expose the first source pad, the first gate pad and the first drain pad;
a fan-out wiring layer formed on the first encapsulation glue layer, the fan-out wiring layer including: the source electrode inner island is communicated with the first source electrode pad through a through hole, the gate electrode line is communicated with the first gate electrode pad through the through hole, and the drain electrode line is communicated with the first drain electrode pad through the through hole;
the MOSFET chip is arranged on the source inner island, so that a drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad, and a second source pad and a second gate pad are arranged on the front surface of the MOSFET chip;
a second packaging adhesive layer formed on the first packaging adhesive layer and the fan-out circuit layer, wherein the second packaging adhesive layer has a second molding height on the MOSFET chip, and the second packaging adhesive layer is provided with a second through hole to expose the second source pad and the second gate pad;
a metal island layer formed on the second encapsulation glue layer, the metal island layer comprising: the through hole is communicated with and interconnects the second source electrode pad and the source electrode outer island of the gate electrode circuit, the gate electrode island communicated to the second gate electrode pad through the through hole and the drain electrode island communicated to the fan-out end of the drain electrode circuit through the through hole;
with the gate island being turned on or off within the positive and negative voltage working range of the MOSFET chip, the potential of the first source pad of the gallium nitride HEMT chip can be synchronously turned down or turned up so as to synchronously turn on or turn off the gallium nitride HEMT chip.
2. The integrated package structure of gallium nitride HEMT chip according to claim 1, wherein the turn-off voltage of the first drain pad of the gallium nitride HEMT chip is between 100-600V through the drain island, the turn-off voltage and the turn-on voltage of the first gate pad of the gallium nitride HEMT chip are both less than 0V by short-circuiting the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip through the outer source island, and the voltage of the first source pad of the gallium nitride HEMT chip is passively raised when the source and the drain of the MOSFET chip are turned off through the gate island, and the voltage of the first gate pad of the gallium nitride HEMT chip is not more than 0V to turn on the gallium nitride HEMT chip.
3. The integrated package structure of gallium nitride HEMT chip of claim 1, wherein the turn-off operating voltage of the gate island is ≦ 0V, the turn-on operating voltage of the gate island is 3-20V, and a Schottky diode is further disposed in the MOSFET chip in a reverse direction.
4. The gallium nitride HEMT chip integrated package structure of any one of claims 1-3, wherein the source inner island is relatively offset from the gallium nitride HEMT chip and has a larger size than the first source pad, and the source inner island has a larger size and a profile corresponding to the backside of the MOSFET chip such that the drain layer is substantially bonded to the source inner island.
5. The integrated package structure of GaN HEMT chip of claim 4, wherein the outer source island is relatively offset and larger than the inner source island, and the through hole of the first package glue layer electrically connected to the outer source island corresponds to the through hole of the second package glue layer in a through manner so as to shorten the conduction path to less than 100um, and the package internal resistance of the integrated package structure of GaN HEMT chip is less than 0.2 milliohm.
6. A gallium nitride HEMT chip integration packaging structure comprises: the FOPLP circuit structure is characterized by comprising an inner source island and an outer source island, wherein the inner source island is positioned in the FOPLP packaging adhesive layer and is connected with a source electrode of the gallium nitride HEMT chip and a drain electrode of the MOSFET chip in an interlayer mode, the outer source island is positioned on one surface of the FOPLP packaging adhesive layer and is short-circuited with a grid electrode of the gallium nitride HEMT chip and a source electrode of the MOSFET chip in a long and short through hole mode.
7. The integrated package structure of GaN HEMT chip of claim 6, wherein the FOPLP circuit structure further comprises a drain island and a gate island on the same surface of the FOPLP package glue layer, the drain island is originally connected to the drain of the GaN HEMT chip, and the gate island is originally connected to the gate of the MOSFET chip.
8. A manufacturing method of a gallium nitride HEMT chip integrated packaging structure is characterized by comprising the following steps:
providing a heat dissipation slide;
arranging a gallium nitride HEMT chip on the heat dissipation carrier, so that the back surface of the gallium nitride HEMT chip is thermally coupled to the heat dissipation carrier, and the front surface of the gallium nitride HEMT chip is provided with a first source pad, a first gate pad and a first drain pad;
forming a first packaging adhesive layer on the heat dissipation chip in a flat plate molding manner to seal the gallium nitride HEMT chip, wherein the first packaging adhesive layer has a first molding height on the gallium nitride HEMT chip, and a first through hole is formed in the first packaging adhesive layer to expose the first source pad, the first gate pad and the first drain pad;
forming a fan-out wiring layer on the first encapsulation glue layer, the fan-out wiring layer comprising: the source electrode inner island is communicated with the first source electrode pad through a through hole, the gate electrode line is communicated with the first gate electrode pad through the through hole, and the drain electrode line is communicated with the first drain electrode pad through the through hole;
arranging an MOSFET chip on the source inner island, so that a drain layer on the back surface of the MOSFET chip is electrically connected with the first source pad, and a second source pad and a second gate pad are arranged on the front surface of the MOSFET chip;
forming a second packaging adhesive layer on the first packaging adhesive layer and the fan-out circuit layer in a flat plate molding manner, wherein the second packaging adhesive layer has a second molding height on the MOSFET chip, and a second through hole is formed in the second packaging adhesive layer so as to expose the second source pad and the second gate pad;
forming a metal island layer on the second encapsulation glue layer, wherein the metal island layer comprises: the through hole is communicated with and interconnected with the second source electrode pad and the source electrode outer island of the gate electrode circuit, the gate electrode island communicated to the second gate electrode pad through the through hole and the drain electrode island communicated to the fan-out end of the drain electrode circuit through the through hole.
9. The method for manufacturing the integrated package structure of the gallium nitride HEMT chip according to claim 8, wherein:
in the step of forming the metal island layer, the outer source island is configured between the drain island and the gate island;
or/and in the step of forming the first packaging adhesive layer in a flat plate molding manner, the first packaging adhesive layer also covers the peripheral side edges of the heat dissipation slide glass;
or/and in the step of forming the fan-out line layer, the source inner island is relatively deviated from the gallium nitride HEMT chip and has a larger size than the first source pad, and the size of the source inner island is larger than and the outline of the source inner island corresponds to the back surface of the MOSFET chip;
or/and, in the step of disposing the MOSFET chip on the source inner island, the drain layer is fully and substantially bonded to the source inner island;
or/and, in the step of forming the metal island layer, the source outer island is relatively deviated and has a size larger than that of the source inner island, and the through hole of the first packaging adhesive layer electrically connected with the source outer island corresponds to the through hole of the second packaging adhesive layer in a through way, so as to shorten the conduction path to be less than 100um, and further enable the packaging internal resistance of the gallium nitride HEMT chip integrated packaging structure to be controlled to be less than 0.2 milliohm;
or/and the manufacturing method further comprises a step of packaging and separating to obtain a separated gallium nitride HEMT chip integrated packaging structure, wherein the turn-off working voltage of the first drain pad of the gallium nitride HEMT chip is between 100 and 600V through the drain island, the first gate pad of the gallium nitride HEMT chip and the second source pad of the MOSFET chip are in short circuit through the source outer island, the turn-off and turn-on working voltages of the first gate pad of the gallium nitride HEMT chip are both less than 0V, when the MOSFET chip is in source and drain turn-off, the voltage of the first source pad of the gallium nitride HEMT chip is passively raised, the voltage of the first gate pad of the gallium nitride HEMT chip is not more than 0V, preferably, the turn-off working voltage of the gate island is less than 0V, the turn-on working voltage of the gate island is 3-20V, and a Schottky diode is arranged in the MOSFET chip in a reverse direction.
10. An electronic device, comprising: the integrated package structure comprises a printed circuit board and the gallium nitride HEMT chip, wherein the gallium nitride HEMT chip is jointed on the printed circuit board, the outer source island, the gate island and the drain island which are positioned on the same surface in the package bottom surface of the integrated package structure are respectively welded to corresponding pins of the printed circuit board, the heat dissipation slide or the back surface of the gallium nitride HEMT chip is exposed in the package top surface of the integrated package structure, the back surface of the MOSFET chip is not directly thermally coupled with the gallium nitride HEMT chip under the obstruction of a package adhesive layer, and the horizontal electric connection path between the drain electrode of the MOSFET chip and the source electrode of the gallium nitride HEMT chip does not exceed the projection area of the MOSFET chip on the package top surface.
CN202110903905.XA 2021-08-06 2021-08-06 Gallium nitride HEMT chip integration packaging structure and manufacturing method thereof Pending CN113629016A (en)

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US20150130071A1 (en) * 2013-11-12 2015-05-14 Infineon Technologies Ag Semiconductor Package Comprising a Transistor Chip Module and a Driver Chip Module and a Method for Fabricating the Same
DE102015115999A1 (en) * 2014-09-23 2016-03-24 Infineon Technologies Ag Electronic component
FR3059155A1 (en) * 2016-11-23 2018-05-25 Exagan INTEGRATED CIRCUIT SHAPED WITH A STACK OF TWO CHIPS CONNECTED IN SERIES
US20210013138A1 (en) * 2019-07-08 2021-01-14 Texas Instruments Incorporated Stacked die semiconductor package
CN215815838U (en) * 2021-08-06 2022-02-11 深圳真茂佳半导体有限公司 Gallium nitride HEMT chip integration packaging structure and electronic device

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WO2023082204A1 (en) * 2021-11-12 2023-05-19 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same
CN116544228A (en) * 2023-07-06 2023-08-04 广东致能科技有限公司 Wafer-level cascode device, chip and preparation method thereof

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