JP7137955B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7137955B2 JP7137955B2 JP2018072984A JP2018072984A JP7137955B2 JP 7137955 B2 JP7137955 B2 JP 7137955B2 JP 2018072984 A JP2018072984 A JP 2018072984A JP 2018072984 A JP2018072984 A JP 2018072984A JP 7137955 B2 JP7137955 B2 JP 7137955B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- lead
- terminal portion
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
11 :半導体素子
11a :素子主面
11b :素子裏面
111 :ゲート電極
112 :ソース電極
113 :ドレイン電極
12 :半導体素子
12a :素子主面
12b :素子裏面
121 :ゲート電極
122 :ソース電極
123 :ドレイン電極
13 :半導体素子
13a :素子主面
13b :素子裏面
131 :アノード電極
132 :カソード電極
2 :封止樹脂
21 :樹脂主面
22 :樹脂裏面
23 :樹脂側面
231 :第1樹脂側面
232 :第2樹脂側面
30 :リードフレーム
31 :第1リード
31a :第1先端面
31b :第1露出裏面
311 :第1ボンディングパッド部
312 :第1端子部
313 :第1連結部
32 :第2リード
32a :第2先端面
32b :第2露出裏面
321 :第2ボンディングパッド部
322 :第2端子部
323 :第2連結部
323a :貫通孔
324 :クリップボンディング部
325 :側方延出部
33 :第3リード
33a :第3先端面
33b :第3露出裏面
33c :側方先端面
331 :第3ボンディングパッド部
332,332a,332b:第3端子部
333 :第3連結部
334 :側方延出部
34 :第4リード
34a :第4先端面
34b :第4露出裏面
341 :第4ボンディングパッド部
342 :第4端子部
343 :第4連結部
35 :第5リード
35a :第5先端面
35b :第5露出裏面
351 :第5ボンディングパッド部
352 :第5端子部
353 :第5連結部
39 :窪み
41 :ボンディングワイヤ
42 :ボンディングリボン
43 :導電性接合材
44 :ストラップ部材
441 :導電性接合材
45 :導電性接合材
Claims (13)
- 厚さ方向において互いに反対側を向く素子主面および素子裏面を有し、前記素子主面に第1電極および第2電極が形成された半導体素子と、
各々が前記半導体素子に導通する複数のリードと、
前記厚さ方向に直交する第1方向において互いに反対側を向く第1樹脂側面および第2樹脂側面を有し、前記複数のリードの一部ずつおよび前記半導体素子を覆う封止樹脂と、
前記封止樹脂に覆われており、第4電極および第5電極が形成された第2の半導体素子と、
を備えており、
前記複数のリードは、前記第1電極に導通する第1リードおよび前記第2電極に導通する第2リードを含み、
前記第1リードは、前記第1樹脂側面から露出する第1実装部を含んでおり、
前記第2リードは、前記第1樹脂側面から露出する第2実装部を含んでおり、
前記第2実装部は、前記厚さ方向および前記第1方向に直交する第2方向において、前記第1実装部に並び、かつ、前記第1実装部よりも前記第2方向の寸法が大きく、
前記半導体素子には、前記素子裏面に第3電極が形成されており、
前記複数のリードは、さらに前記第3電極に導通する第3リードを含み、
前記第3リードは、前記第2樹脂側面から露出する第3実装部を含んでおり、
前記第1電極と前記第4電極とは、前記第2リードを介して電気的に接続され、
前記第3電極と前記第5電極とは、前記第3リードを介して電気的に接続される、
ことを特徴とする半導体装置。 - 前記第2実装部は、前記封止樹脂の前記第1方向の中央を繋ぐ線分の延長線に交わる、請求項1に記載の半導体装置。
- 前記封止樹脂の前記第2方向の寸法に対する、前記第1実装部と前記第2実装部との離間距離の割合は、0.08以上である、
請求項1または請求項2に記載の半導体装置。 - 前記割合は、0.35以下である、
請求項3に記載の半導体装置。 - 前記第1実装部は、前記厚さ方向から見て、前記第1樹脂側面から突き出ており、
前記第2実装部は、前記厚さ方向から見て、前記第1樹脂側面から突き出ている、
請求項1ないし請求項4のいずれか一項に記載の半導体装置。 - 前記第1実装部および前記第2実装部はともに、前記第1樹脂側面が向く方向と同じ方向を向く端面が、前記厚さ方向から見て窪んでいる、
請求項5に記載の半導体装置。 - 前記第1実装部および前記第2実装部はともに、前記第1樹脂側面に近い基端部分の前記厚さ方向の寸法が、先端部分の前記厚さ方向の寸法よりも大きい、
請求項5または請求項6に記載の半導体装置。 - 前記第2実装部は、前記厚さ方向に貫通した貫通孔を有する、
請求項5ないし請求項7のいずれか一項に記載の半導体装置。 - 前記第3実装部は、互いに離間した第1露出部および第2露出部を含んでおり、
前記第2露出部は、前記第2方向において前記第1露出部に並び、かつ、前記第1露出部よりも前記第2方向の寸法が大きい、
請求項1ないし請求項8のいずれか一項に記載の半導体装置。 - 前記第1樹脂側面のうち前記第1実装部と前記第2実装部とに挟まれた領域と、前記第2樹脂側面のうち前記第1露出部と前記第2露出部とに挟まれた領域とが、前記第1方向から見て重なる、
請求項9に記載の半導体装置。 - 前記第3実装部は、前記厚さ方向から見て、前記第2樹脂側面から突き出ている、
請求項1ないし請求項10のいずれか一項に記載の半導体装置。 - 前記半導体素子は、パワーMOSFETであり、
前記第1電極は、ソース電極であり、
前記第2電極は、ゲート電極であり、
前記第3電極は、ドレイン電極である、
請求項1ないし請求項11のいずれか一項に記載の半導体装置。 - 前記第2の半導体素子は、ダイオードであり、
前記第4電極は、アノード電極であり、
前記第5電極は、カソード電極である、
請求項1ないし請求項12のいずれか一項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018072984A JP7137955B2 (ja) | 2018-04-05 | 2018-04-05 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018072984A JP7137955B2 (ja) | 2018-04-05 | 2018-04-05 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019186321A JP2019186321A (ja) | 2019-10-24 |
JP7137955B2 true JP7137955B2 (ja) | 2022-09-15 |
Family
ID=68337446
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018072984A Active JP7137955B2 (ja) | 2018-04-05 | 2018-04-05 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP7137955B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112021000700T5 (de) * | 2020-04-01 | 2022-11-17 | Rohm Co., Ltd. | Elektronische vorrichtung |
CN115769351A (zh) * | 2020-07-13 | 2023-03-07 | 罗姆股份有限公司 | 半导体装置以及半导体装置的制造方法 |
DE112022002587T5 (de) * | 2021-06-07 | 2024-03-07 | Rohm Co., Ltd. | Halbleiterbauelement |
IT202200009839A1 (it) * | 2022-05-12 | 2023-11-12 | St Microelectronics Srl | Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000269395A (ja) | 1999-03-18 | 2000-09-29 | Toshiba Corp | 半導体装置 |
US20060017141A1 (en) | 2004-07-20 | 2006-01-26 | Leeshawn Luo | Power semiconductor package |
JP2008294384A (ja) | 2007-04-27 | 2008-12-04 | Renesas Technology Corp | 半導体装置 |
US20090057869A1 (en) | 2007-08-31 | 2009-03-05 | Alpha & Omega Semiconductor, Ltd. | Co-packaged high-side and low-side nmosfets for efficient dc-dc power conversion |
JP2009278103A5 (ja) | 2009-05-13 | 2012-06-28 | ||
JP2013051324A (ja) | 2011-08-31 | 2013-03-14 | Shindengen Electric Mfg Co Ltd | リードフレーム、半導体装置及びその製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6355551U (ja) * | 1986-09-29 | 1988-04-14 | ||
JPH0832010A (ja) * | 1994-07-15 | 1996-02-02 | Hitachi Ltd | 電子部品及びそれを実装した配線基板を着脱可能に支持する支持装置 |
US8358017B2 (en) | 2008-05-15 | 2013-01-22 | Gem Services, Inc. | Semiconductor package featuring flip-chip die sandwiched between metal layers |
-
2018
- 2018-04-05 JP JP2018072984A patent/JP7137955B2/ja active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000269395A (ja) | 1999-03-18 | 2000-09-29 | Toshiba Corp | 半導体装置 |
US20060017141A1 (en) | 2004-07-20 | 2006-01-26 | Leeshawn Luo | Power semiconductor package |
JP2008294384A (ja) | 2007-04-27 | 2008-12-04 | Renesas Technology Corp | 半導体装置 |
US20090057869A1 (en) | 2007-08-31 | 2009-03-05 | Alpha & Omega Semiconductor, Ltd. | Co-packaged high-side and low-side nmosfets for efficient dc-dc power conversion |
JP2009278103A5 (ja) | 2009-05-13 | 2012-06-28 | ||
JP2013051324A (ja) | 2011-08-31 | 2013-03-14 | Shindengen Electric Mfg Co Ltd | リードフレーム、半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2019186321A (ja) | 2019-10-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7137955B2 (ja) | 半導体装置 | |
US9899299B2 (en) | Semiconductor device | |
JP5176507B2 (ja) | 半導体装置 | |
US8704342B2 (en) | Resin sealing type semiconductor device and method of manufacturing the same, and lead frame | |
JP7150461B2 (ja) | 半導体装置 | |
JP2023015278A (ja) | 半導体装置 | |
US11742279B2 (en) | Semiconductor device | |
JP2021158317A (ja) | 半導体装置 | |
CN108232001A (zh) | 霍尔元件模块 | |
JP7144112B2 (ja) | 半導体装置 | |
JP2022143167A (ja) | 半導体装置 | |
JP5533983B2 (ja) | 半導体装置 | |
CN107331767B (zh) | 半导体器件 | |
WO2023100754A1 (ja) | 半導体装置 | |
WO2022209663A1 (ja) | 半導体装置 | |
WO2023140046A1 (ja) | 半導体装置 | |
JP2023042910A (ja) | 電子装置 | |
JP2022146271A (ja) | 半導体装置 | |
JP2022146269A (ja) | 半導体装置 | |
JP2022143168A (ja) | 半導体装置 | |
JP6254807B2 (ja) | 半導体装置および電子機器 | |
CN115315822A (zh) | 半导体器件 | |
JP2007027405A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210324 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220215 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20220217 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220411 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220823 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220905 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7137955 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |