JP5924110B2 - 半導体装置、半導体装置モジュールおよび半導体装置の製造方法 - Google Patents
半導体装置、半導体装置モジュールおよび半導体装置の製造方法 Download PDFInfo
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- JP5924110B2 JP5924110B2 JP2012110099A JP2012110099A JP5924110B2 JP 5924110 B2 JP5924110 B2 JP 5924110B2 JP 2012110099 A JP2012110099 A JP 2012110099A JP 2012110099 A JP2012110099 A JP 2012110099A JP 5924110 B2 JP5924110 B2 JP 5924110B2
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- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/30—Technical effects
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- H01L2924/30107—Inductance
Description
下記特許文献3には、高出力半導体素子の上面に接する放熱用部材を設けるとともに、下面に信号用バンプと同じ大きさの放熱用のダミーバンプを設けることにより、高出力半導体素子の上下両面からの放熱を行っている。
下記特許文献4には、配線基板の開口内に配設され絶縁層により封止されたチップの下面の端子を、該絶縁層内の配線を介して、パッケージの下面に表出させたものが開示されている。
下記特許文献5には、封止樹脂内に第1及び第2のチップを配設し、下側のチップ下面の電極を、樹脂に埋め込まれたリードを介してパッケージ下面に表出する端子に接続している。
次に、図4を参照して、第1の実施の形態の半導体装置1および半導体装置モジュール101について説明する。半導体装置1は、GaNチップ10と、制御チップ40と、リードフレーム50と、封止樹脂70とを備えている。GaNチップ10と制御チップ40とが1パッケージ化されている。半導体装置モジュール101は、半導体装置1と、マザーボード80とを備えている。マザーボード80は配線基板の一例である。
次に、図5を参照して、第2の実施の形態の半導体装置2および半導体装置モジュール102について説明する。
次に、図6を参照して、第3の実施の形態の半導体装置3および半導体装置モジュール103について説明する。
次に、図14、15を参照して、第4の実施の形態の半導体装置4および半導体装置モジュール104について説明する。半導体装置4は、GaNチップ10と、制御チップ40と、インターポーザ(薄型配線基板)90と、封止樹脂70とを備えている。GaNチップ10と制御チップ40とが1パッケージ化されている。半導体装置モジュール104は、半導体装置4と、マザーボード80とを備えている。インターポーザ90は中継基板の一例である。マザーボード80は配線基板の一例である。
前記第1の半導体素子は、高出力半導体素子または高周波半導体素子である請求項1〜7のいずれか一項に記載の半導体装置。
前記第1の半導体素子は、高周波高出力半導体素子である付記1記載の半導体装置。
前記第1の半導体素子は、窒化ガリウム系高周波高出力半導体素子である付記2記載の半導体装置。
前記第1の半導体素子は、AlGaNとGaNとのヘテロ接合を備える窒化ガリウム系高周波高出力半導体素子である付記3記載の半導体装置。
前記第2の半導体素子は、前記第1の半導体素子の動作を制御する制御用半導体素子である請求項1〜7および付記1〜4のいずれかに記載の半導体装置。
前記第1の外部接続端子は、突起電極である請求項1〜7および付記1〜5のいずれかに記載の半導体装置。
前記突起電極は、バンプまたはボールである付記6記載の半導体装置。
前記第2の半導体素子と第2の外部接続端子はワイヤで接続されている請求項1〜7および付記1〜7のいずれかに記載の半導体装置。
前記半導体装置は、QFP型である請求項1〜5のいずれかに記載の半導体装置。
前記半導体装置は、DIP型である請求項1〜5のいずれかに記載の半導体装置。
前記半導体装置は、QFN型である請求項1〜5のいずれかに記載の半導体装置。
前記半導体装置は、BGAである請求項1〜3、6および7のいずれかに記載の半導体装置。
10 GaNチップ
11 GaN基板
12 ソース電極
13 ドレイン電極
14 ゲート電極
15 SiO2膜
16 有機保護膜
17、18、19 貫通孔
20 表面
21 裏面
22、23、24 半田バンプ
25、26、27 Cu電極
31 樹脂封止層
32、33、34 Cuポスト
35、36、37 半田ボール
40 制御チップ
41 端子
42、43 外部接続副端子
44 外部接続制御端子
42s、43s、44s 下面
45 外部接続端子
47 裏面
50 リードフレーム
51 ダイステージ
52 下面
53 上面
54、55 リード端子
55s 下面
64 接着剤
65、66 ダイボンディング材
65‘ 導電ペーストもしくは半田
67、69 半田
68 ボンディングワイヤ
70 封止樹脂
71 裏面
80 マザーボード
81 基板
82、85 配線
83 上面
90 インターポーザ
91 樹脂基板
93 半田ボール
92 端子
94 裏面
95 表面
96 開口
101、102、103、104 半導体装置モジュール
Claims (5)
- 第1の電極と、第2の電極と、前記第1の電極と前記第2の電極との間を流れる電流を制御する制御電極と、を第1の面に有する第1の半導体素子と、
前記第1の電極、前記第2の電極および前記制御電極の各々の直下に設けられ且つ前記第1の電極、前記第2の電極および前記制御電極の各々に接続された突起電極と、
前記第1の半導体素子の前記第1の面とは反対側の第2の面の全体が接合されたダイステージと、前記突起電極が延在する面内に接続部を有する複数のリードを含み、前記複数のリードのうちの少なくとも1つが前記ダイステージに直結されたリードフレームと、
前記ダイステージの前記第1の半導体素子が接合された面とは反対側の面に接合され、前記複数のリードのいずれかに接続された第2の半導体素子と、
前記突起電極および前記複数のリードの前記接続部を露出させるように前記第1の半導体素子および前記第2の半導体素子を封止する封止部材と、
を備える半導体装置。 - 前記第1の電極および前記第2の電極は、前記制御電極よりも大きい
請求項1記載の半導体装置。 - 請求項1または請求項2に記載の半導体装置と、前記突起電極および前記複数のリードの各々に接続された配線基板と、を備える半導体装置モジュール。
- 前記第2の半導体素子は、前記第1の半導体素子の動作を制御する制御用半導体素子であり、前記制御電極は、前記リードフレームの前記リードおよび前記配線基板の配線を介して前記第2の半導体素子に接続されている
請求項3記載の半導体装置モジュール。 - 第1の電極と、第2の電極と、前記第1の電極と前記第2の電極との間を流れる電流を制御する制御電極と、を第1の面に有する第1の半導体素子と、前記第1の電極、前記第2の電極および前記制御電極の各々の直下に設けられ且つ前記第1の電極、前記第2の電極および前記制御電極の各々に接続された突起電極と、前記第1の半導体素子の前記第1の面とは反対側の第2の面の全体が接合されたダイステージと、前記突起電極が延在する面内に接続部を有する複数のリードを含み、前記複数のリードのうちの少なくとも1つが前記ダイステージに直結されたリードフレームと、前記ダイステージの前記第1の半導体素子が接合された面とは反対側の面に接合され、前記複数のリードのいずれかに接続された第2の半導体素子と、を備える組立体を準備する工程と、
前記突起電極を保護シートで覆った状態で、少なくとも前記第1の半導体素子および前記第2の半導体素子を封止部材で封止する工程と、
前記保護シートを剥がして、前記突起電極を露出させる工程と、
を備える半導体装置の製造方法。
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US13/849,248 US9041186B2 (en) | 2012-05-11 | 2013-03-22 | Encapsulated semiconductor chips with wiring including controlling chip and method of making the same |
CN201310150913.7A CN103390612B (zh) | 2012-05-11 | 2013-04-26 | 半导体器件、半导体器件模块以及半导体器件的制造方法 |
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