JP4332567B2 - 半導体装置の製造方法及び実装方法 - Google Patents

半導体装置の製造方法及び実装方法 Download PDF

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JP4332567B2
JP4332567B2 JP2007081852A JP2007081852A JP4332567B2 JP 4332567 B2 JP4332567 B2 JP 4332567B2 JP 2007081852 A JP2007081852 A JP 2007081852A JP 2007081852 A JP2007081852 A JP 2007081852A JP 4332567 B2 JP4332567 B2 JP 4332567B2
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wiring board
semiconductor device
opening
relay
relay wiring
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JP2008244104A (ja
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誠 照井
靖 白石
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Lapis Semiconductor Co Ltd
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Oki Semiconductor Co Ltd
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Priority to JP2007081852A priority Critical patent/JP4332567B2/ja
Priority to US12/052,074 priority patent/US7932597B2/en
Publication of JP2008244104A publication Critical patent/JP2008244104A/ja
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Publication of JP4332567B2 publication Critical patent/JP4332567B2/ja
Priority to US13/071,741 priority patent/US8409930B2/en
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Description

本発明は、中継配線基板（インターポーザ）を用いて複数の半導体チップを１つのパッケージに搭載した半導体装置の製造方法及び実装方法に関するものである。
図２は、下記特許文献１に記載された従来の半導体装置の構成図である。
この半導体装置は、下段の半導体素子１０１，１０２が、その回路面が多層回路基板２００に向き合うようにフェイスダウン実装され、上段の半導体素子１０３が２つの半導体素子１０１，１０２にまたがって搭載されている。半導体素子１０３は、回路面が半導体素子１０１，１０２と向き合うようにフェイスダウン実装されている。
半導体素子１０１は、そのパッド１１１に形成された金バンプ１２１で、多層回路基板２００の１次側パッド２１１に電気的に接続されている。半導体素子１０１と多層回路基板２００の間には、接着樹脂４０１が介在している。なお、半導体素子１０２も、半導体素子１０１と同様にして、多層回路基板２００と接続されている。
一方、半導体素子１０３の回路面に形成されたパッド１１３は、テープ配線３０１、ボンディング・ワイヤ３０２を介して、多層回路基板２００の表面に形成された１次側パッド２１３に電気的に接続されている。テープ配線３０１と半導体素子１０１，１０２とは、絶縁層４０２によって電気的に絶縁されている。
多層回路基板２００の各１次パッド２１１，２１３は、それぞれスルーホールを介してこの多層回路基板２００の裏面に設けられた２次側パッド２４１，２４３に接続され、この２次側パッド２４１，２４３に外部端子２６１，２６３が設けられている。
多層回路基板２００の半導体素子搭載面側は樹脂４０８で封止され、半導体素子１０３の裏面に熱伝導性接着材４０９を介して金属製の放熱板４１０が搭載されている。
このような積層型の半導体装置によれば、発熱量の多い半導体素子１０３の発熱を放熱板４１０で効率よく拡散でき、筐体等への放熱にも適しているとされている。
特開２００３−７８１０４号公報
しかしながら、従来の半導体装置の製造方法及び実装方法では、半導体素子１０３の裏面に設けた放熱板４１０によって、この半導体素子１０３の発熱を放散することはできるが、内部の半導体素子１０１，１０２の発熱を放散することはできない。このため、場合によっては放熱効果が十分ではなく、内部の半導体素子１０１，１０２が高温になり、誤動作を生じるおそれがあった。
本発明は、中継配線基板を用いて複数の半導体チップを1つのパッケージに搭載した半導体装置における放熱効果の向上を目的としている。
本発明の半導体装置の製造方法は、中継配線基板に複数の半導体チップをフリップチップ接続で搭載する処理と、前記中継配線基板を収容する開口部を有し、該中継配線基板から表面に設けられた外部端子までの配線を行う主配線基板の裏面に放熱板を貼り付ける処理と、前記複数の半導体チップが搭載された中継配線基板を前記主配線基板の開口部に収容し、前記放熱板に熱伝導性を有する接着材で接着する処理と、前記中継配線基板と前記主配線基板の間をボンディング・ワイヤで配線する処理と、前記複数の半導体チップの裏面に熱伝導材を塗布する処理と、前記熱伝導材を介して前記複数の半導体チップと接続するように、金属製の封止板で前記主配線基板の開口部を覆う処理とを、順次行うことを特徴とする。
本発明の他の半導体装置の製造方法は、中継配線基板に複数の半導体チップをフリップチップ接続で搭載する処理と、前記中継配線基板を収容する開口部を有し、該中継配線基板から表面に設けられた外部端子までの配線を行う主配線基板の裏面に放熱板を貼り付ける処理と、前記複数の半導体チップが搭載された中継配線基板を前記主配線基板の開口部に収容し、前記放熱板に熱伝導性を有する接着材で接着する処理と、前記中継配線基板と前記主配線基板の間をボンディング・ワイヤで配線する処理と、前記主配線基板の開口部に樹脂またはオイルの熱伝導材を充填する処理と、金属製の封止板で前記主配線基板の開口部を覆う処理とを、順次行うことを特徴とする。
本発明の半導体装置の実装方法は、前記発明の半導体装置の製造方法により製造された半導体装置を、前記外部端子を実装基板の表面に設けられた配線パターンに接続すると共に前記金属製の封止板を該実装基板の表面に設けられたアース配線に半田を介して接続することにより、該実装基板に実装することを特徴とする。
本発明では、裏面に放熱板が貼り付けられ、表面には中継配線基板を収容する開口部を覆う金属製の封止板が被せられた主配線基板を有し、中継配線基板が放熱板に熱伝導性の接着材で接着され、この中継配線基板にフリップチップ接続された複数の半導体チップが熱伝導材を介して封止板に接続されている。
これにより、半導体チップで発生した熱は、中継配線基板を介して放熱板に伝導されて外部へ放射される。更に、半導体チップで発生した熱は、熱伝導材を介して金属性の封止板に伝導される。従って、封止板を実装基板に半田付けしておけば、半導体チップで発生した熱は、この封止板から半田を介して実装基板のアース配線等へ伝導されて拡散される。このため、ＢＧＡ基板等の主配線基板の裏面のみに放熱板を設けた従来の半導体装置に比べて、放熱効果が向上するという効果がある。
この発明の前記並びにその他の目的と新規な特徴は、次の好ましい実施例の説明を添付図面と照らし合わせて読むと、より完全に明らかになるであろう。但し、図面は、もっぱら解説のためのものであって、この発明の範囲を限定するものではない。
図１は、本発明の実施例１を示す半導体装置の構成図である。
この半導体装置は、ＡＳＩＣ(Application Specified IC)やマイクロコントローラ等の制御用ＬＳＩとメモリ等の汎用ＬＳＩを組み合わせて１つのパッケージにまとめたＳＩＰ(System in Package)構造の半導体装置である。
この半導体装置は、ＡＳＩＣチップ１ａとメモリチップ１ｂを搭載してこれらのチップ間の配線を行う中継配線基板２を有している。一般に、ＡＳＩＣチップ１ａは発熱量が多く、メモリチップ１ｂはＡＳＩＣチップ１ａと比較して熱に弱いことが知られている。中継配線基板２は、シリコン基板に配線ピッチ１００μｍ以下のアルミ配線を形成したものである。中継配線基板２のアルミ配線の上には、直径５０μｍ以下のマイクロバンプ３が形成されたＡＳＩＣチップ１ａとメモリチップ１ｂが、フリップチップ接続技術で搭載されている。そして、フリップチップ接続されたＡＳＩＣチップ１ａ及びメモリチップ１ｂと中継配線基板２の間には、アンダーフィル樹脂４が充填されている。
一方、パッケージの主要部で、中継配線基板２から外部端子までの配線を行う主配線基板は、ＢＧＡ(Ball Grid Array)基板１０となっている。ＢＧＡ基板１０は、複数の配線層を絶縁性の樹脂層を介して多層化した配線基板で、実装基板２０に接続するための球状の外部端子１１を、格子の交差箇所に対応するように規則的に配置したものである。ＢＧＡ基板１０の中央部には、中継配線基板２が丁度収まるような開口部Ｈが設けられている。開口部Ｈの周囲には段差部Ｓが形成され、この段差部Ｓに各外部端子１１に接続する図示しない配線の一端が引き出されている。
ＢＧＡ基板１０の裏面（外部端子１１が設けられていない面）には、この裏面全体を覆うように、高熱伝導率を有する銅等の金属製の放熱板５が貼り付けられている。また、ＢＧＡ基板１０の開口部Ｈに対応する放熱板５の内側には、接着剤６によって中継配線基板２の裏面が実装されている。そして、中継配線基板２の周辺部に引き出されたアルミ電極と、ＢＧＡ基板１０の段差部Ｓに引き出された配線の間が、ボンディング・ワイヤ７によって電気的に接続されている。
ＡＳＩＣチップ１ａとメモリチップ１ｂが搭載された中継配線基板２が実装されたＢＧＡ基板１０の開口部Ｈは、金属キャップ８で封止されている。このとき、ＡＳＩＣチップ１ａ及びメモリチップ１ｂの裏面と金属キャップ８の間には、絶縁性を有する熱伝導グリスや熱伝導ゲル等の熱伝導材９が充填されている。
この半導体装置を実装基板に搭載する場合、外部端子１１を実装基板２０の表面に設けられた配線パターン２１に接続すると共に、金属キャップ８を、この実装基板２０に設けられたアース配線２２等に半田２３等で接続する。
図３は、図１の半導体装置の製造方法を示す概略の工程図である。以下、図３を参照しつつ、図１の半導体装置の製造方法を説明する。なお、この図３と図１では、半導体装置の向き（上下）が逆になっている。
（１） 工程１
中継配線基板２の上に、マイクロバンプ３を用いてＡＳＩＣチップ１ａとメモリチップ１ｂをフリップチップ接続する（図３ａ）。
（２） 工程２
フリップチップ接続したＡＳＩＣチップ１ａ及びメモリチップ１ｂと中継配線基板２の間に、アンダーフィル樹脂４を充填する（図３ｂ）。
（３） 工程３
中央部に中継配線基板２が丁度収まるような開口部Ｈが設けられ、この開口部Ｈの周囲に設けられた段差部Ｓと表面の間に配線が施され、かつ裏面に放熱板５が貼り付けられたＢＧＡ基板１０を準備する。そして、このＢＧＡ基板１０の開口部Ｈの放熱板５の内側に、工程２で組み立てた中継配線基板２を、熱伝導性のある接着材６で接着して搭載する（図３ｃ）。
（４） 工程４
中継配線基板２の周辺部に引き出されたアルミ電極と、ＢＧＡ基板１０の段差部Ｓに引き出された配線の間を、ボンディング・ワイヤ７で電気的に接続する。更に、中継配線基板２にフリップチップ接続されたＡＳＩＣチップ１ａ及びメモリチップ１ｂの上に、熱伝導材９を適量塗布する（図３ｄ）。
（５） 工程５
ＢＧＡ基板１０の開口部Ｈを覆うように、金属キャップ８を被せ、周囲を接着する。このとき、金属キャップ８とＡＳＩＣチップ１ａ及びメモリチップ１ｂの間が、熱伝導材９で充填されるように、工程４で塗布する熱伝導材の量を設定しておく必要がある。
金属キャップ８で開口部Ｈを塞いだ後、ＢＧＡ基板１０の周辺部に半田ボール等の外部端子１１を搭載する。これにより、図３ｅに示すように、図１の半導体装置が完成する。
以上のように、この実施例１の半導体装置は、裏面全体に放熱板５が貼り付けられ、表面の中央部には中継配線基板２を収容する開口部Ｈを覆う金属キャップ８が被せられたＢＧＡ基板１０を有している。そして、中継配線基板２が放熱板５に熱伝導性の接着材６で接着され、この中継配線基板２にフリップチップ接続されたＡＳＩＣチップ１ａとメモリチップ１ｂが熱伝導材９を介して金属キャップ８に接続されている。
これにより、ＡＳＩＣチップ１ａとメモリチップ１ｂで発生した熱は、中継配線基板２を介して放熱板５に伝導され、外部へ放射される。更に、ＡＳＩＣチップ１ａとメモリチップ１ｂで発生した熱は、熱伝導材９を介して金属キャップ８に伝導され、この金属キャップ８から半田２３を介して実装基板のアース配線２２へ伝導されて拡散される。このため、ＢＧＡ基板の裏面のみに放熱板を設けた従来の半導体装置に比べて、放熱効果が向上するという利点がある。
図４は、本発明の実施例２を示す半導体装置の構成図であり、図１中の要素と共通の要素には共通の符号が付されている。
この半導体装置は、図１の半導体装置における熱伝導材９に代えて、ＢＧＡ基板１０の開口部Ｈに搭載された中継配線基板２全体を浸すように、絶縁性を有する高熱伝導性の樹脂またはオイル９Ａを充填したものである。
この半導体装置の製造方法は、実施例１における工程４で、ＡＳＩＣチップ１ａとメモリチップ１ｂの上に熱伝導材９を適量塗布する代わりに、これらのＡＳＩＣチップ１ａとメモリチップ１ｂが完全に浸るように開口部Ｈに高熱伝導性の樹脂またはオイル９Ａを充填することが相違するだけである。
以上のように、この実施例２の半導体装置は、裏面全体に放熱板５が貼り付けられ、表面の中央部には中継配線基板２を収容する開口部Ｈを覆う金属キャップ８が被せられたＢＧＡ基板１０を有している。そして、中継配線基板２が放熱板５に熱伝導性の接着材６で接着されると共に、開口部Ｈの中が高熱伝導性の樹脂またはオイル９Ａで充填されている。これにより、ＡＳＩＣチップ１ａとメモリチップ１ｂで発生した熱は、高熱伝導性の樹脂またはオイル９Ａによって半導体装置全体に均一に伝導され、放熱板５と金属キャップ８から効果的に放散することができるという利点がある。
なお、本発明は、上記実施例に限定されず、種々の変形が可能である。この変形例としては、例えば、次のようなものがある。
（１） 中継配線基板２に搭載する半導体チップは、ＡＳＩＣやメモリに限定されない。また、個数も２個に限定されない。
（２） パッケージの主要部としてＢＧＡ基板１０を使用した半導体装置を例示したが、パッケージの主配線基板はＢＧＡ基板に限定するものではない。
（３） 実施例２のように開口部Ｈに高熱伝導性の樹脂またはオイル９Ａを充填する場合は、フリップチップ接続したＡＳＩＣチップ１ａ及びメモリチップ１ｂと中継配線基板２の間に、アンダーフィル樹脂４を充填する必要は無い。
本発明の実施例１を示す半導体装置の構成図である。 従来の半導体装置の構成図である。 図１の半導体装置の製造方法を示す概略の工程図である。 本発明の実施例２を示す半導体装置の構成図である。
符号の説明
１ａ ＡＳＩＣチップ
１ｂ メモリチップ
２ 中継配線基板
３ マイクロバンプ
４ アンダーフィル樹脂
５ 放熱板
６ 接着材
７ ボンディング・ワイヤ
８ 金属キャップ
９ 熱伝導材
９Ａ 樹脂またはオイル
１０ ＢＧＡ基板
１１ 外部端子
Ｈ 開口部
Ｓ 段差部

Claims (6)

  1. 中継配線基板に複数の半導体チップをフリップチップ接続で搭載する処理と、
    前記中継配線基板を収容する開口部を有し、該中継配線基板から表面に設けられた外部端子までの配線を行う主配線基板の裏面に放熱板を貼り付ける処理と、
    前記複数の半導体チップが搭載された中継配線基板を前記主配線基板の開口部に収容し、前記放熱板に熱伝導性を有する接着材で接着する処理と、
    前記中継配線基板と前記主配線基板の間をボンディング・ワイヤで配線する処理と、
    前記複数の半導体チップの裏面に熱伝導材を塗布する処理と、
    前記熱伝導材を介して前記複数の半導体チップと接続するように、金属製の封止板で前記主配線基板の開口部を覆う処理とを、
    順次行うことを特徴とする半導体装置の製造方法。
  2. 中継配線基板に複数の半導体チップをフリップチップ接続で搭載する処理と、
    前記中継配線基板を収容する開口部を有し、該中継配線基板から表面に設けられた外部端子までの配線を行う主配線基板の裏面に放熱板を貼り付ける処理と、
    前記複数の半導体チップが搭載された中継配線基板を前記主配線基板の開口部に収容し、前記放熱板に熱伝導性を有する接着材で接着する処理と、
    前記中継配線基板と前記主配線基板の間をボンディング・ワイヤで配線する処理と、
    前記主配線基板の開口部に樹脂またはオイルの熱伝導材を充填する処理と、
    金属製の封止板で前記主配線基板の開口部を覆う処理とを、
    順次行うことを特徴とする半導体装置の製造方法。
  3. 前記主配線基板は、前記開口部内に該主配線基板の前記表面とは異なる高さの段差部を有し、かつ該段差部上には前記外部端子と電気的に接続する配線が形成されており、
    前記段差部上に形成された前記配線と前記中継配線基板とを、前記ボンディング・ワイヤにより電気的に接続することを特徴とする請求項１または２記載の半導体装置の製造方法。
  4. 前記中継配線基板は、表面に配線が形成されたシリコン基板であることを特徴とする請求項１〜３のいずれか１項に記載の半導体装置の製造方法。
  5. 前記複数の半導体チップは、２個の半導体チップであり、
    一方の半導体チップはＡＳＩＣチップであり、他方の半導体チップはメモリチップであることを特徴とする請求項１〜４のいずれか１項に記載の半導体装置の製造方法。
  6. 請求項１記載の半導体装置の製造方法により製造された半導体装置を、前記外部端子を実装基板の表面に設けられた配線パターンに接続すると共に前記金属製の封止板を該実装基板の表面に設けられたアース配線に半田を介して接続することにより、該実装基板に実装することを特徴とする半導体装置の実装方法。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010161184A (ja) * 2009-01-08 2010-07-22 Hitachi Ltd 半導体装置
US9013040B1 (en) * 2009-04-10 2015-04-21 Sanmina Corporation Memory device with die stacking and heat dissipation
TWI408310B (zh) * 2009-09-29 2013-09-11 Liang Meng Plastic Share Co Ltd 照明裝置及其製造方法
US8378480B2 (en) * 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
DE102010026344A1 (de) * 2010-07-07 2012-01-12 Osram Opto Semiconductors Gmbh Leuchtdiode
DE102010050395A1 (de) * 2010-11-03 2012-05-03 Emitec Gesellschaft Für Emissionstechnologie Mbh Thermoelektrisches Modul für einen thermoelektrischen Generator eines Fahrzeugs
JP2012109307A (ja) * 2010-11-15 2012-06-07 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
JP5924110B2 (ja) * 2012-05-11 2016-05-25 株式会社ソシオネクスト 半導体装置、半導体装置モジュールおよび半導体装置の製造方法
US10008475B2 (en) 2012-09-27 2018-06-26 Intel Corporation Stacked-die including a die in a package substrate
ES2716903T3 (es) 2013-08-08 2019-06-17 Intel Ip Corp Método, aparato y sistema para ajuste de inclinación hacia abajo eléctrica en un sistema de múltiple entrada múltiple salida
US9564958B2 (en) 2013-08-08 2017-02-07 Intel IP Corporation Power saving mode optimizations and related procedures
JP2015220291A (ja) * 2014-05-15 2015-12-07 株式会社ソシオネクスト 半導体装置及びその製造方法
US9609739B2 (en) 2015-03-10 2017-03-28 Kabushiki Kaisha Toshiba Electronic device
JP2017022352A (ja) 2015-07-15 2017-01-26 富士通株式会社 半導体装置
US9781819B2 (en) * 2015-07-31 2017-10-03 Laird Technologies, Inc. Multifunctional components for electronic devices and related methods of providing thermal management and board level shielding
JP2018037520A (ja) 2016-08-31 2018-03-08 富士通株式会社 半導体装置、電子装置、半導体装置の製造方法及び電子装置の製造方法
JP6880777B2 (ja) * 2017-01-27 2021-06-02 富士通株式会社 光モジュール
KR102566974B1 (ko) 2018-07-11 2023-08-16 삼성전자주식회사 반도체 패키지
US11404394B2 (en) * 2019-09-09 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with integrated device integrated beneath the semiconductor chip
TWI757864B (zh) 2019-09-09 2022-03-11 台灣積體電路製造股份有限公司 封裝結構及其形成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2695175B2 (ja) * 1988-01-29 1997-12-24 株式会社日立製作所 半導体装置の製造方法
JP2591499B2 (ja) * 1994-10-21 1997-03-19 日本電気株式会社 半導体装置
JP2001110928A (ja) * 1999-10-04 2001-04-20 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法
JP3910391B2 (ja) 2001-09-04 2007-04-25 株式会社ルネサステクノロジ 積層型半導体装置
TW582100B (en) * 2002-05-30 2004-04-01 Fujitsu Ltd Semiconductor device having a heat spreader exposed from a seal resin
JP2005175423A (ja) * 2003-11-18 2005-06-30 Denso Corp 半導体パッケージ
US7786591B2 (en) * 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US7271479B2 (en) * 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same

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