CN105575926A - 具有应力补偿的芯片电极的半导体器件 - Google Patents

具有应力补偿的芯片电极的半导体器件 Download PDF

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Publication number
CN105575926A
CN105575926A CN201510739122.7A CN201510739122A CN105575926A CN 105575926 A CN105575926 A CN 105575926A CN 201510739122 A CN201510739122 A CN 201510739122A CN 105575926 A CN105575926 A CN 105575926A
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China
Prior art keywords
metal
chip
semiconductor device
layer
semiconductor chip
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CN201510739122.7A
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Inventor
D.阿勒斯
U.法斯特纳
P.菲舍尔
K-H.加泽
S.亨内克
S.克里维克
K.马托伊
F.魏尔恩伯克
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN105575926A publication Critical patent/CN105575926A/zh
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Abstract

本发明涉及具有应力补偿的芯片电极的半导体器件。半导体器件包括具有第一主表面和第二主表面的半导体芯片。芯片电极被设置在第一主表面上。芯片电极包括第一金属层，该第一金属层包括选自由W、Cr、Ta、Ti和W、Cr、Ta、Ti的金属合金组成的组的第一金属材料。芯片电极进一步包括第二金属层，该第二金属层包括选自由Cu和Cu的合金组成的组的第二金属材料，其中第一金属层被布置在半导体芯片和第二金属层之间。

Description

具有应力补偿的芯片电极的半导体器件
技术领域
本发明涉及具有芯片电极的半导体芯片，并且特别地涉及将芯片电极电连接至导电元件的技术。
背景技术
半导体器件制造商坚持不懈地努力提高其产品的性能，同时降低其制造成本。半导体器件制造的一个方面在于封装半导体芯片。封装常常涉及将半导体芯片电极键合到电接触元件。就机械牢固性和电气可靠性而言的可实现的键合质量是针对以低费用获得高产品产量的重要参数。
出于这些和其它原因，存在对本发明的需要。
附图说明
附图被包括进来以提供对实施例的进一步理解，并且结合在该说明书中且构成该说明书的一部分。附图图示实施例并且和说明书一起用于解释实施例的原理。其它实施例以及实施例的许多预期优点将容易理解，因为通过参考下面的详细描述它们变得更好理解。附图的元素不必相对于彼此成比例。同样的参考数字指代对应的类似部件。
图1示意性地图示了包括半导体芯片和设置于半导体芯片第一主表面上并且具有应力补偿层和焊盘金属层的芯片电极的示例性半导体器件的横截面视图。
图2示意性地图示了包括半导体芯片和设置于半导体芯片两个主表面上并且每一个具有应力补偿层和焊盘金属层的芯片电极的示例性半导体器件的横截面视图。
图3示意性地图示了包括半导体芯片、设置于半导体芯片第一主表面上并且具有应力补偿层和焊盘金属层的芯片电极、焊料材料层和电接触元件的示例性半导体器件的横截面视图。
图4示意性地图示了图3的示例性半导体器件在形成焊料键合接缝之后的横截面视图。
图5示意性地图示了类似于图4中示出的半导体器件的除了在形成焊料键合接缝期间焊盘金属层完全转变为金属间相之外的示例性半导体器件的横截面视图。
图6是在半导体芯片上制造芯片电极的示例性工艺的流程图。
图7A示意性图示了放置在载体上的半导体芯片和放置在半导体芯片上的接触夹的横截面视图。
图7B示意性图示了图7A中示出的布置的顶视图。
图7C示意性图示了图7A的布置在引入到烘炉中并且形成焊料接缝之后的横截面视图。
图8图示了用于使用隧道式烘炉来制造半导体器件的方法的实施例的示意性视图。
图9图示了用于在烘炉中使用批量工艺来制造半导体器件的方法的实施例的示意性视图。
具体实施方式
在下面的详细描述中对附图进行参考，附图形成详细描述的一部分，并且在附图中借助于图示示出在其中可以实践本发明的特定实施例。在这点上，诸如“顶”、“底”、“前”、“后”、“上”、“下”等方向术语参考正被描述的（一个或多个）附图的定向来使用。因为实施例的部件能够被定位在多个不同的定向中，所以方向术语被用于图示的目的而绝不是限制。要理解在不脱离本发明范围的情况下，可以利用其它实施例并且可以进行结构或逻辑上的改变。因此下面详细的描述不以限制性的意义来解读，并且本发明的范围由所附权利要求来限定。
要理解，在本文中描述的各种示例性实施例的特征可以彼此相组合，除非另外特定指出。
如该说明书中使用的，术语“键合的”、“附着的”、“连接的”、“耦合的”和/或“电连接的/电耦合的”不意图表示元件或层必须直接接触在一起；居间元件或层可以分别被提供在“键合的”、“附着的”、“连接的”、“耦合的”和/或“电连接的/电耦合的”元件之间。然而，根据公开内容，上面提及的术语可选地还可以具有下述特定意义：元件或层直接接触在一起，即没有居间元件或层分别被提供在“键合的”、“附着的”、“连接的”、“耦合的”和/或“电连接的/电耦合的”元件之间。
进一步，关于被形成或被定位“在表面之上”的部分、元件或材料层而使用的词“之上”在本文中可以被用来表示部分、元件或材料层“间接地被定位（例如被放置、被形成、被沉积等）在暗指表面上”，其中一个或多个附加的部分、元件或层被布置在暗指表面和部分、元件或材料层之间。然而，关于被形成或被定位“在表面之上”的部分、元件或材料层而使用的词“之上”还可以可选地具有特定含义：部分、元件或材料层“直接地被定位（例如被放置、被形成、被沉积等）在暗指表面上”，例如与暗指表面直接接触。
在本文中描述包含半导体芯片的器件。特别地，可以涉及具有垂直结构的半一个或多个导体芯片，就是说，可以以这样的方式来制造半导体芯片使得电流能够以垂直于半导体芯片的主表面的方向流动。具有垂直结构的半导体芯片在其两个主表面上（就是说，在其顶侧和底侧上）具有电极。特别地，可以涉及具有垂直结构的半导体功率芯片。
在各种其它实施例中，可以涉及具有水平结构的半导体芯片。具有水平结构的半导体芯片可以仅在一个表面上（例如，在其顶侧表面上）具有电极。特别地，可以涉及具有水平结构的半导体功率芯片。
半导体芯片可以从诸如例如Si、SiC、SiGe、GaAs、GaN、AlGaN、InGaAs、InAlAs等特定半导体材料来制造，并且此外可以包含不是半导体的无机和/或有机材料。半导体芯片可以是不同的类型并且可以通过不同的技术来制造。
在本文中描述的半导体芯片可以包括一个或多个逻辑集成电路。特别地，如果半导体芯片是功率芯片，那么功率半导体芯片可以包括：一个或多个逻辑集成电路，诸如例如用于驱动半导体功率芯片的驱动器电路；和/或一个或多个传感器，诸如例如温度传感器。逻辑集成电路可以是例如包括例如存储器电路、电平移位器等的微控制器。
例如，在本文中描述的半导体芯片可以配置为功率MISFET（金属绝缘体半导体场效应晶体管）、功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结型栅场效应晶体管）、HEMT（高电子迁移率晶体管）、功率双极晶体管或功率二极管诸如例如PIN二极管或肖特基二极管。作为示例，在垂直功率器件中，功率MISFET或功率MOSFET或HEMT的源极接触电极和栅极接触电极可以位于一个主表面上，而功率MISFET或功率MOSFET或HEMT的漏极接触电极可以布置在另一主表面上。进一步，在本文中诸如例如HEMT的半导体功率芯片被认为是水平器件，其中电极仅被布置在其顶表面上。
半导体芯片具有设置在半导体芯片主表面上的芯片电极（芯片焊盘）。芯片电极允许与包括在半导体芯片中的（一个或多个）集成电路进行电气接触。芯片电极中的至少一个包括至少两个金属层，即应力补偿层和焊盘金属层。这些金属层可以以任何期望的几何形状来制造。这些金属层可以例如具有覆盖半导体主表面的限定区域的岸面（land）的形式，该金属层被设置在半导体主表面之上。
焊料材料可以被施加至芯片电极以将半导体芯片电气地和机械地连接至诸如例如载体或接触夹的芯片外电气接触元件。焊料材料可以是软焊料材料。焊料材料可以基于Sn，例如可以包括下述或由下述组成：Sn或Sn的合金，特别是Sn（Ag）、Sn（Au）、Sn（Zn）、Sn（Sb）、Sn（AgCu）或Sn（CuNiGe）。
在本文中针对合金使用的符号中，主要元素（例如Sn）是合金的基础或基质，而围在括号中的（一个或多个）次要组分是（一个或多个）溶质。作为示例，Sn（Ag）是二元Sn合金的示例，Sn（AgCu）是三元Sn合金的示例，Sn（CuNiGe）是四元Sn合金的示例。主要元素总是合计等于或大于合金的50%（原子百分比）。
特别地，如果焊料材料包括Sn，那么所述焊料材料可以包括大于50%（原子百分比）,80%（原子百分比）,90%（原子百分比）或甚至95%（原子百分比）的Sn含量。焊料材料还可以包括100%（原子百分比）的Sn含量。焊料材料可以例如没有Pb。
焊料材料可以是包括以上成分的焊料金属颗粒的焊料膏。进一步，它可以包含焊料金属颗粒悬浮在其中的熔剂材料。焊料材料可以进一步包括间隔颗粒，诸如例如具有在例如5μm和30μm之间范围中的直径的Cu颗粒或Ni涂布的Cu颗粒。
图1示意性地图示了示例性半导体器件100。半导体器件100包括具有第一主表面11和相对于第一主表面11布置的第二主表面12的半导体芯片10。进一步，半导体器件100包括芯片电极20，例如半导体芯片10的负载电极或控制电极。芯片电极20被设置在半导体芯片10的第一主表面11之上。芯片电极20包括第一金属层21和第二金属层22。第二金属层22被布置在第一金属层21之上。
在本文中也被称为应力补偿层的第一金属层21包括第一金属材料或由其组成，该第一金属材料选自由以下组成的组：W、Cr、Ta、Ti和W、Cr、Ta、Ti的金属合金。作为示例，第一金属层21可以包括下述或由下述组成：W合金，特别是W（Ti）合金。基础或基质金属W、Cr、Ta或Ti合计等于或多于总体成分的50%（原子百分比）。它还可以合计总体成分的100%（原子百分比）。
特定地，第一金属层21可以具有下述成分：在其中基础或基质金属W、Cr、Ta或Ti具有等于或多于70%（原子百分比）、80%（原子百分比）或90%（原子百分比）的含量，其中（一个或多个）次要组分（例如单独的Ti或与其它金属元素一起）加起来达到成分的100%（原子百分比）。要指出残余不想要的杂质可以被包含在第一金属层21的成分中，然而其在成分符号中不被指定，因为它是本领域的常见做法。
芯片电极20的第二或焊盘金属层22基于Cu，例如可以由Cu或Cu的合金（在下文中还被表示为Cu/Cu合金）组成。第二金属层22具有上表面22a，该上表面22a被配置成被焊接至电接触元件（图1中未示出），如在本文中以下将进一步更详细描述的。进一步，第二金属层22具有下表面22b，该下表面22b可以例如与第一金属层21的上表面21a直接接触。第一金属层的下表面21b可以例如与半导体芯片10的第一主表面11直接接触。然而，要指出诸如例如粘附层或阻挡层的一个或多个中间层可以设置在形成芯片电极20的第一金属层21和第二金属层22的堆叠之下、之间或之上。
第一金属层21可以具有等于或大于50nm、100nm、200nm、300nm或400nm的厚度。进一步，第一金属层21可以具有等于或小于500nm、400nm、300nm、200nm、100nm或80nm的厚度。
第二金属层22可以具有下述厚度：等于或大于6μm，特别是7μm。特别地，第二金属层22的厚度可以等于或大于9μm、11μm、13μm或15μm。第二金属层22的厚度可以等于或小于50μm、40μm、30μm、20μm、15μm或10μm。
第一金属层21的厚度在其下表面21b和上表面21a之间被测量，并且第二金属层22的厚度在其下表面22a和上表面22b之间被测量。要指出层21和22两者可以每个跨过其横向延伸具有基本上恒定的厚度（例如，意味着厚度容差变化小于±20%）。
进一步，第一金属层21可以覆盖等于或多于半导体芯片10的第一主表面11的面积的60%、70%、80%或90%。还有可能的是，半导体芯片10的整个第一主表面11被第一金属层21覆盖。
第二金属层22也可以覆盖等于或多于半导体芯片10的第一主表面11的60%、70%、80%或90%的面积，并且特别地例如覆盖整个第一主表面11。典型地，如图1中图示的，第一金属层21在第二金属层22的整个下表面22b下面延伸。
第一金属层21可以充当应力补偿层，该应力补偿层被配置成：当第二金属层22被应用为半导体芯片10之上的可焊接芯片电极焊盘金属层时，抵消在第二金属层22中建立的内部压缩应力。
更特定地，如以下将进一步更详细解释的，基于Cu/Cu合金第二金属层22的芯片电极20必须具有用于可焊接的某个最小厚度。最小厚度是需要的，因为在焊接工艺期间并且例如在通过扩散转移到焊料接缝中的所有随后温度预算期间，第二金属层22的Cu被消耗。Cu从第二金属层22到焊料接缝（图1中未示出）中的该移除使第二金属层22必须具有特定临界最小厚度以避免Cu的完全消耗，该Cu的完全消耗将导致第二金属层22从半导体芯片10脱离。另一方面，等于或大于临界最小厚度的第二金属层22的厚度确保在焊接期间第二金属层22的整个Cu不被消耗，其中效果是至少薄的残余同质Cu/Cu合金层保持在第一金属层21之上。该薄的残余Cu/Cu合金层随后确保焊料接缝的牢固性和/或稳定性和电可靠性。
第二金属层22越厚，在第二金属层22和半导体芯片10之间的界面处的机械错配就越大。更特定地，在其施加至半导体芯片10或施加至晶片之后，第二金属层22倾向于比半导体芯片10的半导体材料在加热期间膨胀以及在冷却期间收缩多得多，该半导体芯片10在切割之前形成该晶片的组成部分。第二金属层22和半导体芯片材料的热-机械行为或CTE（热膨胀系数）的这个差异造成半导体芯片10和/或半导体晶片的翘曲。进一步，芯片电极20在半导体芯片10上的面积越大，得到的翘曲就越高。如果超出临界翘曲，那么顾客处的封装工艺和/或管芯附连将变得不可靠或甚至不可能。因芯片翘曲产生的这些困难可能对于裸露管芯应用甚至也是关键的。
进一步，要指出芯片电极20的第二金属层22和半导体芯片10的半导体材料之间的机械错配特定地包括半导体功率器件。这归因于如下事实：半导体功率器件经常使用非常薄的半导体芯片10（为了减少器件的内部电阻），并且另一方面使用大尺寸的芯片电极以应对所涉及的相对高的电流。这两种状况（薄芯片，宽面积芯片电极）促进翘曲。作为示例，本文中公开的半导体芯片10可以具有例如等于或小于400μm、300μm、200μm、100μm或50μm的厚度。
第一金属层21适配于减少第二金属层22和半导体芯片10之间的机械错配的影响，即减少芯片和/或晶片翘曲（其总体的弓形）。进一步，可以在厚度上设置第二金属层22的尺寸尽可能少地造成翘曲，但是另一方面，确保在芯片电极20和电接触元件（图1中未示出）之间生成合适的焊料接缝。
假设第一金属层21引起的应力补偿或应力弛豫可以归因于第一金属层21的内部应力，该内部应力抵消第二金属层22的内部应力。结果，第二金属层22的内部应力减弱。作用在半导体芯片10或晶片上的该总体应力的减少减少或甚至防止半导体芯片10的翘曲或弓形的发生。
第一金属层（应力补偿层）21可以仅在半导体芯片10的第一主表面11上（见图1）被提供，或仅在半导体芯片10的第二主表面12上被提供，或如例如图2中图示的，在半导体芯片10的第一和第二主表面11、12两者上被提供。更特定地，图2图示示例性半导体器件200，该半导体器件200包括半导体芯片10和芯片电极20并且具有设置在半导体芯片10的第二主表面12上的另一芯片电极40，其中另一芯片电极40包括第三金属层（应力补偿层）41和第二金属层（焊盘金属层）42。第一金属层21和第二金属层22可以将包括尺寸、材料以及以上针对芯片电极20列举的其它量和特性的所有特征分别应用到另一芯片电极40、第三金属层41和第四金属层42，并且对以上描述进行参考以避免重复。要指出对于芯片电极20和另一芯片电极40来说，这些特征（例如尺寸、材料等）可以是不同的，并且意图在本文中公开针对芯片电极20和另一芯片电极40的相应特征的所有可能组合。作为特定示例，第三金属层41可以例如是纯的Ti层，而第一金属层21可以例如是W（Ti）合金层。进一步，作为示例，还可能的是另一芯片电极40不包括第三金属层（应力补偿层）41。
要指出，图2中示出的半导体器件200可以例如是垂直半导体芯片，该垂直半导体芯片具有垂直于半导体芯片10的第一和第二主表面11、12的电流流动。然而，还可能的是，半导体器件200的半导体芯片10具有仅设置在第一主表面11处的一个或多个芯片电极20，以及设置在第二主表面12上的第三金属层41和第四金属层42仅仅提供半导体芯片10的背侧金属化，该半导体芯片10的背侧金属化被用于将半导体芯片10安装在例如芯片载体（图2中未示出）诸如例如引线框架或DCB（直接铜键合）陶瓷衬底上。在这个情况下，第三金属层41和第四金属层42可以仅仅提供半导体芯片10到载体的热耗散和附连，而可以不具有任何电气功能。
图3图示了示例性半导体器件300。半导体器件300可以包括半导体器件100，并且在这方面，对以上描述进行参考以避免重复。进一步，半导体器件300包括焊料键合层60和电接触元件80。在焊接之前，焊料键合层60可以是沉积在第二金属层22的上表面22a之上的焊料膏层。另一方面，电接触元件80可以具有布置在焊料键合层60之上并且例如与焊料键合层60直接接触的下表面80b。
电接触元件80可以例如是接触夹或带。电接触元件80可以包括下述或由下述组成：例如Cu或Cu的合金的金属材料。
可以例如通过将焊料材料膏印制或分配在第二金属层22的上表面22a上来沉积焊料键合层60的焊料材料。焊料材料膏可以包含分布如在以上提及的焊剂中的金属颗粒。
焊料键合层60可以随后被加热至足够将半导体芯片10牢固地附连到电接触元件80的温度T。加热可以例如在烘炉中执行。
作为示例，在烘炉中施加到焊料材料的温度T可以例如在220℃和450℃之间，更特定地，在230℃和330℃之间。
在其停留在烘炉中期间，图3中示出的布置可以不被施加外部压力。就是说，仅重力可以控制当焊料键合层60在烘炉中暴露到高温T时施加到焊料键合层60的力或压力。
在停留在烘炉中期间，焊料键合层60转变成焊料键合接缝60'，如图4和5中示出的。更特定地，焊料材料在熔化温度处开始熔化。作为示例，Sn具有232℃的融化温度。焊料材料被暴露到高于焊料材料的融化温度的温度T。
图4示意性图示了在将芯片电极20焊接到电接触元件80的工艺之后的半导体器件300。如图4中指示的，焊料键合层60已转变成焊料键合接缝60'。进一步，如在图4中由虚线指示的，金属间化合物（IMC）已在之前是第二金属层22的一部分的区域22_1中形成，和/或金属间化合物（IMC）已在之前是电接触元件80的一部分的区域80_1中形成。金属间化合物区域22_1和80_1由下述造成：在回流期间Cu材料分别从第二金属层22和电接触元件80扩散转移到焊料键合接缝60'中。指出的是，与具有可能成分的连续范围的固溶体的合金对比，金属间化合物（IMC）具有良好限定的晶体结构和固定的化学计量法。因此，IMC区别于相同成分的合金。
如可以从图4看到，IMC区域22_1不穿透第二金属层22的全部厚度，就是说在第一金属层21的上表面21a和IMC区域22_1的底22_1b之间保留残余同质金属层。该残余同质金属层确保焊料键合接缝60'保持稳定并且不在机械负载下面分层。
图5图示了半导体器件300'，该半导体器件300'和半导体器件300等同，除了第二金属层22具有小于其临界最小厚度的厚度之外。作为示例，在图5中第二金属层22的厚度可以小于7μm，特别是6μm。在这个情况下，IMC区域22_1尽可能远地向下到达第一金属层21的上表面21a，就是说第二金属层22的Cu在焊料键合接缝60'下面完全被消耗。结果，空洞90可以在第一金属层21的上表面21a附近生成，并且可以造成焊料键合接缝60'变得易毁坏。要指出，基于Sn的焊料材料具有比基于Pb的焊料材料显著更高的Cu消耗。
图6图示了在半导体芯片上制造芯片电极的示例性工艺。在S1处，在半导体芯片的第一主表面的至少一部分之上形成包括第一金属材料的第一金属层，该第一金属材料选自由下述组成的组：W、Cr、Ta、Ti和W、Cr、Ta、Ti的金属合金。第一金属层的形成可以在晶片级上（即在芯片单体化之前）执行。如之前提及的，视需要，类似于第一金属层的第三金属层可以形成在半导体芯片的相对（第二）主表面上，见图2。
第一金属层的形成可以通过PVD（物理气相沉积）例如溅射、或通过CVD（化学气相沉积）来执行。沉积第一金属层的其它工艺也可以是可用的。
随后，在S2处，在第一金属表面的至少一部分之上形成包括第二金属材料的第二金属层，该第二金属材料选自由Cu和Cu合金组成的组。第二金属层可以例如通过PVD例如溅射、流电沉积或无电沉积来形成。
溅射允许产生具有非常少杂质和缺陷的高纯度金属层。另一方面，也被所知为电化学沉积（ECD）的流电沉积允许高沉积速率，然而其具有层中的增加的杂质含量。特定地，ECD层具有显著的硫贡献，除了结构差异之外，该显著的硫贡献允许区分溅射层和流电沉积层。
图7A-7C举例说明根据一个实施例的制造半导体器件400的阶段。以下公开内容在一些方面比前述实施例的公开内容更加详细。要指出，结合图7A-7C描述的细节可以被应用到前述实施例中描述的概念和方面，或与其组合。反之亦然，关于前述实施例公开的特征和概念可以被应用到参考图7A-7C解释的实施例的公开内容，或与其组合。
图7A示意性地图示了载体100，例如引线框架或DCB。在下面，不失一般性地，通过引线框架100举例说明载体100。在平面视图（图7B）和沿着线A-A'的横截面视图（图7A）中图示引线框架100。引线框架100可以包括管芯焊盘101、第一引线102、第二引线103和第三引线104。引线102-104可以从管芯焊盘101的一侧基本上平行地突出。第二引线103可以与管芯焊盘101的一侧连续。管芯焊盘101和引线102-104可以通过栏坝（系杆）链接，为了清楚起见图中未图示该栏坝（系杆）。引线102-104可以可选地布置在与管芯焊盘101不同的平面中，但是可替换地可以布置在相同的平面中。
引线框架100可以例如包括Cu或Cu合金，或由Cu或Cu合金组成。引线框架100可以具有范围在100μm和1mm之间的厚度，或可以甚至更厚。引线框架100可以通过对金属板冲孔、铣削或冲压已被制造。
图7A-7C示意性图示了设置在管芯焊盘101之上的半导体芯片10。在一个实施例中，进一步功率半导体芯片可以被放置在相同的管芯焊盘101上或在图7A-7C中未图示的引线框架100的进一步管芯焊盘上。
芯片电极20被布置在第一主表面11上，并且另一芯片电极40被布置在半导体芯片10的第二主表面12上。芯片电极20、40是负载电极。此外，第三芯片电极18可以被设置在半导体芯片10的第一主表面11上。第三芯片电极18可以是控制电极。管芯焊盘101的顶表面可以在尺寸上比半导体芯片10的第二主表面12更大。如之前提及的，第三芯片电极18（控制电极）还可以通过使用如以上描述的相同概念（例如层21、22、60）被连接到夹（类似于接触元件80，未示出）。
半导体芯片10可以被配置为功率器件，例如功率晶体管诸如例如MOSFET、IGBT、JFET、功率双极晶体管或功率二极管。在功率MOSFET或JFET的情况下，芯片电极20是源极电极，另一芯片电极40是漏极电极，并且第三芯片电极18是栅极电极。在IGBT的情况下，芯片电极20是发射极电极，另一芯片电极40是集电极电极，并且第三芯片电极18是栅极电极。在功率双极晶体管的情况下，芯片电极20是发射极电极，另一芯片电极40是集电极电极，并且第三芯片电极18是基极电极。在功率二极管的情况下，负载芯片电极20、40分别是阴极和阳极，并且不存在第三芯片电极。在操作期间，高于5、50、100、500或1000V的电压可以被施加在负载芯片电极20、40之间。
图7A中示出的布置可以以顺序拾放构建工艺来建立。首先，焊料材料的焊料键合层90_1可以被施加在管芯焊盘101之上。半导体芯片10可以随后被放置在焊料键合层90_1之上，其中其第二主表面12面对管芯焊盘101。在将半导体芯片10放置在管芯焊盘101之上之前或之后，焊料键合层60可以被施加到芯片电极20上。同时地或在任何其它时间，焊料键合层90_2可以被施加到第一引线102。可以通过印制、分配或如之前提及的任何其它合适技术沉积焊料键合层60、90_1、90_2。
随后，接触夹80被放置在第一引线102和半导体芯片10之上。接触夹80具有面对芯片电极20的第一接触区域81和面对第一引线102的第二接触区域82。
接触夹80可以从如以上提及的金属或金属合金来制造。接触夹80的形状不被限制到任何尺寸或几何形状。接触夹80可以具有如在图7A-7B中举例说明的形状，但是其它形状也是可能的。在一个实施例中，接触夹80可以具有范围从例如100μm到800μm的厚度。接触夹80可以通过冲压、冲孔、按压、切割、锯切、铣削或任何其它合适技术来制造。接触夹80的底表面可以例如具有银或金的表面完成层。可选地，NiP层可以夹在接触夹80的金属（例如Cu或Cu合金）和银或金层之间。银或金层可以例如具有范围在10到200nm的厚度。
图7C示意性地图示了图7A-7B中示出的布置被引入到烘炉50中。在烘炉50中，焊料键合层60、90_1、90_2可以同时被加热到温度T以将焊料键合层60、90_1、90_2转变成相应的焊料键合接缝60'、90_1'、90_2'。烘炉工艺可以如以上描述的来执行，特别是考虑到不使用外部压力、温度T和焊料材料的应用。
图8示意性地图示了根据一个实施例的烘炉工艺。载体100与半导体芯片10以及可选的电接触元件（例如接触夹）80一起被称为布置X。布置X被放置在输送机70上。输送机70可以例如由步进电机驱动并且在由图8中的箭头P指示方向上移动布置X。在将布置X放置在输送机70上之后，布置X传递通过隧道式烘炉50_1。在隧道式烘炉50_1中，焊料键合层60、90_1、90_2被暴露以加热来得到最大温度T。布置X在隧道式烘炉50_1中的停留时间可以或在使用连续工艺（即输送机70以恒定速度被驱动）的情况下由输送机70的速度控制，或在使用半连续工艺的情况下由时间间隔控制，在该时间间隔期间以间歇操作停止输送机。停留时间应该足够大以允许焊料材料的完全回流。在隧道式烘炉50_1中，压力可以减少到环境压力之下（即可以应用真空）。
图9图示了用于焊接布置X的进一步烘炉工艺的示意性视图。这里，布置X被放置在一个或多个料斗（magazine）36中。随后，料斗36和可能地进一步料斗36被放置或引入在烘炉50_2中。在烘炉50_2中，类似于隧道式烘炉50_1，焊料键合层60、90_1、90_2被暴露以加热来得到最大温度T。在烘炉50_2中，压力可以减少到环境压力之下（即可以应用真空）。停留时间过去之后，一个或多个料斗36从烘炉50_2移除。
在焊料回流之后，半导体芯片10、电元件80和例如载体100可以至少部分地被包围或嵌入在至少一个电绝缘材料(未示出)中。电绝缘材料可以形成封装体。封装体可以包括模具材料或层压片，或由模具材料或层压片制成。可以使用各种技术来形成模具材料的封装体，例如压缩成型、注塑成型、粉末成型或液体成型。进一步，如果封装体由层压片制成，那么封装体可以具有一片层的形状，例如层压在半导体功率芯片和导电载体的顶上的一片薄片或箔。封装体可以形成包装的外围的部分，即可以至少部分地限定半导体器件的形状。
电绝缘材料可以包括热固性材料或热塑性材料，或由热固性材料或热塑性材料制成。热固性材料可以例如基于环氧树脂制成。热塑性材料可以例如包括聚醚酰亚胺（PEI），聚醚砜（PES）、聚苯硫醚（PPS）或聚酰胺酰亚胺（PAI）的组的一个或多个材料。
各种不同类型的半导体器件可以被配置成使用如在本文中描述的芯片电极20、40。作为示例，根据公开内容的半导体器件可以构成例如电源、DC-DC电压转换器、AC-DC电压转换器、功率放大器和许多其它功率或非功率器件。
进一步，在本文中描述的半导体器件可以在包括例如其中需要高的器件鲁棒性的汽车应用的许多不同应用中使用。
尽管在本文中已描述和图示了特定实施例，但是本领域普通技术人员将理解各种替换和/或等同的实施方式可以替代示出和描述的特定实施例而不脱离本发明范围。本申请意图覆盖在本文中所讨论的特定实施例的任何修改或变型。因此，意图本发明仅由权利要求书及其等同物来限制。

Claims (23)

1.一种半导体器件，包括：
半导体芯片，具有第一主表面和第二主表面；和
芯片电极，设置在所述半导体芯片的所述第一主表面上，其中所述芯片电极包括：
第一金属层，包括选自由W、Cr、Ta、Ti和W、Cr、Ta、Ti的金属合金组成的组的第一金属材料；和
第二金属层，包括选自由Cu和Cu的合金组成的组的第二金属材料，其中所述第一金属层被布置在所述半导体芯片和所述第二金属层之间。
2.权利要求1的所述半导体器件，其中所述第一金属层是W合金层，更特定地是W（Ti）合金层。
3.权利要求1或2的所述半导体器件，其中所述第一金属层是具有等于或多于原子百分比为70%的基础金属含量的W、Cr、Ta或Ti的基础金属的金属合金。
4.前述权利要求之一的所述半导体器件，其中所述第二金属层具有等于或大于6μm特别是7μm的厚度。
5.前述权利要求之一的所述半导体器件，其中所述第一金属层具有等于或大于50nm的厚度。
6.前述权利要求之一的所述半导体器件，其中所述第一金属层具有等于或小于500nm的厚度。
7.前述权利要求之一的所述半导体器件，其中所述第一金属层被配置成减少芯片翘曲。
8.前述权利要求之一的所述半导体器件，其中所述半导体芯片是功率芯片并且所述芯片电极是所述半导体芯片的第一负载电极。
9.权利要求8的所述半导体器件，其中所述第一负载电极覆盖等于或多于所述第一主表面的面积的60%。
10.前述权利要求之一的所述半导体器件，进一步包括：
设置在所述半导体芯片的第二主表面上的另一芯片电极，其中所述另一芯片电极包括：
第三金属层，所述第三金属层包括选自由W、Cr、Ta、Ti和W、Cr、Ta、Ti的金属合金组成的组的第三金属材料；以及
第四金属层，所述第四金属层包括选自由Cu和Cu的合金组成的组的第四金属材料，其中所述第三金属层被布置在所述半导体芯片和所述第四金属层之间。
11.权利要求10的所述半导体器件，其中所述第四金属层具有等于或大于6μm特别是7μm的厚度。
12.前述权利要求之一的所述半导体器件，进一步包括：
电接触元件；和
焊料键合层，将所述电接触元件附连到所述芯片电极。
13.权利要求12的所述半导体器件，其中所述焊料键合层的焊料材料选自由Sn和Sn的合金特别是Sn（Ag）、Sn（Au）、Sn（Zn）、Sn（Sb）、Sn（AgCu）和Sn（CuNiGe）组成的组。
14.权利要求12的所述半导体器件，其中所述电接触元件是接触夹。
15.权利要求14的所述半导体器件，进一步包括：
引线框架，其中设置在所述半导体芯片的第二主表面上的另一芯片电极被安装到所述引线框架。
16.权利要求15的所述半导体器件，进一步包括：
形成封装体的电绝缘材料，所述电绝缘材料至少部分地包围所述半导体芯片、所述接触夹和所述引线框架。
17.一种在半导体芯片上制造芯片电极的方法，包括：
在所述半导体芯片的第一主表面的至少一部分之上形成包括第一金属材料的第一金属层，所述第一金属材料选自由W、Cr、Ta、Ti和W、Cr、Ta、Ti的金属合金组成的组；以及
在所述第一金属层的至少一部分之上形成包括第二金属材料的第二金属层，所述第二金属材料选自由Cu和Cu的合金组成的组。
18.权利要求17的所述方法，其中通过溅射或CVD执行第一金属层的形成。
19.权利要求17或18的所述方法，其中通过溅射、流电沉积或无电沉积来执行成第二金属层的形成。
20.权利要求17至19之一的所述方法，其中通过形成第二金属层得到等于或大于6μm特别是7μm的厚度的第二金属层。
21.一种将电接触元件键合到半导体芯片的芯片电极的方法，其中所述芯片电极包括：第一金属层，包括选自由W、Cr、Ta、Ti和W、Cr、Ta、Ti的金属合金组成的组的第一金属材料；和第二金属层，覆盖所述第一金属层上并且包括选自由Cu和Cu的合金组成的组的第二金属材料，所述方法包括：
将接触元件放置在所述芯片电极之上，其中焊料材料层被提供在所述芯片电极和所述接触元件之间；以及
将热施加到焊料材料层以在所述芯片电极和所述接触元件之间形成焊料键合。
22.权利要求21的所述方法，其中施加热包括将所述半导体芯片和所述接触元件放置在回流焊接烘炉中。
23.权利要求22的所述方法，其中在所述回流焊接烘炉中时不对所述接触元件和所述半导体芯片施加外部压力。
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CN106531821A (zh) * 2016-11-17 2017-03-22 苏州元昱新能源有限公司 一种二极管、配置二极管的光伏电池串及光伏组件
CN106908970A (zh) * 2017-03-06 2017-06-30 中国电子科技集团公司第二十六研究所 声光晶体与换能器键合结构
CN106908970B (zh) * 2017-03-06 2019-09-13 中国电子科技集团公司第二十六研究所 声光晶体与换能器键合结构
CN109285767A (zh) * 2017-07-21 2019-01-29 三菱电机株式会社 功率器件

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