CN109979825A - 阵列批次式封装元件晶粒的电路元件制作方法 - Google Patents

阵列批次式封装元件晶粒的电路元件制作方法 Download PDF

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Publication number
CN109979825A
CN109979825A CN201811532954.1A CN201811532954A CN109979825A CN 109979825 A CN109979825 A CN 109979825A CN 201811532954 A CN201811532954 A CN 201811532954A CN 109979825 A CN109979825 A CN 109979825A
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Prior art keywords
crystal grain
circuit element
electrode
termination
array
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CN201811532954.1A
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胡志良
胡哲恺
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Individual
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Priority claimed from TW106144126A external-priority patent/TW201929098A/zh
Priority claimed from TW106144125A external-priority patent/TW201929097A/zh
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Publication of CN109979825A publication Critical patent/CN109979825A/zh
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Abstract

一种以多单位的阵列形态同时封装多个单位的元件晶粒以批次制作电路元件的方法，其步骤包含：于基底阵列铜板上形成阵列中每一电路元件的至少二端电极初步构造；其后为每一电路元件取置元件晶粒；再为每一电路元件取置水平导电片，其水平一侧的底接面对置于元件晶粒体顶面的电极；然后为每一电路元件取置垂直导电块。之后进行回焊，将晶粒体底面电极与其对应的基底阵列铜板的端电极初步构造表面间的预施焊锡料，水平导电片其底接面与其对应的晶粒体顶面电极间的预施焊锡料，垂直导电块上端与其对应的水平导电片垂直接孔内垂直接面间的预施焊锡料，垂直导电块下端底接面与其对应的端电极初步构造表面间的预施焊锡料，全皆同时融熔后固焊。

Description

阵列批次式封装元件晶粒的电路元件制作方法
技术领域
本发明涉及半导体电路元件的封装体及封装方法，特别涉及需求较大功率，良好热散的表面粘着电路元件的封装体及封装方法。本发明更涉及以多单位的阵列形态，同时封装多个单位的电路元件晶粒以批次方式，有效率且高良率地制作电路元件的方法。
背景技术
目前诸如二极管、发光二极管、晶体管及闸流体等离散式电路元件(DiscreteCircuit Component)的表面粘着型(Surface Mount)构装，一般常见者大致有圆柱型玻璃/塑胶封装，导线架(Lead-frame)有引脚封装(Leaded package)，方形无引脚的平板式封装(Flat-pack leadless)，以及覆晶(Flit-chip)封装等。其中，覆晶封装虽有轻薄短小优点，但因制程昂贵，应用不便，及零件相对易于老化诸多缺点，故少使用在诉求大功率及耐久等应用上。相较之下，前述除覆晶封装以外是目前功率型封装体的市场主流。不过，随着电性要求越高，功率增大，热传及高温等因素所引致问题，上述常见封装制程技术亦已趋近技术瓶颈。
高功率电路元件，特别是诸如功率二极管，晶体管及闸流体等是功率电子(PowerElectronics)应用领域不可或缺的离散式元件。其性能，可靠度，使用寿命等对于诸如再生能源，电动车等重要用途的推广有关键性的影响。但性能寿命以外，其制造成本亦为其广泛应用的同等重要因素。
现有技术制作具良好散热性及高电功率的电路元件封装体的封装方法，例如中国台湾专利I583282号，以及发明申请105110137号，是以两大片导电铜板为基础，以多单位的阵列形态，同时封装多个单位的电路元件晶粒，以便利用批次方式，寻求有效率地大量制作电路元件，以降低单位成本。然而，这两个现有技术利用两大整片铜板的方法需要将其基底阵列铜板、电路元件晶粒体、平行阵列排列的平行导电片，以及焊锡料的厚度公差控制在一定程度之内。一旦其这些制程参数的实质差异控制不佳，其整批产品之中即会发生焊接品质、对位精准不佳的严重后果。换言之，生产良率降低，直接结果即是合格产品的单位成本升高。
发明内容
为克服现有技术前述问题，本发明提供一种以多单位的阵列形态同时封装多个单位的元件晶粒以批次制作电路元件的方法，其元件晶粒体上包含有至少二电极，其中至少一电极位于元件晶粒体顶面，而其余电极则位于相反对应的晶粒体底面。该方法是将每一电路元件其所封装保护的元件晶粒的每一电极电性连接至电路元件构体的一对应端电极。此方法的步骤包含先于一基底阵列铜板上形成阵列中每一电路元件的至少二端电极初步构造。其后为每一电路元件取置元件晶粒，使晶粒体底面电极面对基底阵列铜板的至少二端电极初步构造中的一对应端电极初步构造的表面。再为每一电路元件取置一水平导电片，其水平一侧的一底接面对置于元件晶粒体顶面的电极。然后为每一电路元件取置一垂直导电块，其上端置入水平导电片其水平另一侧的一垂直接孔内，其具有一垂直接面以与垂直导电块上端对接，垂直导电块下端的一底接面则对置于基底阵列铜板的至少二端电极初步构造中的一对应端电极初步构造的表面。之后则进行回焊，将晶粒体底面电极与其所对应的基底阵列铜板的端电极初步构造表面间的预施焊锡料，水平导电片其底接面与其所对应的晶粒体顶面电极间的预施焊锡料，垂直导电块上端与其所对应的水平导电片垂直接孔内垂直接面间的预施焊锡料，与垂直导电块下端底接面与其所对应的端电极初步构造表面间的预施焊锡料，全皆同时融熔后固焊。
附图说明
图1显示应用于本发明一实施例制作具有三端电极一电路元件的基底阵列铜板的局部区域。
图2的透视图显示可适用于图1的基底阵列铜板的电路元件的元件晶粒体的基本构造。
图3A的示意图显示本发明制作电路元件时于基底阵列铜板之上依序所进行的取置作业。
图3B的透视图显示图3A中取置程序完成且经回焊处理后每一电路元件单位所完成的单位结构体。
图4的透视图显示依据本发明先取置垂直导电块，其后再取置水平导电片的另种作法，其回焊处理后每一电路元件单位所完成的单位结构体。
图5A为图3B的单位结构体进行水气密封装之后，沿aa’面切割的剖面图。
图5B为图3B的单位结构体进行水气密封装之后，沿bb’面切割的剖面图。
图6的透视图是水气密封装后，个别电路元件单位被分别切割分离之前，整个阵列的背面构造。
图7显示依据本发明方法所制作电路元件其结构体的外形构造。
具体实施方式
图1显示应用于本发明一实施例制作具有三端电极的电路元件的基底阵列铜板1000，其局部区域，放大透视图。依据本发明，典型的批次制作会使用数十乘数十的电路元件单位的矩阵。图1中仅显示其中的四个单位，如图中以标号1020所标示的虚线框线所围的范围。此实例中，基底阵列铜板1000的上表面预先指定或初步形成上表面端电极1011，1012。
在图1的例中，此些端电极初步构造可以突出于基底阵列铜板1000的上表面，其可利用诸如蚀刻的减法制程、电镀/化学的加法制程或常用的机械加工，如车、铣、钻、磨、锯、冲压等技术于一基础铜板上形成，此可整批制作多个电路元件单位1020的端电极初步构造1011及1012。在另一实施例中，此些端电极初步构造1010亦可不须突出于基底阵列铜板1000的上表面。
图2的透视图显示可适用于图1的基底阵列铜板的电路元件的元件晶粒体的基本构造。典型的功率二极管，晶体管或闸流体的元件晶粒，一般而言，是矩型体的构造。依据本发明，一整批的这种元件晶粒200将分别被取置于图1基底阵列铜板1000表面上的各自对应电路元件单位1020上。于此图1及图2的实例中，元件晶粒体200，当利用自动取置设备(automatic pick-and-place equipment)正确地置放于基底阵列铜板1000表面上的对应单位1020上时，其二底面电极220将分别与基底阵列铜板1000表面上的端电极初步构造1011对正吻合。
图3A的示意图显示本发明制作电路元件时于基底阵列铜板之上依序所进行的取置作业，其中包含首先取置元件晶粒体200，将此晶粒体定置于其指定元件单位1020的定位上。如同前述，晶粒体200的底面电极220分别与基底阵列铜板1000的端电极初步构造1011吻合。
接着取置一水平导电片3001，其水平一侧，即图3中的左侧，其一底接面对置于元件晶粒体200顶面的电极210。
其后再取置一垂直导电块3005，其上端置入水平导电片3001其水平另一侧，即图中右侧的一垂直接孔3003内。此垂直接孔3003具有垂直接面3002以与垂直导电块3005上端对接。垂直导电块3005下端的一底接面则对置于基底阵列铜板1000上的对应端电极初步构造1012的表面。
注意到垂直接孔3003可为具有完整周缘的洞孔。其亦可为不具完整周缘的开放洞孔，如图中所示。
前述元件晶粒体200，水平导电片3001，与垂直导电块3005先后取置动作完成之后，即可进行回焊(thermal reflow)。此回焊处理可将晶粒体200底面电极220与其所对应的基底阵列铜板1000的端电极初步构造1011表面间所预先施布的焊锡料；水平导电片3001其底接面与其所对应的晶粒体200顶面电极210间所预先施布的焊锡料；垂直导电块3005上端与其所对应的水平导电片3001垂直接孔3003内垂直接面3002间所预先施布的焊锡料；以及垂直导电块3005下端底接面与其所对应的基底阵列铜板1000的端电极初步构造1012表面间所预先施布的焊锡料，全皆同时融熔后固焊。
前述的预先施布的施焊锡料可为一般常用含锡颗粒的锡膏，或含锡的焊片。此些焊料可在元件晶粒体200，水平导电片3001，与垂直导电块3005的取置程序步骤之间适时施用。若用锡膏，可利用诸如自动点锡膏设备进行，若用焊片，则可利用元件晶粒的取置设备进行。
图3B的透视图显示图3A中取置程序完成且经回焊处理，所有焊料皆固焊而形成永久性电性导接之后，为每一电路元件单位所完成的单位结构体3100。
图3B之中，前述晶粒体200底面电极220与其所对应的基底阵列铜板1000的端电极初步构造1011表面间所预先施布的焊锡料，此时已焊固为焊接层1018；水平导电片3001其底接面与其所对应的晶粒体200顶面电极210间所预先施布的焊锡料，此时已焊固为焊接层218；垂直导电块3005上端与其所对应的水平导电片3001垂直接孔3003内垂直接面3002间所预先施布的焊锡料，此时已焊固为焊接层3008；而垂直导电块3005下端底接面与其所对应的基底阵列铜板1000的端电极初步构造1012表面间所预先施布的焊锡料，此时则已焊固为焊接层1028。
依据本发明，于另一实施例中，水平导电片及垂直导电块的取置顺序亦可对调。此时，水平导电片的一侧即不需具备有垂直接孔(3003，图3A)。换言之，图3A及图3B的实施例是先取置水平导电片3001，然后才取置垂直导电块3005，而此另种作法则是先取置垂直导电块，然后才取置水平导电片。
图4的透视图显示此先取置垂直导电块3005A，其后再取置水平导电片3001A的作法，其取置程序完成且经回焊处理后每一电路元件单位所完成的单位结构体3100A。依据本发明，制作图4单位结构体3100A的程序是如下述。
首先取置元件晶粒体200，将此晶粒体定置于其指定元件单位的定位上。晶粒体200的底面电极220分别与基底阵列铜板1000的端电极初步构造1011吻合。
接着取置一垂直导电块3005A，其下端的一底接面对置于基底阵列铜板1000的对应端电极初步构造1012的表面。
其后再取置一水平导电片3001A，其水平一侧的一底接面对置于元件晶粒体200顶面的电极210，其水平另一侧的另一底接面则对置于垂直导电块3005A其上端的一顶接面。
前述元件晶粒体200，垂直导电块3005A，与水平导电片3001A先后取置动作完成之后，即可进行回焊(thermal reflow)。此回焊处理可将晶粒体200底面电极220与其所对应的基底阵列铜板1000的端电极初步构造1011表面间所预先施布的焊锡料；水平导电片3001A其底接面与其所对应的晶粒体200顶面电极210间所预先施布的焊锡料；垂直导电块3005A上端与其所对应的水平导电片3001A其底接面间所预先施布的焊锡料；以及垂直导电块3005A下端底接面与其所对应的基底阵列铜板1000的端电极初步构造1012表面间所预先施布的焊锡料，全皆同时融熔后固焊。
图4之中，前述晶粒体200底面电极220与其所对应的基底阵列铜板1000的端电极初步构造1011表面间所预先施布的焊锡料，此时已焊固为焊接层1018；水平导电片3001A其底接面与其所对应的晶粒体200顶面电极210间所预先施布的焊锡料，此时已焊固为焊接层218；垂直导电块3005A上端与其所对应的水平导电片3001A其底接面间所预先施布的焊锡料，此时已焊固为焊接层3008；而垂直导电块3005A下端底接面与其所对应的基底阵列铜板1000的端电极初步构造1012表面间所预先施布的焊锡料，此时则已焊固为焊接层1028。
依据本发明的阵列批次式封装元件晶粒的电路元件制作方法，图3B电路元件的单位结构体3100及其制作方法可适用于整批元件晶粒体的厚度公差变异较大的情况。相较之下，图4电路元件的单位结构体3100A及其制作方法则可适用于整批元件晶粒体的厚度公差变异较小的情况。二者相比，虽然水平导电片与垂直导电快块构造稍有不同，且取置次序前后相反，但基本上，本发明电路元件封装体内的电路元件的单位结构体，皆是利用垂直导电块上端与水平导电片一端的焊接而将元件晶粒体200的顶面电极210电性连结到基底阵列铜板1000上的对应端电极初步构造1012。两者所具有的大面积焊接面是本发明方法所制作电路元件具备高功率，良好散热性的关键。
此外，本发明图3A及图4中所描述的电路元件的单位结构体中的四个焊接面，其容许加温回焊时融熔焊料的整体系统平衡特性，其结果为批次制程良率的极为显着改善。此改善直接代表电路元件产品成本的降低。
依据本发明，再形成图3B或4中的强固高性能单位结构体后，即可进行水气密封装保护。一般典型作法是利用模具以胶状或胶饼树酯进行灌注并冷却固化。固化后的树酯体5100即可保护整个单位结构体。图5A为图3B的单位结构体进行水气密封装之后，沿aa’面切割的剖面图。图5B则为图3B的单位结构体进行水气密封装之后，沿bb’面切割的剖面图。
其后，便可对基底阵列铜板1000的底面进行减法处理，以将整个阵列所有个别电路元件的所有端电极分离开来。一般典型的减法处理可以是，例如，化学蚀刻处理。图6的透视图即为水气密封装，并分离所有端电极之后，个别电路元件单位被分别切割分离之前，整个阵列的背面构造。注意到图6中此例是具二端电极6009的电路元件，例如功率二极管。
接着，图6的整体阵列便可以沿图中的AA’与BB’切割面进行切割，以将阵列中所有个别电路元件实体分离开。图7即显示依据本发明方法所制作电路元件2000其结构体的外形构造。
如同本技艺中所熟知，图7中各别分离之后的电路元件单体，其所有端电极皆已电性分离，此时可对每一个别端电极进行镍-金或镍-锡镀覆处理。
如同本技艺中所熟知，本发明方法所制作的电路元件可为具有二、三或更多端电极的离散式电路元件。此电路元件可为二极管。其亦可为晶体管。其亦可为光耦合开关。其还可为具有至少四端电极的集成电路元件。
本发明已经由优选实例公开说明如上，然以上说明并非用以限定本发明。在不脱离于本发明精神的情况下，一般熟习于本技艺者当可作些许变动与变化。因此本发明的保护范围当视后附的权利要求所界定者为准。

Claims (18)

1.一种以多单位的阵列形态同时封装多个单位的元件晶粒以批次制作电路元件的方法，元件晶粒体上包含有至少二电极，其中，至少一电极位于元件晶粒体顶面，其余电极则位于相反对应的晶粒体底面，该方法将每一电路元件其所封装保护的元件晶粒的每一电极电性连接至电路元件构体的一对应端电极，其包含有下列步骤：
于一基底阵列铜板上形成阵列中每一电路元件的至少二端电极初步构造；
为每一电路元件取置元件晶粒，使晶粒体底面电极面对基底阵列铜板的至少二端电极初步构造中的一对应端电极初步构造的表面；
为每一电路元件取置一水平导电片，其水平一侧的一底接面对置于元件晶粒体顶面的电极；
为每一电路元件取置一垂直导电块，其上端置入水平导电片其水平另一侧的一垂直接孔内，其具有一垂直接面以与垂直导电块上端对接，垂直导电块下端的一底接面则对置于基底阵列铜板的至少二端电极初步构造中的一对应端电极初步构造的表面；与，
进行回焊，将晶粒体底面电极与其所对应的基底阵列铜板的端电极初步构造表面间的预施焊锡料，水平导电片其底接面与其所对应的晶粒体顶面电极间的预施焊锡料，垂直导电块上端与其所对应的水平导电片垂直接孔内垂直接面间的预施焊锡料，与垂直导电块下端底接面与其所对应的端电极初步构造表面间的预施焊锡料，全皆同时融熔后固焊。
2.根据权利要求1所述的方法，其中，该水平导电片的洞孔是具有完整周缘的洞孔。
3.根据权利要求1所述的方法，其中，该水平导电片的洞孔是不具完整周缘的开放洞孔。
4.根据权利要求1所述的方法，其中，回焊处理之后还包含有：
形成水气密隔绝封装结构，其包覆基底阵列铜板上所固焊的元件晶粒，水平导电片，及垂直导电块；
对基底阵列铜板的底面进行减法处理，以分离该阵列中所有个别电路元件的所有端电极；与
切割水气密隔绝封装结构以将阵列中所有个别电路元件实体分离开。
5.根据权利要求4所述的方法，还包含有：
于减法处理，阵列中所有个别电路元件的所有端电极皆分离之后，对每一个别端电极进行镍-金或镍-锡镀覆处理。
6.根据权利要求1所述的方法，其中，该电路元件是具有二、三或更多端电极的离散式电路元件。
7.根据权利要求6所述的方法，其中，该电路元件是二极管。
8.根据权利要求6所述的方法，其中，该电路元件是晶体管。
9.根据权利要求6所述的方法，其中，该电路元件是光耦合开关。
10.根据权利要求1所述的方法，其中，该电路元件是具有至少四端电极的集成电路元件。
11.一种以多单位的阵列形态同时封装多个单位的元件晶粒以批次制作电路元件的方法，元件晶粒体上包含有至少二电极，其中，至少一电极位于元件晶粒体顶面，其余电极则位于相反对应的晶粒体底面，该方法将每一电路元件其所封装保护的元件晶粒的每一电极电性连接至电路元件构体的一对应端电极，其包含有下列步骤：
于一基底阵列铜板上形成阵列中每一电路元件的至少二端电极初步构造；
为每一电路元件取置元件晶粒，使晶粒体底面电极面对基底阵列铜板的至少二端电极初步构造中的一对应端电极初步构造的表面；
为每一电路元件取置一垂直导电块，其下端的一底接面对置于基底阵列铜板的至少二端电极初步构造中的一对应端电极初步构造的表面；
为每一电路元件取置一水平导电片，其水平一侧的一底接面对置于元件晶粒体顶面的电极，其水平另一侧的另一底接面则对置于垂直导电块其上端的一顶接面；与
进行回焊(thermal reflow)，将晶粒体底面电极与其所对应的基底阵列铜板的端电极初步构造表面间的预施焊锡料，水平导电片其底接面与其所对应的晶粒体顶面电极间的预施焊锡料，垂直导电块上端顶接面与其所对应的水平导电片间的预施焊锡料，与垂直导电块下端底接面与其所对应的端电极初步构造表面间的预施焊锡料，全皆同时融熔后固焊。
12.根据权利要求11所述的方法，其中，回焊处理的后还包含有：
形成水气密隔绝封装结构，其包覆基底阵列铜板上所固焊的元件晶粒，水平导电片，及垂直导电块；
对基底阵列铜板的底面进行减法处理，以分离该阵列中所有个别电路元件的所有端电极；与
切割水气密隔绝封装结构以将阵列中所有个别电路元件实体分离开。
13.根据权利要求12所述的方法，还包含有：
于减法处理，阵列中所有个别电路元件的所有端电极皆分离之后，对每一个别端电极进行镍-金或镍-锡镀覆处理。
14.根据权利要求11所述的方法，其中，该电路元件是具有二、三或更多端电极的离散式电路元件。
15.根据权利要求14所述的方法，其中，该电路元件是二极管。
16.根据权利要求14所述的方法，其中，该电路元件是晶体管。
17.根据权利要求14所述的方法，其中，该电路元件是光耦合开关。
18.根据权利要求11所述的方法，其中，该电路元件是具有至少四端电极的集成电路元件。
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