WO2024078079A1 - 一种半导体器件组及其制备方法与应用 - Google Patents

一种半导体器件组及其制备方法与应用 Download PDF

Info

Publication number
WO2024078079A1
WO2024078079A1 PCT/CN2023/107418 CN2023107418W WO2024078079A1 WO 2024078079 A1 WO2024078079 A1 WO 2024078079A1 CN 2023107418 W CN2023107418 W CN 2023107418W WO 2024078079 A1 WO2024078079 A1 WO 2024078079A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
chip
device group
metal frame
cutting
Prior art date
Application number
PCT/CN2023/107418
Other languages
English (en)
French (fr)
Inventor
汪利民
黄鑫
Original Assignee
重庆万国半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 重庆万国半导体科技有限公司 filed Critical 重庆万国半导体科技有限公司
Publication of WO2024078079A1 publication Critical patent/WO2024078079A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions

Definitions

  • the present invention relates to the technical field of semiconductor accessory manufacturing, and in particular to a semiconductor device group and a preparation method and application thereof, and specifically to a semiconductor packaging layer including a copper sheet clip or a welding wire (gold wire/copper wire/aluminum wire/aluminum strip) and a molding and cutting separation manufacturing method and application thereof.
  • a semiconductor packaging layer including a copper sheet clip or a welding wire (gold wire/copper wire/aluminum wire/aluminum strip) and a molding and cutting separation manufacturing method and application thereof.
  • Another design method for injection molding is integrated modularization, that is, when designing the metal frame, the single device structure is regularly arranged in horizontal and vertical formats, and the matching mold design also uses a block design.
  • the mold runner is no longer connected to a single device but is connected to each other through a block design (multiple devices are integrated together), thereby increasing the unit density of the product on a single metal frame, but limiting the appearance requirements of the product device.
  • the blade cutting method is used to separate each device, the external exposure of the device pin can only be maintained on the same plane as the cutting surface of the device, which limits the use of the device in specific applications.
  • the present invention aims to provide a redundant frame structure that can simplify the structure of carrying and isolating a single product unit, thereby increasing the product density on the single-piece frame and reducing the production cost. Cost, improve product reliability, and facilitate the guarantee of pin bending for semiconductor device groups that meet design requirements in specific occasions.
  • the first object of the present invention is achieved through the following technical solution: a semiconductor device group, including a metal frame, a plurality of semiconductor device units; a plurality of wafer carriers are arranged in the metal frame;
  • the semiconductor device unit comprises a chip, pins and a connector, wherein the chip and the pins are located above the metal frame, and the connector is used to electrically connect the electrodes of the chip and the pins;
  • the semiconductor device units are paired in pairs, the chips are respectively located on corresponding wafer carriers, the pins in each pair of semiconductor device units are connected, and the connectors of each pair of semiconductor device units are far away from each other;
  • a plurality of pairs of semiconductor device units are arranged in sequence along the length direction or the width direction of the metal frame, and a packaging layer is provided along the arrangement direction of the plurality of pairs of semiconductor device units, and the packaging layer is located above the wafer carrier.
  • the connecting piece includes a copper sheet clip or a welding wire.
  • the bonding wire includes one or more of gold wire, copper wire, aluminum wire, and aluminum ribbon.
  • the second object of the present invention is to provide a method for preparing a semiconductor device group.
  • the second object of the present invention is achieved by the following technical solution:
  • a method for preparing a semiconductor device group comprises the following steps:
  • step A specifically comprises the following steps:
  • Chip preparation Check whether there is a film on the back of the wafer. If yes, perform wafer cutting. If not, perform wafer cutting after film is applied on the back of the wafer to obtain chips.
  • Chip installation spray silver paste or solder paste on the wafer carrier, and then place the chip on top of the silver paste or solder paste; when silver paste is sprayed on the wafer carrier, an oven is required to bake and cure the chip; when solder paste is sprayed on the wafer carrier, reflow soldering is required separately or in step B.
  • step B specifically comprises the following steps:
  • the connector of the semiconductor device unit is a copper clip
  • spray the solder paste on the specific pin area of the chip and the metal frame place the pin and the copper clip on the solder paste for positioning, and then perform reflow soldering in a reflow oven to melt the solder paste coated between the chip and the metal frame or between the chip and the copper clip for eutectic welding;
  • the pin is connected to the chip by a wire bonding method.
  • step C specifically comprises the following steps:
  • the connecting piece of the semiconductor device unit is a copper clip
  • chemical cleaning is performed; the chemical cleaning includes ultrasonic chemical reagent immersion cleaning or chemical reagent spray cleaning;
  • Plastic encapsulation using a plastic encapsulation material to integrally encapsulate a number of chips and connectors in the width direction of the semiconductor device unit and then performing a curing process to obtain an overall encapsulation layer.
  • the third object of the present invention is to provide an application of a semiconductor device group.
  • the third object of the present invention is achieved by the following technical solution: an application of a semiconductor device group, comprising step D and step E:
  • the cutting is preferably double-sided cutting separation.
  • step D specifically comprises the following steps:
  • the step E specifically includes the following steps: bending the pin into a desired shape; the step E is located between steps d1 and d2 or after steps d1 and d2.
  • step d0 is also included: cleaning up the overflow and/or electroplating operation left over from the plastic packaging process;
  • the electroplating operation specifically includes: removing impurities and organic matter on the surface of the frame, Slightly corrode and plate a tin layer on the frame surface; then clean the chemical residue; and finally bake;
  • the step E also includes step F: testing the products to screen out inferior products in terms of performance and appearance according to the electrical performance requirements of the products, packaging the qualified products with suitable carrier tapes, cover tapes and outer packaging cartons, affixing labels containing complete product information, and then storing them in a warehouse with temperature and humidity that meet the requirements and waiting for shipment.
  • the present invention has the following beneficial effects:
  • the semiconductor device group of the present invention is arranged by arranging a metal frame and a plurality of semiconductor device units.
  • a plurality of wafer carriers are arranged in the metal frame.
  • the semiconductor device units include chips, pins and connectors.
  • the semiconductor device units are arranged in pairs, and the pins in each pair of semiconductor device units are connected.
  • the plurality of pairs of semiconductor device units are arranged in sequence along the length direction or the width direction of the metal frame, and a packaging layer is arranged along the arrangement direction of the plurality of pairs of semiconductor device units.
  • the redundant frame structure used to carry and isolate a single product unit is simplified, thereby increasing the product density on the single-piece frame, facilitating cutting and bending of exposed pins after cutting, and ensuring the design requirements of the pins for specific occasions.
  • the product density on the single-piece metal frame is significantly increased on the basis of the existing packaging density, and the increase ratio of the product density on the single-piece frame can reach 30% or more.
  • the preparation method and application of the semiconductor device of the present invention reduces the production cost by arranging and preparing the semiconductor device, and then cutting and separating it after the overall plastic packaging.
  • the separation is carried out by cutting, preferably double-sided cutting separation, which can reduce the stress of mechanical stamping and cutting, thereby improving the reliability of the product.
  • the exposed pins of the obtained single product are easy to separate by cutting, bending and cutting technology, thereby ensuring the design requirements of the pins for specific occasions.
  • FIG1 is a schematic diagram of the three-dimensional structure of a semiconductor device group according to Embodiment 1 of the present invention.
  • FIG2 is a schematic diagram of an exploded three-dimensional structure of a semiconductor device group according to Embodiment 1 of the present invention.
  • FIG3 is a partially exploded three-dimensional structural diagram of a semiconductor device group according to Embodiment 1 of the present invention.
  • FIG4 is a schematic diagram of a planar structure of a semiconductor device group according to Embodiment 1 of the present invention.
  • FIG5 is another schematic diagram of the planar structure of the semiconductor device group according to the first embodiment of the present invention.
  • FIG. 6 is a flow chart of a method for preparing a semiconductor device group according to Embodiment 2 of the present invention.
  • FIG. 7 is a flow chart of a specific implementation of a method for preparing a semiconductor device group according to Embodiment 2 of the present invention.
  • FIG. 9 is a flow chart of a specific implementation of the application of the semiconductor device group according to Embodiment 3 of the present invention.
  • FIG10 is a schematic diagram of the three-dimensional structure of a product obtained by applying the semiconductor device group according to Embodiment 3 of the present invention.
  • FIG11 is a schematic diagram of a partially exploded three-dimensional structure of a product obtained by applying the semiconductor device group according to Example 3 of the present invention.
  • Figure numerals 1. Metal frame; 11. Wafer carrier; 2. Semiconductor device unit; 21. Chip; 22. Pin; 23. Connector; 3. Packaging layer; 4. Install the chip on the metal frame; 401. Chip preparation; 402. Chip installation; 5. Install two connectors in a plurality of pairs of semiconductor device units correspondingly above the chip and arrange them along its width direction; 501. Spray solder paste on specific pin areas of the chip and the metal frame, position the pin and the copper clip above the solder paste, and then perform reflow soldering in a reflow oven; 502. Connect the pin to the chip by wire bonding; 6.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • this embodiment relates to a semiconductor device group, including a metal frame 1 and six semiconductor device units 2 ; six wafer carriers 11 are arranged in the metal frame 1 .
  • Each semiconductor device unit 2 includes a chip 21 , a plurality of pins 22 and a connector 23 connecting the chip 21 with the pins 22 .
  • the chip 21 and the pins 22 are located above the metal frame 1 .
  • the connector 23 is a copper sheet clip, and in another embodiment, the connector 23 is a welding wire, which can be any one of a gold wire, a copper wire, an aluminum wire, and an aluminum strip.
  • the chip 21 is connected to the pin 22 by wire bonding technology to electrically connect the electrode of the chip 21 and the pin 22.
  • the semiconductor device units 2 are arranged in pairs, for a total of three pairs, the chips 21 are respectively located on corresponding wafer carriers 11, the pins 22 in each pair of semiconductor device units 2 are connected, and the connectors 23 of each pair of semiconductor device units 2 are far away from each other.
  • three pairs of semiconductor device units 2 are arranged in sequence along the width direction of the semiconductor device units 2. At this time, the three pairs of semiconductor device units 2 are also arranged in sequence along the width direction of the metal frame 1.
  • Two integral packaging layers 3 are provided along the arrangement direction of the three pairs of semiconductor device units 2. The packaging layers 3 Located above the wafer stage 11 , it covers two rows of chips 21 and the connecting components 23 .
  • three pairs of semiconductor device units 2 are arranged in sequence along the width direction of the semiconductor device units 2, but at this time the three pairs of semiconductor device units 2 are arranged in sequence along the length direction of the metal frame 1, and two integral packaging layers 3 are arranged along the arrangement direction of the three pairs of semiconductor device units 2.
  • the packaging layer 3 is located above the wafer carrier 11, covering the two rows of chips 21 and the connectors 23.
  • the present invention simplifies the redundant frame structure used for carrying and isolating a single product unit through the frame layout, thereby improving the product density on the single-piece frame, and significantly improving the product density on the single-piece metal frame 1 on the basis of the existing packaging density.
  • the product density on the single-piece frame can be increased by 30% or more.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • this embodiment relates to a method for preparing a semiconductor device group, comprising the following steps:
  • Step A installing the chip 21 on the metal frame 1.
  • Step B Install two connectors 23 in a plurality of pairs of semiconductor device units 2 correspondingly above the chip 21 and arrange them along the width direction thereof.
  • Step C Plastic-encapsulate the semiconductor device unit 2 along its arrangement direction on the wafer stage 11 to encapsulate a plurality of chips 21 and connectors 23 to obtain a packaging layer 3.
  • step A specifically includes the following steps:
  • Step a1 chip 21 preparation: after receiving the wafer to be cut, first check whether there is a film on the back of the incoming wafer. If there is no film, it is necessary to paste a film on the back of the wafer.
  • step a1 After a wafer has been prepared for cutting, slotting and cutting are performed sequentially to complete the cutting process from the whole wafer to the separated independent chips 21. If the chips 21 are already prepared, step a1 can be omitted.
  • Step a2 chip 21 installation;
  • silver paste or solder paste will be sprayed on the designated area on the copper frame, and then the machine will suck up the chip 21 and place it on the silver or solder paste.
  • the machine will suck up the chip 21 and place it on the silver or solder paste.
  • an oven is required to bake and solidify the chip 21 .
  • solder paste when solder paste is sprayed on the wafer carrier 11, reflow soldering needs to be performed separately or in step B.
  • step B specifically includes the following steps:
  • Step b1 when the connecting piece 23 of the semiconductor device unit 2 is a copper clip, spray the solder paste on the specific pin area of the chip 21 and the metal frame 1, place the pin 22 and the copper clip on top of the solder paste for positioning, and then perform reflow soldering in a reflow furnace to melt the solder paste coated between the chip 21 and the metal frame 1 or between the chip 21 and the copper clip for eutectic welding.
  • Step b2 When the connecting member 23 of the semiconductor device unit 2 is a bonding wire, the pin 22 is connected to the chip 21 by a wire bonding method.
  • step b1 or step b2 can be performed, and preferably, the effect of step b1 is more excellent.
  • step C specifically includes the following steps:
  • Step c1 when the connector 23 of the semiconductor device unit 2 is a copper clip, chemical cleaning is performed; the chemical cleaning includes ultrasonic chemical reagent immersion cleaning or chemical reagent spray cleaning, which is beneficial to reduce the risk of later product stratification.
  • Step c2 plastic packaging: use a plastic packaging material to integrally plastic package a plurality of chips 21 and connectors 23 in the width direction of the semiconductor device unit 2 and perform a curing treatment to obtain an overall packaging layer 3 to obtain a semiconductor device group as shown in FIG. 1 .
  • the preparation method and application of the semiconductor device of the present invention prepare the layout of the semiconductor device, and then cut and separate the semiconductor device after the overall plastic packaging, thereby reducing the production cost.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • an application of a semiconductor device group includes the following steps:
  • Step D cutting the semiconductor device group.
  • Step E bend the outer pin 22 into shape.
  • Step d0 clean up the overflow left over from the plastic packaging process and/or electroplating operation.
  • the electroplating operation specifically includes: removing impurities and organic matter on the surface of the frame, slightly corroding the surface of the frame, plating a tin layer on the surface of the frame; then cleaning chemical residues; and finally baking.
  • Step d1 cutting off the connecting ribs of the semiconductor device group.
  • Step E bending the outer pin 22 into shape.
  • Step E can be located between steps d1 and d2 or after steps d1 and d2.
  • step E is located between steps d1 and d2, so that the outer pin 22 can be bent into shape more conveniently.
  • Step d2 cutting the encapsulation layer 3, preferably, cutting from both sides, and separating individual products from the entire encapsulation layer 3 as shown in FIGS. 10 and 11 .
  • Step F Test the products according to the electrical performance requirements and specifications of the products to remove defective products in terms of performance and appearance. Pack the qualified products with appropriate carrier tapes, cover tapes and outer packaging cartons, and affix labels containing complete product information. Then store them in a warehouse where the temperature and humidity meet the requirements and wait for shipment.
  • Separation by cutting preferably double-sided cutting, can reduce the stress of mechanical stamping and cutting, thereby improving the reliability of the product.
  • the exposed pin 22 of the obtained single product is easy to separate by cutting, bending and cutting technology, thereby ensuring that the pin 22 is used in the design requirements of specific occasions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明提供了一种半导体器件组及其制备方法与应用，涉及半导体配件制造技术领域；半导体器件组包括金属框架、半导体器件单元、载片台，半导体器件单元包括芯片、引脚、连接件；半导体器件单元两两一对，沿金属框架长度方向或宽度方向依次排列，沿半导体器件单元排列方向设置有封装层；本发明将用于承载和隔离单个产品单元的多余框架结构简化，提高单片框架上的产品密度达到30％及以上，便于切割和切割后对外露引脚打弯，便于保证引脚应用于特定场合下的设计要求；本发明的半导体器件的制备方法与应用，通过对半导体器件的布局制备，整体塑封后再进行切割分型，进而降低了生产成本，提高产品的可靠性。

Description

一种半导体器件组及其制备方法与应用 技术领域
本发明涉及半导体配件制造技术领域，尤其涉及半导体器件组及其制备方法与应用，具体涉及一种包含铜片夹扣或焊线(金线/铜线/铝线/铝带)的半导体封装层及成型和切割分离的制作方法与应用。
背景技术
目前，传统的功率半导体分立器件通常采用两种生产方式。其一是单颗注塑成型的传统塑封模式来设计模具，注塑流道和配套的金属框架连接结构。这种模具设计方法通常需要在单颗模具型腔旁边预留足够的空间来满足注塑主要和次要流道设计的需要。而这类设计中，由于必须预留主次流道空间，每个产品单元都需要单独定位和隔离，这就导致金属框架需要贡献出大量无用面积，单个产品单元在金属框架上占用的面积都较大，因此产品密度普遍不高。
另一种注塑成型的设计方法是集成模块化，即在金属框架设计时将单颗器件结构按横和竖格式化有规律地排列在一起，而配套的模具设计也是使用块状化设计。模具流道不再是与单颗器件连接而是通过块状化设计(多颗器件集成在一起)相互连接，从而提高产品在单一金属框架上的单位密度，但又限制了产品器件的外形要求。并且由于是采用刀片切割的方法来分离各个器件，所以器件引脚的外暴露只能是和器件的切割面保持同一平面，从而限制了器件在特定应用场合下的使用。
发明内容
针对现有技术中的缺陷，本发明的目的一是提供一种可以简化用于承载和隔离单个产品单元的多余框架结构，提高单片框架上的产品密度，降低了生产 成本，提高产品的可靠性，便于保证引脚打弯应用于特定场合下的设计要求的半导体器件组。本发明的目的一是通过以下技术方案实现的：一种半导体器件组，包括金属框架、若干半导体器件单元；所述金属框架内设置若干载片台；
所述半导体器件单元包括芯片、引脚以及连接件，所述芯片、引脚位于金属框架上方，所述连接件用于使芯片的电极和引脚电连接；
所述半导体器件单元两两一对，所述芯片分别位于对应的载片台上，每对半导体器件单元中的引脚相连接，每对半导体器件单元的连接件相互远离；
若干对半导体器件单元沿着金属框架的长度方向或宽度方向依次排列，沿若干对所述半导体器件单元排列方向设置有封装层，所述封装层位于载片台上方。
进一步地，所述连接件包括铜片夹扣或焊线。
进一步地，所述焊线包括金线、铜线、铝线、铝带中的一种或多种。
本发明的目的二是提供一种半导体器件组的制备方法，本发明的目的二是通过以下技术方案实现的：一种半导体器件组的制备方法，包括如下步骤：
A、将芯片安装在金属框架上；
B、将若干对半导体器件单元中两个连接件在芯片上方对应安装并沿其宽度方向排列；
C、将半导体器件单元沿其排列方向在载片台上方将若干芯片、连接件整体塑封得到封装层。
进一步地，所述步骤A具体包括如下步骤：
a1、芯片制备；检查晶圆背面是否有贴膜，如果是，则进行晶圆切割；如果否，则在晶圆背面贴膜后进行晶圆切割得到芯片；
a2、芯片安装；将银浆或焊锡膏喷涂于载片台，然后将芯片置于银浆或焊锡膏上方；当喷涂于载片台的是银浆时，需要使用烘箱烘烤固化芯片；当喷涂于载片台的是焊锡膏时需要单独进行回流焊或在步骤B中进行回流焊。
进一步地，所述步骤B具体包括如下步骤：
b1、当所述半导体器件单元的连接件为铜片夹扣时，将焊锡膏喷涂于芯片和金属框架的管脚特定区域上，将引脚以及铜片夹扣置于焊锡膏上方进行定位，然后在回流炉内进行回流焊，使涂覆于芯片和金属框架之间或芯片与铜片夹扣之间的焊锡膏熔融共晶焊接；
b2、当所述半导体器件单元的连接件为焊线时，通过打线方法将引脚与芯片相连接。
进一步地，所述步骤C具体包括如下步骤：
c1、当所述半导体器件单元的连接件为铜片夹扣时进行化学清洗；所述化学清洗包括通过超声化学试剂浸泡清洗或喷淋化学试剂清洗；
c2、塑封；使用塑封料对半导体器件单元宽度方向的若干芯片、连接件进行整体塑封并固化处理得到整体封装层。
本发明的目的三是提供一种半导体器件组的应用，本发明的目的三是通过以下技术方案实现的：一种半导体器件组的应用，包括步骤D和步骤E：
D、将半导体器件组的进行切割；
E、将外引脚打弯成型。
所述切割优选为双面切割分离。
进一步地，所述步骤D具体包括如下步骤：
d1、将半导体器件组的连筋切断；
d2、将封装层进行切割，从整体封装层分离出单个的产品；
所述步骤E具体包括如下步骤：将引脚打弯成型所需形状；所述步骤E位于步骤d1、d2之间或步骤d1、d2之后。
进一步地，所述步骤d1之前还包括步骤d0：清除掉塑封过程留下的溢料和/或电镀操作；
所述电镀操作具体包括：去除框架表面的杂质和有机物，对框架表面部位 轻微腐蚀，在框架表面镀上锡层；然后清洗化学残留；最后进行烘烤；
所述步骤E之后还包括步骤F：根据产品的电性能要求规范，对产品进行测试筛除性能次品、外观次品，将合格产品选择合适的载带和盖带以及外包装纸箱进行包装，并贴上包含完整产品信息的标签，然后放入温湿度符合要求的仓库进行保存并等待出货。
与现有技术相比，本发明具有如下的有益效果：
(1)本发明的半导体器件组通过布局设置金属框架、若干半导体器件单元，金属框架内设置若干载片台，半导体器件单元包括芯片、引脚以及连接件；半导体器件单元两两一对，每对半导体器件单元中的引脚相连接，若干对半导体器件单元沿着金属框架的长度方向或宽度方向依次排列，沿若干对所述半导体器件单元排列方向设置有封装层；将用于承载和隔离单个产品单元的多余框架结构简化，从而提高单片框架上的产品密度，便于切割和切割后对外露引脚打弯，便于保证引脚应用于特定场合下的设计要求；在现有封装密度的基础上显著提高单片金属框架上的产品密度，单片框架上的产品密度提高比例能达到30％及以上；
(2)本发明的半导体器件的制备方法与应用通过对半导体器件的布局制备，整体塑封后再进行切割分型，进而降低了生产成本，通过切割的方法进行分离，优选双面切割分离，可以减少机械冲压切断的应力，从而提高产品的可靠性，得到的单个产品外露引脚便于通过切筋，打弯和切断的分离技术，进而保证引脚应用于特定场合下的设计要求。
附图说明
图1为本发明实施例1半导体器件组的立体结构示意图；
图2为本发明实施例1半导体器件组的爆炸立体结构示意图；
图3为本发明实施例1半导体器件组的部分爆炸立体结构示意图；
图4为本发明实施例1半导体器件组的平面结构示意图；
图5为本发明实施例1半导体器件组的另一种平面结构示意图；
图6为本发明实施例2半导体器件组的制备方法的流程图；
图7为本发明实施例2半导体器件组的制备方法的具体实施方式的流程图；
图8为本发明实施例3半导体器件组的应用的流程图；
图9为本发明实施例3半导体器件组的应用的具体实施方式的流程图；
图10为本发明实施例3半导体器件组的应用得到产品的立体结构示意图；
图11为本发明实施例3半导体器件组的应用得到产品的部分爆炸立体结构示意图；
附图标记：1、金属框架；11、载片台；2、半导体器件单元；21、芯片；22、引脚；23、连接件；3、封装层；4、将芯片安装在金属框架上；401、芯片制备；402、芯片安装；5、将若干对半导体器件单元中两个连接件在芯片上方对应安装并沿其宽度方向排列；501、将焊锡膏喷涂于芯片和金属框架的管脚特定区域上，将引脚以及铜片夹扣置于焊锡膏上方进行定位，然后在回流炉内进行回流焊；502、通过打线方法将引脚与芯片相连接；6、将半导体器件单元沿其排列方向在载片台上方将若干芯片、连接件整体塑封得到封装层；601、化学清洗；602、塑封；7、将半导体器件组的进行切割；701、清除掉塑封过程留下的溢料和/或电镀操作；702、将半导体器件组的连筋切断；703、将封装层进行切割，从整体封装层分离出单个的产品；8、将外引脚打弯成型；9、测试筛除性能次品、外观次品，将合格产品选择合适的载带和盖带以及外包装纸箱进行包装，并贴上包含完整产品信息的标签，然后放入温湿度符合要求的仓库进行保存并等待出货。
具体实施方式
以下实施例将有助于本领域的技术人员进一步理解本发明，但不以任何形式限制本发明。在以下描述中，为了清楚展示本发明的结构及工作方式，将借助诸多方向性词语进行描述，但是应当将“前”、“后”、“左”、“右”、 “外”、“内”、“向外”、“向内”、“上”、“下”等词语理解为方便用语，而不应当理解为限定性词语。本文中的“远段”、“远端”、“近段”和“近端”中的“远”和“近”是相对于操作者的位置来讲，即靠近操作者为“近”，远离操作者为“远”。
对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变化和改进，这些都属于本发明的保护范围。在本文中所披露的范围的端点和任何值都不限于该精确的范围或值，这些范围或值应当理解为包含接近这些范围或值的值。对于数值范围来说，各个范围的端点值之间、各个范围的端点值和单独的点值之间，以及单独的点值之间可以彼此组合而得到一个或多个新的数值范围，这些数值范围应被视为在本文中具体公开，下面结合具体实施例对本发明进行详细说明：
实施例1：
如图1、图2所示，本实施例涉及一种半导体器件组，包括一个金属框架1、6个半导体器件单元2；金属框架1内设置6个载片台11。
每个半导体器件单元2包括1个芯片21、若干引脚22以及将芯片21与引脚22相连接的连接件23，芯片21、引脚22位于金属框架1上方。
如图3所示，在一个具体的实施例中连接件23为铜片夹扣，在另一个实施例中连接件23为焊线，焊线可以为金线、铜线、铝线、铝带中任意一种，通过打线技术将芯片21与引脚22相连接，用于使芯片21的电极和引脚22电连接。
在一个具体实施例中，半导体器件单元2两两一对，共分为3对，芯片21分别位于对应的载片台11上，每对半导体器件单元2中的引脚22相连接，每对半导体器件单元2的连接件23相互远离。
如图4所示，3对半导体器件单元2沿着半导体器件单元2的宽度方向依次排列，此时3对半导体器件单元2亦是沿着金属框架1的宽度方向依次排列的，沿3对半导体器件单元2排列方向设置有两条整体的封装层3，封装层3 位于载片台11上方，将两列芯片21与连接件23包覆。
如图5所示，在另一个具体实施例中，3对半导体器件单元2沿着半导体器件单元2的宽度方向依次排列，但此时3对半导体器件单元2是沿着金属框架1的长度方向依次排列的，沿3对半导体器件单元2排列方向设置有两条整体的封装层3，封装层3位于载片台11上方，将两行芯片21与连接件23包覆。
本发明通过框架布局将用于承载和隔离单个产品单元的多余框架结构简化，从而提高单片框架上的产品密度，在现有封装密度的基础上显著提高单片金属框架1上的产品密度，单片框架上的产品密度提高比例能达到30％及以上，同时便于切割和切割后对外露引脚22打弯，便于保证引脚22应用于特定场合下的设计要求。
实施例2：
如图6所示，本实施例涉及一种半导体器件组的制备方法，包括如下步骤：
步骤A、将芯片21安装在金属框架1上。
步骤B、将若干对半导体器件单元2中两个连接件23在芯片21上方对应安装并沿其宽度方向排列。
步骤C、将半导体器件单元2沿其排列方向在载片台11上方将若干芯片21、连接件23整体塑封得到封装层3。
如图7所示，在一个具体实施例中，步骤A具体包括如下步骤：
步骤a1、芯片21制备；当收到需要切割的晶圆后，先检查晶圆来料背面是否有贴膜。如果没有贴膜，需要在晶圆背面贴膜。
当一片晶圆作好各项切割前的准备工作后，开始依次进行开槽切割，完成从整片晶圆到被分离的独立芯片21的切割过程。如果有已经准备好芯片21则可以省略该步骤a1。
步骤a2、芯片21安装；在芯片21贴装工序，会先将银浆或焊锡膏喷涂于铜框架之上的指定区域，然后机台会将芯片21吸起后将其放置于银奖或焊锡膏 上方。
在一个实施例中，当喷涂于载片台11的是银浆时，需要使用烘箱烘烤固化芯片21。
在另一个实施例中，当喷涂于载片台11的是焊锡膏时需要单独进行回流焊或在步骤B中进行回流焊。
在一个具体实施例中，步骤B具体包括如下步骤：
步骤b1、当所述半导体器件单元2的连接件23为铜片夹扣时，将焊锡膏喷涂于芯片21和金属框架1的管脚特定区域上，将引脚22以及铜片夹扣置于焊锡膏上方进行定位，然后在回流炉内进行回流焊，使涂覆于芯片21和金属框架1之间或芯片21与铜片夹扣之间的焊锡膏熔融共晶焊接。
步骤b2、当所述半导体器件单元2的连接件23为焊线时，通过打线方法将引脚22与芯片21相连接。
步骤b1与步骤b2择一进行即可，优选的，步骤b1的效果更加优异。
在一个具体实施例中，步骤C具体包括如下步骤：
步骤c1、当所述半导体器件单元2的连接件23为铜片夹扣时进行化学清洗；所述化学清洗包括通过超声化学试剂浸泡清洗或喷淋化学试剂清洗，有利于降低后期产品分层的风险。
步骤c2、塑封；使用塑封料对半导体器件单元2宽度方向的若干芯片21、连接件23进行整体塑封并固化处理得到整体封装层3得到如图1所示的半导体器件组。
本发明的半导体器件的制备方法与应用通过对半导体器件的布局制备，整体塑封后再进行切割分型，进而降低了生产成本。
实施例3：
如图8所示，一种半导体器件组的应用，包括如下步骤：
步骤D、将半导体器件组的进行切割。
步骤E、将外引脚22打弯成型。
如图9所示，在一个具体实施例中，具体包括如下步骤：
步骤d0、清除掉塑封过程留下的溢料和/或电镀操作。
所述电镀操作具体包括：去除框架表面的杂质和有机物，对框架表面部位轻微腐蚀，在框架表面镀上锡层；然后清洗化学残留；最后进行烘烤。
步骤d1、将半导体器件组的连筋切断。
步骤E、将外引脚22打弯成型。其中，步骤E位于步骤d1、d2之间或步骤d1、d2之后均可。优选的，步骤E位于步骤d1、d2之间为宜，外引脚22打弯成型更加方便。
步骤d2、将封装层3进行切割，优选的，从双面进行切割，从整体封装层3分离出单个的产品如图10、图11所示。
步骤F、根据产品的电性能要求规范，对产品进行测试筛除性能次品、外观次品，将合格产品选择合适的载带和盖带以及外包装纸箱进行包装，并贴上包含完整产品信息的标签，然后放入温湿度符合要求的仓库进行保存并等待出货。
通过切割的方法进行分离，优选双面切割分离，可以减少机械冲压切断的应力，从而提高产品的可靠性，得到的单个产品外露引脚22便于通过切筋，打弯和切断的分离技术，进而保证引脚22应用于特定场合下的设计要求。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变化或修改，这并不影响本发明的实质内容。在不冲突的情况下，本申请的实施例和实施例中的特征可以任意相互组合。

Claims (10)

  1. 一种半导体器件组，其特征在于，包括金属框架(1)、若干半导体器件单元(2)；所述金属框架(1)内设置若干载片台(11)；
    所述半导体器件单元(2)包括芯片(21)、引脚(22)以及连接件(23)，所述芯片(21)、引脚(22)位于金属框架(1)上方，所述连接件(23)用于使芯片(21)的电极和引脚(22)电连接；
    所述半导体器件单元(2)两两一对，所述芯片(21)分别位于对应的载片台(11)上，每对半导体器件单元(2)中的引脚(22)相连接，每对半导体器件单元(2)的连接件(23)相互远离；
    若干对半导体器件单元(2)沿着金属框架(1)的长度方向或宽度方向依次排列，沿若干对所述半导体器件单元(2)排列方向设置有封装层(3)，所述封装层(3)位于载片台(11)上方。
  2. 根据权利要求1所述的半导体器件组，其特征在于，所述连接件(23)包括铜片夹扣或焊线。
  3. 根据权利要求2所述的半导体器件组，其特征在于，所述焊线包括金线、铜线、铝线、铝带中的一种或多种。
  4. 一种半导体器件组的制备方法，其特征在于，包括如下步骤：
    A、将芯片(21)安装在金属框架(1)上；
    B、将若干对半导体器件单元(2)中两个连接件(23)在芯片(21)上方对应安装并沿其宽度方向排列；
    C、将半导体器件单元(2)沿其排列方向在载片台(11)上方将若干芯片(21)、连接件(23)整体塑封得到封装层(3)。
  5. 根据权利要求4所述的半导体器件组的制备方法，其特征在于，所述步骤A具体包括如下步骤：
    a1、芯片(21)制备；检查晶圆背面是否有贴膜，如果是，则进行晶圆切割；如果否，则在晶圆背面贴膜后进行晶圆切割得到芯片(21)；
    a2、芯片(21)安装；将银浆或焊锡膏喷涂于载片台(11)，然后将芯片(21)置 于银浆或焊锡膏上方；当喷涂于载片台(11)的是银浆时，需要使用烘箱烘烤固化芯片(21)；当喷涂于载片台(11)的是焊锡膏时需要单独进行回流焊或在步骤B中进行回流焊。
  6. 根据权利要求4所述的半导体器件组的制备方法，其特征在于，所述步骤B具体包括如下步骤：
    b1、当所述半导体器件单元(2)的连接件(23)为铜片夹扣时，将焊锡膏喷涂于芯片(21)和金属框架(1)的管脚特定区域上，将引脚(22)以及铜片夹扣置于焊锡膏上方进行定位，然后在回流炉内进行回流焊，使涂覆于芯片(21)和金属框架(1)之间或芯片(21)与铜片夹扣之间的焊锡膏熔融共晶焊接；
    b2、当所述半导体器件单元(2)的连接件(23)为焊线时，通过打线方法将引脚(22)与芯片(21)相连接。
  7. 根据权利要求4所述的半导体器件组的制备方法，其特征在于，所述步骤C具体包括如下步骤：
    c1、当所述半导体器件单元(2)的连接件(23)为铜片夹扣时进行化学清洗；所述化学清洗包括通过超声化学试剂浸泡清洗或喷淋化学试剂清洗；
    c2、塑封；使用塑封料对半导体器件单元(2)宽度方向的若干芯片(21)、连接件(23)进行整体塑封并固化处理得到整体封装层(3)。
  8. 一种半导体器件组的应用，其特征在于，包括步骤D和步骤E：
    D、将半导体器件组的进行切割；
    E、将外引脚(22)打弯成型。
  9. 根据权利要求8所述的半导体器件组的应用，其特征在于，所述步骤D具体包括如下步骤：
    d1、将半导体器件组的连筋切断；
    d2、将封装层(3)进行切割，从整体封装层(3)分离出单个的产品；
    所述步骤E具体包括如下步骤：将引脚(22)打弯成型所需形状；所述步骤E位于步骤d1、d2之间或步骤d1、d2之后。
  10. 根据权利要求9所述的半导体器件组的应用，其特征在于，所述步骤d1之前还包括步骤d0：清除掉塑封过程留下的溢料和/或电镀操作；
    所述电镀操作具体包括：去除框架表面的杂质和有机物，对框架表面部位轻微腐蚀，在框架表面镀上锡层；然后清洗化学残留；最后进行烘烤；
    所述步骤E之后还包括步骤F：根据产品的电性能要求规范，对产品进行测试筛除性能次品、外观次品，将合格产品选择合适的载带和盖带以及外包装纸箱进行包装，并贴上包含完整产品信息的标签，然后放入温湿度符合要求的仓库进行保存并等待出货。
PCT/CN2023/107418 2023-01-06 2023-07-14 一种半导体器件组及其制备方法与应用 WO2024078079A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202310015717.2 2023-01-06
CN202310015717.2A CN116230648A (zh) 2023-01-06 2023-01-06 一种半导体器件组及其制备方法与应用

Publications (1)

Publication Number Publication Date
WO2024078079A1 true WO2024078079A1 (zh) 2024-04-18

Family

ID=86574144

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/107418 WO2024078079A1 (zh) 2023-01-06 2023-07-14 一种半导体器件组及其制备方法与应用

Country Status (2)

Country Link
CN (1) CN116230648A (zh)
WO (1) WO2024078079A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118099124A (zh) * 2024-04-19 2024-05-28 深圳市美彩光电有限公司 一种高速光电耦合器及与该配套设置的引线框架

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116230648A (zh) * 2023-01-06 2023-06-06 重庆万国半导体科技有限公司 一种半导体器件组及其制备方法与应用

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102082100A (zh) * 2009-11-30 2011-06-01 万国半导体有限公司 一种用于引脚凸出的半导体器件的封装方法
US20130017649A1 (en) * 2009-11-25 2013-01-17 Stmicroelectronics (Tours) Sas Packaging for clip-assembled electronic components
CN109545769A (zh) * 2018-11-15 2019-03-29 佛山市蓝箭电子股份有限公司 硅芯片封装引线框架及其封装方法
CN109904077A (zh) * 2019-01-21 2019-06-18 深圳赛意法微电子有限公司 多管脚半导体产品的封装方法
CN111524868A (zh) * 2020-03-25 2020-08-11 长电科技（宿迁）有限公司 一种引线框架和金属夹片的组合结构及铆接装片工艺
CN215578542U (zh) * 2021-04-01 2022-01-18 长电科技（宿迁）有限公司 一种引线框架和管脚夹片的弹性锁口连接结构
CN217544605U (zh) * 2022-05-31 2022-10-04 广东钜芯半导体科技有限公司 一种d2pak引线框架
CN116230648A (zh) * 2023-01-06 2023-06-06 重庆万国半导体科技有限公司 一种半导体器件组及其制备方法与应用

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130017649A1 (en) * 2009-11-25 2013-01-17 Stmicroelectronics (Tours) Sas Packaging for clip-assembled electronic components
CN102082100A (zh) * 2009-11-30 2011-06-01 万国半导体有限公司 一种用于引脚凸出的半导体器件的封装方法
CN109545769A (zh) * 2018-11-15 2019-03-29 佛山市蓝箭电子股份有限公司 硅芯片封装引线框架及其封装方法
CN109904077A (zh) * 2019-01-21 2019-06-18 深圳赛意法微电子有限公司 多管脚半导体产品的封装方法
CN111524868A (zh) * 2020-03-25 2020-08-11 长电科技（宿迁）有限公司 一种引线框架和金属夹片的组合结构及铆接装片工艺
CN215578542U (zh) * 2021-04-01 2022-01-18 长电科技（宿迁）有限公司 一种引线框架和管脚夹片的弹性锁口连接结构
CN217544605U (zh) * 2022-05-31 2022-10-04 广东钜芯半导体科技有限公司 一种d2pak引线框架
CN116230648A (zh) * 2023-01-06 2023-06-06 重庆万国半导体科技有限公司 一种半导体器件组及其制备方法与应用

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118099124A (zh) * 2024-04-19 2024-05-28 深圳市美彩光电有限公司 一种高速光电耦合器及与该配套设置的引线框架

Also Published As

Publication number Publication date
CN116230648A (zh) 2023-06-06

Similar Documents

Publication Publication Date Title
US4514750A (en) Integrated circuit package having interconnected leads adjacent the package ends
CN207781575U (zh) 经封装的电子装置
CN102789994B (zh) 侧面可浸润半导体器件
EP0730781B1 (en) A lead frame having layered conductive planes
WO2024078079A1 (zh) 一种半导体器件组及其制备方法与应用
CN109817769B (zh) 一种新型led芯片封装制作方法
JPH0785499B2 (ja) 同時ボンディング作業に適した集積回路リ−ドフレ−ム
JPH0828455B2 (ja) リードフレーム及びそれを用いた電子部品の製造方法
WO2024078077A1 (zh) 一种金属夹扣组及半导体器件组及其制备方法与应用
CN102315135B (zh) 芯片封装及其制作工艺
CN107749399B (zh) 一种功率芯片封装方法和结构
US7768104B2 (en) Apparatus and method for series connection of two die or chips in single electronics package
US8222088B2 (en) Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
TWI380379B (en) Package structure and manufacturing method thereof
CN110211932A (zh) 一种柔性芯片封装结构及制造方法
KR20120138779A (ko) 태양 전지 조립체 ⅱ
JPH08264819A (ja) 半導体装置及び該製造方法
CN104112811B (zh) 一种led的封装方法
JPH06318615A (ja) 集積回路
JP3691790B2 (ja) 半導体装置の製造方法及び該方法によって製造された半導体装置
CN109979825A (zh) 阵列批次式封装元件晶粒的电路元件制作方法
JP2875591B2 (ja) 半導体装置及びその製造方法
JPH03220761A (ja) 半導体装置
TW200529383A (en) Electrode package for semiconductor device
KR930010075B1 (ko) 집적 회로용 리드프레임 및 소켓

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23866633

Country of ref document: EP

Kind code of ref document: A1