CN102789994B - 侧面可浸润半导体器件 - Google Patents
侧面可浸润半导体器件 Download PDFInfo
- Publication number
- CN102789994B CN102789994B CN201110162405.1A CN201110162405A CN102789994B CN 102789994 B CN102789994 B CN 102789994B CN 201110162405 A CN201110162405 A CN 201110162405A CN 102789994 B CN102789994 B CN 102789994B
- Authority
- CN
- China
- Prior art keywords
- lead frame
- pin
- semiconductor device
- substrate panel
- coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 33
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000005520 cutting process Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000011248 coating agent Substances 0.000 claims abstract description 13
- 238000000576 coating method Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims description 15
- 238000004070 electrodeposition Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- YQOLEILXOBUDMU-KRWDZBQOSA-N (4R)-5-[(6-bromo-3-methyl-2-pyrrolidin-1-ylquinoline-4-carbonyl)amino]-4-(2-chlorophenyl)pentanoic acid Chemical compound CC1=C(C2=C(C=CC(=C2)Br)N=C1N3CCCC3)C(=O)NC[C@H](CCC(=O)O)C4=CC=CC=C4Cl YQOLEILXOBUDMU-KRWDZBQOSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 229940125844 compound 46 Drugs 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000002372 labelling Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
从引线框架或基板面板装配侧面可浸润半导体器件:用第一切割工具至少部分地底切引线框架或基板面板,以暴露引线框架的侧面;以及在将引线框架或基板面板切单为单个半导体器件之前,向暴露侧面施加锡或锡合金的涂敷。该方法包括在施加锡或锡合金涂敷之前,电互连与相邻半导体器件关联的引线框架侧面。引线框架侧面可以在丝线键合过程中被电气互连。
Description
技术领域
本发明涉及半导体封装并且特别地涉及一种半导体器件,其具有焊料可浸润侧壁或侧面,以便于在使用表面安装技术(SMT)工艺将半导体器件安装在基板或电路板上时检查焊点。
背景技术
由于诸如QFN(四方扁平无引脚)封装的半导体器件采用划片刀切单的方式,使得暴露的引线框架侧面的表面与模制化合物平齐,从而焊料不容易攀附或“吸附”在封装的侧面或侧壁,这意味着QFN封装不是侧面可浸润的。
图1是装配QFN器件的常规装配工艺的流程图。该常规工艺包括晶圆安装和划片步骤10,随后是管芯键合步骤11以及丝线键合步骤12,在步骤11中,管芯键合到引线框架的标志处,在丝线键合步骤12中,管芯电连接到引线框架的引脚。引线框架通常由铜形成并可以镀有其他金属,如钯(PPF)或者银(Ag)。在丝线键合步骤中,利用键合丝线将管芯键合焊盘与引线框架焊盘连接。所述键合丝线可以是金、铜、铝等等。之后将该组件在步骤13中用模制化合物进行包封,随后是激光标记或去胶带(de-tape)步骤14。如果采用了镀银引线框架,则在步骤15中进行进一步的镀锡或锡合金(Sn)。最后,单个QFN器件通过切单步骤16形成。然后视检切单后的QFN器件并封装用于装运。
图2是诸如经由上述方法利用铜引线框架组装的常规QFN器件的部分截面图。由于暴露但是与QFN器件的侧壁平齐的未处理的铜表面20,使得QFN器件在其侧面是不可浸润的。
鉴于上述,需要一种QFN器件,其在侧壁或侧面是焊料可浸润的,以便于在使用SMT工艺将封装安装到诸如印刷电路板(PCB)时检查焊点。
附图说明
结合附图将更好地理解本发明的优选实施例的以下详细描述。通过示例的形式示出本发明,并且本发明不限于附图。在附图中,相似的附图标记指代相似的元件。应该认识到附图并非按比例的,并且为了容易理解而对本发明进行了简化。
图1是用于装配QFN半导体器件的常规工艺的流程图;
图2是由图1的工艺制造的常规QFN器件的局部扩大截面图;
图3是根据本发明的装配QFN半导体器件的工艺的流程图;
图4-7示出了由图3的工艺装配的QFN器件的放大截面图;以及
图8示出了由图3的工艺装配的QFN器件的放大截面图。
发明内容
根据本发明,提供一种用于制造侧面可浸润的半导体器件的工艺,包括:提供引线框架或基板面板;使用第一切割工具部分至少部分地底切引线框架或基板面板以暴露所述引线框架的侧面;以及在将引线框架或基板面板切单为单个半导体器件之前,向所述暴露的侧面施加锡或锡合金的涂敷。
该工艺可以包括在施加锡或锡合金涂敷之前,电气互连与相邻半导体器件关联的引线框架侧面。引线框架侧面可以通过丝线键合步骤进行电气互连。
该工艺可以包括将基板面板切单为单个半导体器件,其中切单步骤包括用第二切割工具切割基板面板来将面板分离为单个半导体器件。第二切割工具优选地比第一切割工具窄。锡涂敷可以通过电镀或电沉积来执行。
本发明还提供一种由上述方法装配的划片QFN半导体器件。
具体实施方式
现在参考图3,根据本发明的装配QFN半导体器件的工艺包括晶圆安装和划片步骤30,随后是管芯键合步骤31。步骤30和31相当于参考图1描述的常规工艺的步骤10和11,并且因此是本领域公知的。
步骤31之后是丝线键合步骤32,其与常规丝线键合步骤12的不同之处在于不但将管芯键合焊盘连接到引线框架的引脚,还采用连接丝线电气互连相邻QFN器件之间的引线框架引脚。
图4示出了丝线键合步骤32,其示出了连接丝线40、41将相邻管芯42、43上的管芯键合焊盘连接到引线框架44的引脚44a和44b。图4还示出电气互连引脚44a和44b的附加连接丝线45。引脚44a和44b将在切单步骤37之后形成相邻QFN器件的引脚,将在下面描述切单步骤37,其将引线框架面板分离为单个半导体器件。附加连接丝线45的目的在于在镀锡步骤36过程中将引脚44a和44b保持在相似的电势。
丝线键合步骤32之后是包封或模制步骤33,其中和现有技术一样,利用模制化合物46覆盖引线框架和管芯组件。在模制步骤33之后,执行激光标记或去胶带(de-tape)步骤34。步骤33和34相当于参考图1描述的常规工艺中的步骤13和14。
步骤34之后是第一划片步骤35,在该步骤中,附加连接丝线45下面的引线框架的材料(例如铜)被切除。连接丝线45和模制化合物46没有被分离,从而半导体面板具有用于处理的足够的硬度。划片步骤35是使得将面板切单为单个半导体器件的两步划片工艺中的第一步。划片步骤35通过第一切割工具来执行,以部分地底切半导体面板以形成如图5所示的部分底切50。部分底切50基本上将引线框架44分离为引脚或者引脚指44a和44b,其将形成相邻QFN器件的引脚。尽管底切50将引线框架44分离以形成两个引脚44a和44b时,其并没有切断连接丝线45,这用于确保引脚44a和44b在下面描述的之后的镀锡步骤36中保持电互连。
图6示出通过电镀或电沉积工艺进行的镀锡步骤36,其间,包括通过底切50暴露的引脚44a和44b的端部或边缘的引线框架44(例如铜)被涂敷有锡(Sn)或诸如用于非绿(non-green)器件的锡/铅合金的锡合金的层60。引脚44a和44b连接到电势源,从而在电镀或电沉积工艺中将形成阴极。电镀或电沉积工艺使得锡或锡合金的层60沉积在引线框架44的暴露的表面(例如铜)上。锡/锡合金的层60赋予了诸如SMT的焊接工艺中的可焊性或焊料可浸润性,并且保护引线框架44的暴露表面不被腐蚀。引线框架44在键合表面(背面是裸铜)通常预镀有银,因为通常预镀钯并随后镀锡或者锡合金是不经济的。
在镀锡步骤36之后,在步骤37中诸如利用划片将半导体面板切单为单个半导体器件(也参见图7)。在本发明的一个实施例中,切单步骤37采用比用于形成部分底切50的第一切割工具窄的第二切割工具(如,划片刀)来执行。采用更窄的切割工具的原因在于避免干扰引脚44a和44b的锡涂层60或再次暴露材料(例如铜)。第二切割工具需要精确的对准或者定位以避免干扰在镀锡步骤36中施加的涂层60。镀锡步骤36也可以采用化学方法,但是电镀或电沉积由于目前是更经济的从而是优选的。之后对切单的QFN器件进行检查并且封装以装运。
图8示出通过本发明的工艺制造的QFN器件,其采用SMT工艺安装到印刷电路板,可以清楚地看到锡涂层60之上的焊点80,这便于检查。即,由于步骤35和36中的第一切割和镀工艺,使得在焊接过程中,焊料将容易地流到引脚44a和44b的暴露的侧面上,并且因而在SMT后,能够通过视检容易地检查焊料连接。
从前述描述清楚地看出,本发明提供了一种制造侧面可浸润半导体器件的方法。虽然已经示出并且描述了本发明的优选实施例,但应该清楚的是,本发明不只限于这些实施例。在不偏离由权利要求限定的本发明的精神和范围的情况下,本领域技术人员可以进行各种修改、改变、变化、替换和等效。
Claims (7)
1.一种装配侧面可浸润半导体器件的方法,包括:
提供引线框架或基板面板,所述引线框架或基板面板包括多个管芯贴附标志,并且其中,每一所述管芯贴附标志被多个电接触焊盘围绕;
将半导体管芯贴附到所述管芯贴附标志;
利用第一键合丝线将所述半导体管芯上的键合焊盘与围绕其上贴附所述半导体管芯的所述管芯贴附标志的所述电接触焊盘电连接;
使用多个附加键合丝线电连接相邻器件的电接触焊盘;
采用第一切割工具至少部分地底切所述引线框架或基板面板,以暴露所述引线框架或基板面板的所述电接触焊盘侧面;
向所述暴露的侧面施加锡或锡合金的涂敷;以及
在施加所述涂敷之后,将所述引线框架或基板面板切单为单个半导体器件,其中,所述切单包括切割所述附加键合引线以使得相邻器件的所述电接触焊盘不再相互电连接。
2.根据权利要求1所述的方法,其中,所述切单包括用第二切割工具切割所述引线框架或基板面板以将所述引线框架或基板面板分离为所述单个半导体器件。
3.根据权利要求2所述的方法,其中,所述第二切割工具比所述第一切割工具窄。
4.根据权利要求1所述的方法,其中,通过电镀或者电沉积执行所述锡涂敷。
5.一种根据权利要求1所述的方法装配的QFN半导体器件。
6.一种侧面可浸润QFN半导体器件,包括:
包括多个引脚的引线框架;
被所述多个引脚围绕的半导体管芯,其中,引脚通过第一键合丝线电连接到管芯的管芯键合焊盘;
贴附到所述多个引脚的附加键合丝线,其中,在将所述半导体器件与相邻器件分离之前,所述附加键合丝线将所述多个引脚电连接到所述相邻器件的各个相应引脚;
模制化合物,所述模制化合物包封管芯、引脚和第一键合丝线,其中,引脚的末端沿着器件的侧壁暴露;
位于引脚的暴露部分上的锡或者锡合金的涂敷,其中,在装配期间,在将所述器件与相邻器件分离之前将所述涂敷施加到引脚的暴露部分。
7.根据权利要求6所述的侧面可浸润QFN半导体器件,其中,通过电镀或者电沉积将所述涂敷施加到引脚的暴露部分。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110162405.1A CN102789994B (zh) | 2011-05-18 | 2011-05-18 | 侧面可浸润半导体器件 |
US13/462,827 US8685795B2 (en) | 2011-05-18 | 2012-05-03 | Flank wettable semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110162405.1A CN102789994B (zh) | 2011-05-18 | 2011-05-18 | 侧面可浸润半导体器件 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102789994A CN102789994A (zh) | 2012-11-21 |
CN102789994B true CN102789994B (zh) | 2016-08-10 |
Family
ID=47155366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110162405.1A Active CN102789994B (zh) | 2011-05-18 | 2011-05-18 | 侧面可浸润半导体器件 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8685795B2 (zh) |
CN (1) | CN102789994B (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9034697B2 (en) * | 2011-07-14 | 2015-05-19 | Freescale Semiconductor, Inc. | Apparatus and methods for quad flat no lead packaging |
DE102011112659B4 (de) | 2011-09-06 | 2022-01-27 | Vishay Semiconductor Gmbh | Oberflächenmontierbares elektronisches Bauelement |
US20140357022A1 (en) * | 2013-06-04 | 2014-12-04 | Cambridge Silicon Radio Limited | A qfn with wettable flank |
CN103730441A (zh) * | 2013-12-16 | 2014-04-16 | 上海凯虹科技电子有限公司 | 引线框架以及使用该引线框架的半导体器件的封装方法 |
EP2980845B1 (en) * | 2014-08-01 | 2019-11-27 | Nexperia B.V. | A leadless semiconductor package and method |
US20160148877A1 (en) * | 2014-11-20 | 2016-05-26 | Microchip Technology Incorporated | Qfn package with improved contact pins |
US20160172275A1 (en) | 2014-12-10 | 2016-06-16 | Stmicroelectronics S.R.L. | Package for a surface-mount semiconductor device and manufacturing method thereof |
CN105895611B (zh) | 2014-12-17 | 2019-07-12 | 恩智浦美国有限公司 | 具有可湿性侧面的无引线方形扁平半导体封装 |
KR20160124328A (ko) * | 2015-04-16 | 2016-10-27 | 삼성전기주식회사 | 칩 부품 및 그 제조방법 |
US10366948B2 (en) * | 2016-03-17 | 2019-07-30 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10930581B2 (en) * | 2016-05-19 | 2021-02-23 | Stmicroelectronics S.R.L. | Semiconductor package with wettable flank |
CN106024750B (zh) * | 2016-07-14 | 2018-11-23 | 江阴芯智联电子科技有限公司 | 一种低测试成本的金属引线框结构及其制造方法 |
US9847283B1 (en) | 2016-11-06 | 2017-12-19 | Nexperia B.V. | Semiconductor device with wettable corner leads |
US9978668B1 (en) | 2017-01-17 | 2018-05-22 | Fairchild Semiconductor Corporation | Packaged semiconductor devices with laser grooved wettable flank and methods of manufacture |
US10121742B2 (en) * | 2017-03-15 | 2018-11-06 | Amkor Technology, Inc. | Method of forming a packaged semiconductor device using ganged conductive connective assembly and structure |
EP3203229B1 (en) | 2017-04-06 | 2020-03-18 | Sensirion AG | Calibrating a gas sensor |
US11127660B2 (en) | 2018-12-31 | 2021-09-21 | Microchip Technology Incorporated | Surface-mount integrated circuit package with coated surfaces for improved solder connection |
KR20210137143A (ko) * | 2019-03-08 | 2021-11-17 | 실리코닉스 인코포레이티드 | 측벽 도금을 갖는 반도체 패키지 |
CN110349857A (zh) * | 2019-08-01 | 2019-10-18 | 合肥矽迈微电子科技有限公司 | 侧壁露铜封装结构及其制作工艺 |
CN112652583A (zh) * | 2019-10-10 | 2021-04-13 | 珠海格力电器股份有限公司 | 一种封装器件及其生产方法 |
CN113035722A (zh) | 2019-12-24 | 2021-06-25 | 维谢综合半导体有限责任公司 | 具有选择性模制的用于镀覆的封装工艺 |
CN113035721A (zh) * | 2019-12-24 | 2021-06-25 | 维谢综合半导体有限责任公司 | 用于侧壁镀覆导电膜的封装工艺 |
CN116682740A (zh) * | 2023-05-18 | 2023-09-01 | 苏州震坤科技有限公司 | 减少半导体封装结构发生连锡的方法 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000294719A (ja) | 1999-04-09 | 2000-10-20 | Hitachi Ltd | リードフレームおよびそれを用いた半導体装置ならびにその製造方法 |
US6333252B1 (en) | 2000-01-05 | 2001-12-25 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6342730B1 (en) | 2000-01-28 | 2002-01-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6261864B1 (en) | 2000-01-28 | 2001-07-17 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6306685B1 (en) | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
US6238952B1 (en) | 2000-02-29 | 2001-05-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
JP4034073B2 (ja) * | 2001-05-11 | 2008-01-16 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
US7423337B1 (en) | 2002-08-19 | 2008-09-09 | National Semiconductor Corporation | Integrated circuit device package having a support coating for improved reliability during temperature cycling |
US7105383B2 (en) | 2002-08-29 | 2006-09-12 | Freescale Semiconductor, Inc. | Packaged semiconductor with coated leads and method therefore |
JP3866178B2 (ja) | 2002-10-08 | 2007-01-10 | 株式会社ルネサステクノロジ | Icカード |
JP3736516B2 (ja) | 2002-11-01 | 2006-01-18 | 松下電器産業株式会社 | リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法 |
US6872599B1 (en) * | 2002-12-10 | 2005-03-29 | National Semiconductor Corporation | Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
JP4645071B2 (ja) | 2003-06-20 | 2011-03-09 | 日亜化学工業株式会社 | パッケージ成型体およびそれを用いた半導体装置 |
CN100490140C (zh) | 2003-07-15 | 2009-05-20 | 飞思卡尔半导体公司 | 双规引线框 |
TWI338358B (en) | 2003-11-19 | 2011-03-01 | Rohm Co Ltd | Method of fabricating lead frame and method of fabricating semiconductor device using the same, and lead frame and semiconductor device using the same |
JP2006179760A (ja) | 2004-12-24 | 2006-07-06 | Yamaha Corp | 半導体パッケージ、および、これに使用するリードフレーム |
JP4207004B2 (ja) | 2005-01-12 | 2009-01-14 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP4408082B2 (ja) | 2005-01-14 | 2010-02-03 | シャープ株式会社 | 集積回路パッケージの設計方法および製造方法 |
JP4207934B2 (ja) | 2005-08-09 | 2009-01-14 | 三菱電機株式会社 | 4方向リードフラットパッケージic実装プリント配線基板、4方向リードフラットパッケージicの半田付方法、空気調和機。 |
US7256481B2 (en) | 2005-11-30 | 2007-08-14 | Texas Instruments Incorporated | Leadframes for improved moisture reliability and enhanced solderability of semiconductor devices |
US7943431B2 (en) | 2005-12-02 | 2011-05-17 | Unisem (Mauritius) Holdings Limited | Leadless semiconductor package and method of manufacture |
JP2007214185A (ja) | 2006-02-07 | 2007-08-23 | Denso Corp | リードフレーム |
US7405106B2 (en) | 2006-05-23 | 2008-07-29 | International Business Machines Corporation | Quad flat no-lead chip carrier with stand-off |
US7402459B2 (en) | 2006-07-10 | 2008-07-22 | Shanghai Kaihong Technology Co., Ltd. | Quad flat no-lead (QFN) chip package assembly apparatus and method |
WO2009125250A1 (en) | 2008-04-11 | 2009-10-15 | Freescale Semiconductor, Inc. | Integrated circuit package, method of manufacturing an integrated circuit package and printed circuit board |
US8329509B2 (en) * | 2010-04-01 | 2012-12-11 | Freescale Semiconductor, Inc. | Packaging process to create wettable lead flank during board assembly |
US8642461B2 (en) | 2010-08-09 | 2014-02-04 | Maxim Integrated Products, Inc. | Side wettable plating for semiconductor chip package |
-
2011
- 2011-05-18 CN CN201110162405.1A patent/CN102789994B/zh active Active
-
2012
- 2012-05-03 US US13/462,827 patent/US8685795B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20120292755A1 (en) | 2012-11-22 |
CN102789994A (zh) | 2012-11-21 |
US8685795B2 (en) | 2014-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102789994B (zh) | 侧面可浸润半导体器件 | |
CN207781575U (zh) | 经封装的电子装置 | |
KR101254803B1 (ko) | 반도체 장치의 제조 방법 | |
TWI291756B (en) | Low cost lead-free preplated leadframe having improved adhesion and solderability | |
US8487424B2 (en) | Routable array metal integrated circuit package fabricated using partial etching process | |
CN104685615A (zh) | 半导体器件的制造方法及半导体器件 | |
CN101536183B (zh) | 引线框条带、半导体装置以及用于制造该引线框的方法 | |
US10727169B2 (en) | Semiconductor device having lead with back and end surfaces provided with plating layers | |
CN105720033A (zh) | 具有预先施加的填充材料的引线框封装体 | |
US20140151865A1 (en) | Semiconductor device packages providing enhanced exposed toe fillets | |
CN102859687A (zh) | 半导体器件及其制造方法 | |
US8076181B1 (en) | Lead plating technique for singulated IC packages | |
JP2014232811A (ja) | 半導体装置および半導体装置の製造方法 | |
US20210265214A1 (en) | Methods and apparatus for an improved integrated circuit package | |
US9099484B2 (en) | Method of manufacturing semiconductor device | |
JP2006165411A (ja) | 半導体装置およびその製造方法 | |
US9287238B2 (en) | Leadless semiconductor package with optical inspection feature | |
CN108074901A (zh) | 具有可湿拐角引线的半导体器件及半导体器件组装方法 | |
CN102339762B (zh) | 无载具的半导体封装件及其制造方法 | |
CN107919331A (zh) | 无引线框架的表面安装半导体器件 | |
TW201530723A (zh) | 用於處理導線框表面之方法及具有經處理之導線框表面之裝置 | |
EP4213197A1 (en) | A semiconductor package substrate made from non-metallic material and a method of manufacturing thereof | |
CN101494210A (zh) | 导线架以及封装结构 | |
JP2022039128A (ja) | 電子部品 | |
KR19990030504A (ko) | 집적 회로 패키지용 리드프레임 및 그의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: NXP America Co Ltd Address before: Texas in the United States Patentee before: Fisical Semiconductor Inc. |
|
CP01 | Change in the name or title of a patent holder |