CN105720033A - 具有预先施加的填充材料的引线框封装体 - Google Patents

具有预先施加的填充材料的引线框封装体 Download PDF

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Publication number
CN105720033A
CN105720033A CN201510591002.7A CN201510591002A CN105720033A CN 105720033 A CN105720033 A CN 105720033A CN 201510591002 A CN201510591002 A CN 201510591002A CN 105720033 A CN105720033 A CN 105720033A
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China
Prior art keywords
recessed
lead
wire
leads
package body
Prior art date
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Pending
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CN201510591002.7A
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English (en)
Inventor
J·塔利多
F·R·戈麦斯
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STMicroelectronics Inc Philippines
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STMicroelectronics Inc Philippines
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Publication of CN105720033A publication Critical patent/CN105720033A/zh
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Abstract

本申请涉及具有预先施加的填充材料的引线框封装体。本公开的实施例涉及一种在引线外表面中形成有凹进的引线框封装体。该凹进被填充以诸如焊料的填充材料。该凹进中的填充材料为诸如焊料的填充材料提供在将该封装体安装至诸如印刷电路板(PCB)的另一设备期间用以粘合的可润湿表面。这使得能够在该封装体的引线和PCB之间形成强的焊料接合。这还使得能够在该封装体已经被安装之后对该焊料接合进行有所改善的视觉检查。

Description

具有预先施加的填充材料的引线框封装体
技术领域
本公开的实施例涉及引线框条和无引线封装体，以及制造引线框条和组装无引线封装体的方法。
背景技术
无引线(或没有引线)的封装体经常在其中需要小尺寸封装体的应用中得以被采用。通常，扁平无引线封装提供包括平面引线框的以接近芯片规模进行密封的封装体。位于该封装体的底部表面上并且在许多情况下位于该封装体的侧表面上的连接盘(land)(也被称作引线)提供与诸如印刷电路板(PCB)的衬底的电连接。该封装体使用表面安装技术(SMT)被直接安装在PCB的表面上。
虽然SMT允许较小的封装体，但是其也带来了一些缺陷。特别地，封装体和PCB之间的焊料接合会由于PCB和封装体具有不同的热膨胀系数(CTE)而变弱。因此，在一些情况下，封装体的可靠性会取决于焊料接合的完整性。
随着封装体尺寸的减小，可用于焊料接合的空间进一步受到限制。因此，需要封装体的连接盘与板的焊盘之间有强的焊料键合。
发明内容
本公开的实施例针对一种具有形成于引线外表面中的凹进的引线框封装体。该凹进被填充以诸如焊料的填充材料。该凹进中的填充材料为诸如焊料的填充材料提供了在将该封装体安装至诸如印刷电路板(PCB)的另一设备期间用以粘合的可润湿表面。这使得能够在该封装体的引线和PCB之间形成强的焊料接合。这还使得能够在该封装体已经被安装之后对该焊料接合进行有所改善的视觉检查。
附图说明
图1A是依据一个实施例的半导体封装体的截面视图的示意性图示。
图1B是图1的封装体的侧视图。
图2A和图2B是图示依据一个实施例的将图1的封装体安装至衬底的阶段的截面视图。
图3A-3D是依据各个实施例的作为特写视图的半导体封装体的引线的截面视图。
图4A-4F是依据一个实施例的图示出在制造的各个阶段进行组装的图1的封装体的截面视图。
图5A-5E是依据一个实施例的图示出在制造的各个阶段进行组装的图1的封装体的截面视图。
具体实施方式
图1A示出了依据本公开的一个实施例进行制作的引线框封装体10的截面视图。封装体10示出了裸片焊盘12以及与裸片焊盘12分隔开来并且处于裸片焊盘12的相反两侧上的两条引线18。裸片焊盘12具有上表面14和下表面16，并且引线18具有上表面22和下表面24。引线18的下表面24也被称作封装体10的连接盘。裸片焊盘12和引线18由诸如铜或铜合金的导电材料制成。
图1B示出了封装体10的侧视图。如该侧视图所示出的，该封装体在一侧上包括四条引线18。然而，所要意识到的是，可以在该封装体中包括任意数量的引线，包括裸片焊盘12仅一侧上的一条引线。在一些实施例中，引线被提供在裸片焊盘的两个侧面或四个侧面上。
引线18的外表面17和下表面24具有形成于其中的相应凹进26。凹进26可以为任意形状。在所图示的实施例中，凹进26为矩形形状。如图1B中最佳示出的，凹进26跨相应引线18的整个宽度进行延伸。然而，在其它实施例中，该引线的一部分可以形成凹进周围的侧表面。也就是说，该凹进从该封装体的侧面看可以为U形。凹进26可以具有任意的横向或垂直深度。在所图示的实施例中，该凹进延伸大约一半或者仅通过引线18的厚度的一半进行延伸且小于横向方向的一半。
裸片焊盘12的下表面16、引线18的下表面以及凹进26可以具有处于其上的导电层30。该导电材料可以是促进诸如焊料之类的填充材料粘合到引线18的任意导电材料。导电层30可以是一种或多种导电材料的纳米层或微米层。例如，裸片焊盘12的上表面14和下表面16以及引线18的上表面22和下表面24可以被镀以一种或多种金属材料，诸如Au、Ag、Ni/Pd/Ag、Ni/Pd/Au-Ag合金或Ni/Pd/Au/Ag。
填充材料32位于引线18的凹进26中。填充材料32可以是具有等于或低于被接合材料的熔点的任意导电材料，诸如处于导电层30或引线18与印刷电路板46上的焊盘之间(图2)。在一些实施例中，填充材料32是焊料材料。例如，在一些实施例中，该焊料材料是Ag或Sn组合物，诸如Sn/Pb合金、Sn/Bi合金、Cu/Sn合金等。
在所图示的实施例中，填充材料32对凹进26进行填充。填充材料32具有基本上与引线18的外表面17齐平的侧表面以及基本上与裸片焊盘12的下表面16齐平的底部表面。
再次参考图1A，封装体10进一步包括半导体裸片33，其通过粘合材料34耦合至裸片焊盘12的上表面14。半导体裸片33是被配置为发送和/或接收电信号的任意半导体裸片。例如，半导体裸片可以是集成电路、微机电传感器(MEMS)以及任意其它电子芯片。粘合材料34可以是被配置为在组装过程期间将半导体裸片33固定在原位的任意材料。粘合材料34可以是双面胶带、环氧树脂、胶合物或者用于将裸片33粘合到裸片焊盘12的上表面14的任意适当材料。
半导体裸片33包括导电焊盘40，如本领域中所熟知的，导电焊盘40电连接至形成于半导体裸片33中的一个或多个电路。导电导线36将半导体裸片33电耦合至引线18。例如，导电导线36的第一端38耦合至裸片33的键合焊盘40并且导电导线36的第二端42耦合至第一引线18。
密封材料44位于裸片焊盘12和引线18上方，对裸片33和导电导线36进行封闭。密封材料44还位于引线18和裸片焊盘12之间并且在其间形成底部表面45。引线18的外表面17和填充材料32连同密封材料44一起形成封装体10的外表面。密封材料44可以是被配置为针对诸如腐蚀、物理损伤、潮湿损伤或者针对电子器件的其它损伤原因之类的环境损伤来源提供保护。密封材料44可以是包括聚合物、聚氨酯、丙烯酸、环氧树脂、硅树脂或任何其它合适材料中的一种或多种材料的模制化合物。
图2A和图2B示出了依据一个实施例的将图1的封装体10安装至诸如印刷电路板(PCB)46的板的过程。如图2A所示，使用标准组装处理技术将诸如焊料凸块之类的导电凸块48形成于PCB的焊盘上。
导电凸块48由其熔化温度低于PCB46的焊盘以及引线18的熔化温度的任意材料所形成。在一些实施例中，该导电凸块具有大约与引线18的凹进26中的填充材料32相同或者比其更低的熔化温度。导电凸块48可以为以上参考填充材料32所提到的任意一种材料，然而，导电凸块48可以与填充材料32相同或者为不同材料。
如图2B中所最佳示出的，封装体10通过导电凸块48而以电气和机械的方式耦合至诸如PCB46的衬底的焊盘。如本领域中所熟知的，PCB46由一层或多层绝缘材料和包括导电迹线、焊盘的导电材料所制成。所要意识到的是，在一些实施例中，导电凸块形成于封装体10的引线18上。
在所图示的实施例中，封装体10的引线18被置于PCB的焊盘上的导电凸块48上。该导电凸块48诸如在回焊(reflow)步骤中被熔化，这将封装体10附着至PCB46。在回焊期间，填充材料32也会熔化，由此改善封装体10和PCB46之间的电气和机械连接。
在将封装体10安装在板46上之前将填充材料32置于引线18的凹进26中提供了许多优势。例如，通过在安装工艺之前利用填充材料32对凹进26进行填充，填充材料32更可能轻易地填充凹进26，由此消除或者至少减少凹进26中的空隙。就此而言，与凹进在安装工艺期间进行填充的情形相比，可以使得封装体10和PCB46之间的接合更强。
凹进26中的填充材料32提供可润湿的表面，诸如侧表面51，其使得导电凸块48能够在安装工艺期间沿其流动。也就是说，导电凸块48沿着凹进26中的填充材料32的侧表面51向上移动。就此而言，导电凸块48对封装体10和PCB46之间的接合的视觉检查提供了便利。此外，与凹进在板附着期间进行填充时相比，填充材料32和导电凸块48共同具有被用来将封装体10键合至PCB46的更大表面积。
此外，通过在安装步骤之前施加填充材料32，引线18——至少是凹进26中的引线部分——可以被保护而免于氧化，由此改善了在封装体10的引线18和PCB46的焊盘之间的电耦合。
图3A以与导电层30对齐并且被填充以填充材料32的凹进26的特写视图示出了图1中的一条引线18。填充材料32的下表面47与引线18的下表面24共面。填充材料32的侧表面51与引线18的外表面17共面。
图3B图示了依据另一实施例的能够在图1的封装体10中使用的引线18a。引线18a在功能和结构上基本上与图3A的引线18相同，区别在于图3B的引线18a并不包括凹进26内的导电层30。在该实施例中，填充材料32是易于与用于引线框以便形成引线和裸片焊盘的标准材料键合的任意填充材料，诸如包括铜和铜合金的金属。例如，在一个实施例中，引线和裸片焊盘由铜制成，而填充材料32为Cu/Sn，后者容易地键合至凹进26中的引线18的表面。
图3C图示了依据另一实施例的能够在图1的封装体10中使用的引线18b。引线18b在功能和结构上基本上与图3B的引线18a相同，区别在于填充材料32并不完全填充凹进26。虽然填充材料32基本上填充凹进26，但是填充材料32的下表面47a保持处于凹进26之内。就此而言，导电凸块48在安装期间也将会被提供至凹进26之中以可能地加强封装体10和PCB46之间的键合。在一个实施例中，填充材料32的下表面47a是凹面形状的。
图3D图示了依据另一实施例的能够在图1的封装体10中使用的引线18c。引线18c在功能和结构上基本上与图3B的引线18a相同，区别在于与凹进26延伸到引线18a中相比，图3D的凹进26a延伸到引线18c中更远。也就是说，图3D的凹进26a比图3B的凹进26具有更大的垂直深度。填充材料32对凹进26进行填充并且因此具有比图3A-3C的实施例中更大的侧表面51。就此而言，更大的侧表面51为导电凸块48提供更大的表面积，而使得导电凸块48在安装工艺期间沿其流动。因此，更大的侧表面51可以对安装之后的封装体10和PCB46之间的接合提供有所改进的视觉检查。
虽然并未示出，但是所要意识到的是，引线18、18a、18b、18c的各种特征能够在其它实施例中进行组合。例如，图3B-3D的实施例可以包括凹进26中的导电层30。
图4A-4E图示了依据一个实施例的制造图1的封装体10的各个阶段。特别地，图4A-4C图示了制造引线框条50的各个阶段，而图4D-4E图示了制造具有引线框条50的封装体10的各个阶段。
如图4A所示，其示出了引线框条50的一部分。引线框条50为诸如金属的导电材料，并且在一些实施例中由铜或铜合金制成。如本领域中已知的，引线框条50被形成为具有多个裸片焊盘12、引线18、将相邻引线18耦合在一起的连接栏(connectingbar)52、以及将裸片焊盘12耦合至引线18的结合栏(tiebar)(未示出)。
凹进26形成于引线18的下表面24中并且使用标准半导体处理技术所形成，包括利用光敏材料和蚀刻技术形成图案。如以上所提到的，凹进26可以被形成为延伸通过引线18的厚度的大约一半或更多。如图4A中所最佳示出的，凹进26形成相邻引线18之间的连接栏52。
如图4B所示，如果被使用，则导电材料30诸如通过电镀技术而沉积在引线框条50的下表面上。导电材料30可以如所图示实施例中所示的那样被沉积在凹进26中的表面上。然而，针对图3B-3D的实施例而言，导电材料将不会沉积在凹进之中。虽然并未示出，但是在一些实施例中，导电材料也可以被沉积在引线框条的上表面上。
如图4C所示，填充材料32被沉积在凹进26中。填充材料32可以通过任意技术进行沉积。在一些实施例中，引线框条50的一些或全部下表面可以在将填充材料32沉积在凹进26中之后被进行表面处理。例如，该表面处理可以包括研磨、化学-机械抛光、蚀刻或者填充材料32的任意其它表面处理方法，并且在一些实施例中可以包括对引线框条50的下表面进行处理。在一些实施例中，执行填充材料32的沉积或填充材料32的表面处理，使得该填充材料与引线18的下表面24共面，或者使得填充材料在引线18的下表面24之下凹进。就此而言，在一些实施例中，填充材料32被沉积而使得其并未填充凹进26。
如图4D所示，在一些实施例中，引线框条50可以被固定至诸如胶带的衬底材料54，以在后续处理期间为引线框条50提供支撑。所要意识到的是，衬底材料也可以提供在引线框条的上表面上以在图4A-4C中所示的任意步骤期间提供支撑。
如图4E所示，半导体裸片33使用已知的封装体组装技术而通过粘合材料34被附着至裸片焊盘12的上表面14。导电导线36耦合在半导体裸片33的焊盘40和相邻引线18之间。也就是说，导电导线36的第一端38耦合至裸片33的焊盘40，而导电导线36的第二端42耦合至引线18。
密封材料44形成在引线框条50的上表面上方，使得密封材料44包围裸片33、导电导线36以及引线框条50的上表面。密封材料44还形成于连接栏52、引线18和裸片焊盘12上方。密封材料44可以通过常规技术——例如通过模制工艺——而被形成于引线框条50上，并且在一些实施例中在固化步骤期间被硬化。
该制造工艺进一步包括将每个封装体分割为如图4F所示的个体封装体10。特别地，封装体10通过经连接栏52、凹进26中的填充材料32以及位于连接栏52上方的密封材料44进行切割而被分割。封装体10可以通过各种切割方法进行分割，包括锯和激光。用于分割封装体10的锯片或激光具有小于连接栏52的宽度的切割宽度，而使得每条引线18包括利用随每个封装体10一起提供的填充材料进行填充的凹进26。虽然并未示出，但是如本领域所熟知的，引线框条50可以在该切割步骤期间被固定至诸如胶带的支撑结构。
图5A-5E图示了依据另一实施例的制造图1的封装体10的各个阶段。该制造步骤基本上与图4A-4E的制造步骤相同，然而一些步骤是以不同的顺序来执行。引线框条50包括利用连接栏52而被耦合在一起的相邻引线18，该引线18具有凹进26。引线框条50可以被提供在衬底材料54上。如图5B中所示，半导体裸片33被固定至裸片焊盘12，导电导线36耦合在裸片33的焊盘40和引线18之间，并且密封材料在对引线框条50的凹进26进行填充之前被形成。
如图5C所示，如果被使用，则衬底材料54被去除而暴露出凹进26。如图5D所示，凹进26利用填充材料32进行填充。如以上所讨论的，填充材料32或者引线框条50的下表面可以是经表面处理的。如图5D所示，执行切割步骤以将每个封装体分割为个体封装体10。
以上所描述的各个实施例能够进行组合以提供另外的实施例。本申请中所引用和/或在申请数据页中所列出的所有美国专利、美国专利申请公开、美国专利申请、外国专利、外国专利申请和非专利公开都通过引用全文结合于此。实施例的多个方面可以在有必要采用各个专利、申请和公开的概念以提供另外的实施例的情况下进行修改。
能够借鉴以上的详细描述对实施例进行这些和其它改变。通常，在以下权利要求中，所使用的术语并不应当被理解为将权利要求限制为说明书和权利要求中所公开的具体实施例，而是应当被理解为包括所有可能的实施例以及这样的实施例所要求保护的等同形式的完整范围。因此，权利要求并不被本公开所限制。

Claims (20)

1.一种电子器件，包括：
半导体封装体，包括：
具有第一表面和第二表面的裸片焊盘；
耦合至所述裸片焊盘的第一表面的半导体裸片；
位于所述裸片焊盘附近并且与所述裸片焊盘分开的多条引线，所述多条引线中的每一条引线的外表面包括凹进；和
位于所述多个凹进中的导电填充材料；
衬底，具有多个导电焊盘；以及
导电凸块，将所述半导体封装体的引线耦合至所述衬底的焊盘，所述导电凸块被耦合至所述导电填充材料。
2.根据权利要求1所述的电子器件，进一步包括位于所述半导体裸片和所述多条引线的一部分上方的密封材料。
3.根据权利要求1所述的电子器件，其中焊料为第一焊料，其中所述填充材料为第二焊料。
4.根据权利要求2所述的电子器件，其中所述第一焊料为Sn/Pb、Ag、Sn/Bi或Cu/Sn。
5.根据权利要求1所述的电子器件，其中所述衬底是印刷电路板。
6.一种半导体封装体，包括：
具有第一表面和第二表面的裸片焊盘；
耦合至所述裸片焊盘的第一表面的半导体裸片；
位于所述裸片焊盘的至少一个侧面附近并且与所述侧面分开的多条引线，所述多条引线的外表面形成所述半导体封装体的外表面的一部分；所述多条引线分别具有凹进；
位于所述多条引线的凹进中的导电填充材料，所述导电填充材料与所述封装体外部的其它电气组件电绝缘；以及
位于所述半导体裸片和所述多条引线的一部分上方的密封材料。
7.根据权利要求6所述的半导体封装体，其中所述凹进跨所述引线的整个宽度进行延伸。
8.根据权利要求6所述的半导体封装体，其中所述填充材料是焊料材料。
9.根据权利要求8所述的半导体封装体，其中所述焊料材料是Cu/Sn、Sn/Pb、Ag和Sn/Bi之一。
10.根据权利要求6所述的半导体封装体，其中所述填充材料具有第一表面并且所述密封材料具有第三表面，所述第三表面基本上与所述第一表面共面。
11.根据权利要求6所述的半导体封装体，其中所述填充材料具有至少一个为凹面形状并且低于所述裸片焊盘的第二表面而凹进的表面。
12.根据权利要求6所述的半导体封装体，其中所述凹进延伸通过所述多条引线的超过一半。
13.根据权利要求6所述的半导体封装体，进一步包括将所述半导体裸片的键合焊盘电耦合至所述多条引线之一的导线键合。
14.根据权利要求6所述的半导体封装体，其中所述多条引线包括所述凹进中的导电层，所述导电层包括Au、Ag、Ni/Pd/Ag、Ni/Pd/Au-Ag合金和Ni/Pd/Au/Ag中的一种，并且所述填充材料位于所述导电层上。
15.一种形成多个半导体封装体的方法，所述方法包括：
利用导电填充材料对通过连接栏接合在一起的多条引线中的多个凹进进行基本上填充；
将多个半导体裸片附着至裸片焊盘的表面；
将所述多个半导体裸片电耦合至所述多条引线；
密封所述多个半导体裸片；以及
切割穿过所述密封材料、所述连接栏和所述导电填充材料，以形成所述多个半导体封装体，其中切割穿过所述连接栏包括将接合的所述引线进行分割。
16.根据权利要求15所述的方法，进一步包括对所述导电填充材料进行表面处理，使得所述导电填充材料的表面基本上与相应引线的表面共面。
17.根据权利要求15所述的方法，其中基本上填充包括对所述多个凹进进行填充使得所述导电填充材料在所述引线的表面之下而凹进。
18.根据权利要求15所述的方法，其中在将所述多个半导体裸片附着至裸片焊盘的表面之前对所述多个凹进进行基本上填充。
19.根据权利要求15所述的方法，其中在密封所述半导体裸片之后对所述多个凹进进行基本上填充。
20.根据权利要求15所述的方法，其中所述导电填充材料为焊料。
CN201510591002.7A 2014-12-22 2015-09-16 具有预先施加的填充材料的引线框封装体 Pending CN105720033A (zh)

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