JP6253531B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6253531B2 JP6253531B2 JP2014133849A JP2014133849A JP6253531B2 JP 6253531 B2 JP6253531 B2 JP 6253531B2 JP 2014133849 A JP2014133849 A JP 2014133849A JP 2014133849 A JP2014133849 A JP 2014133849A JP 6253531 B2 JP6253531 B2 JP 6253531B2
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- lead
- groove
- sealing body
- semiconductor device
- wire
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
<関連技術の説明>
まず、本発明者が検討した関連技術について、図面を参照しながら説明する。図9は、本実施の形態の関連技術の半導体装置の構成を示す要部断面図である。
まず、本実施の形態の半導体装置SDの構成について、図1および図2を用いて説明する。本実施の形態の半導体装置SDは、ダイパッド(チップ搭載部、タブ)DPと、ダイパッドDP上にダイボンド材(接着材)AD(図2参照)を介して搭載された半導体チップCHと、を備えている。また、半導体装置SDは、半導体チップCH(ダイパッドDP)の隣(周囲)に配置された複数のリード(端子、外部端子)と、半導体チップCHの複数のパッド(電極、ボンディングパッド)と複数のリードとをそれぞれ電気的に接続する複数のワイヤ(ボンディングワイヤ、導電性部材)BWと、を有している。
次に、図1から図6を用いて、本実施の形態の半導体装置SDの製造方法について説明する。図4は、本実施の形態の半導体装置SDの製造工程を示すプロセスフローである。
図7は、本実施の形態の信号リードSLの変形例を示す拡大平面図および拡大断面図である。つまり、図7は、図6の変形例に相当する。
図8は、本実施の形態の信号リードSLの変形例を示す拡大平面図および拡大断面図である。つまり、図7は、図6の変形例に相当する。
BD 封止体
BW ワイヤ
CH 半導体チップ
SD 半導体装置
SL 信号リード
GV1 内溝
Claims (16)
- 半導体チップと、
前記半導体チップの周囲に配置され、主面と前記主面に対向する裏面とを有するリードと、
前記リードの前記主面に接続され、前記半導体チップと前記リードとを電気的に接続するワイヤと、
前記半導体チップ、前記リードおよび前記ワイヤを封止樹脂で被覆した封止体と、
を有し、
前記リードは、前記リードの延在方向である第1方向において、前記封止体の内部に位置する一端と、前記封止体の外部に位置する他端と、前記ワイヤが接続されたワイヤ接続部と、を有し、
前記リードは、前記主面上において、前記一端と前記ワイヤ接続部との間であって、前記封止体の内部に第1溝を有し、
前記第1溝は、前記第1方向に対して直交する第2方向に沿って延在しており、
前記第2方向において、第1溝の長さは、平面視において前記リードの前記一端の長さよりも小であり、
前記リードは、前記主面上において、前記ワイヤ接続部と前記他端の間であって、前記封止体の内部に第2溝を有し、
前記第1溝の深さは、前記リードの膜厚方向において前記第2溝の深さよりも大である、半導体装置。 - 請求項1において、
前記リードの線膨張係数は、前記封止樹脂の線膨張係数よりも大である、半導体装置。 - 請求項2において、
前記リードは銅からなり、前記封止樹脂はシリカからなるフィラーを含むエポキシ樹脂からなる、半導体装置。 - 請求項1において、
前記第2方向において、前記第1溝の長さは、前記第2溝の長さよりも大きい、半導体装置。 - 請求項1において、
前記リードは、前記封止体の内部のインナー部と前記封止体の外部のアウター部とを有し、前記第2方向における前記アウター部の幅は、前記第2方向における前記第1溝の長さよりも小である、半導体装置。 - 請求項5において、
前記第2方向において、前記インナー部の幅は、前記アウター部の幅よりも大である、半導体装置。 - 請求項1において、
前記第1溝の断面形状はV字形状である、半導体装置。 - 請求項1において、
前記第2溝の断面形状はV字形状である、半導体装置。 - 対向する第1辺と第2辺とを有する四角形の第1面を有し、前記第1面上に第1パッドと複数の第2パッドとを有する半導体チップと、
前記半導体チップの前記第1辺および前記第2辺に直交する第1方向に延在し、主面と前記主面に対向する裏面とを有する第1リードおよび第2リードと、
前記第1リードの主面に接続され、前記半導体チップの前記第1パッドと前記第1リードとを電気的に接続する第1ワイヤと、
前記第2リードの主面に接続され、前記半導体チップの前記複数の第2パッドと前記第2リードとを電気的に接続する複数の第2ワイヤと、
前記半導体チップ、前記第1リード、前記第2リード、前記第1ワイヤおよび前記複数の第2ワイヤを封止樹脂で被覆した封止体と、
を有し、
前記第1リードは、前記半導体チップの前記第1辺側に配置され、前記第2リードは、前記半導体チップの前記第2辺側に配置されており、
前記第1リードは、前記第1方向において、前記封止体の内部に位置する第1端部と、前記封止体の外部に位置する第2端部と、前記封止体の内部に位置し、前記第1ワイヤが接続された第1ワイヤ接続部とを有し、
前記第2リードは、前記第1方向において、前記封止体の内部に位置する第3端部と、前記封止体の外部に位置する第4端部と、前記封止体の内部に位置し、前記複数の第2ワイヤが接続された第2ワイヤ接続部とを有し、
前記第1リードは、前記第1リードの主面上において、前記第1端部と前記第1ワイヤ接続部との間であって、前記封止体の内部に第1溝を有し、
前記第2リードは、前記第2リードの主面上において、前記第2ワイヤ接続部から前記第3端部までは溝が配置されていない連続する平坦面を有し、
前記第1溝は、前記第1方向に対して直交する第2方向に沿って延在しており、
前記第2方向において、前記第1溝の長さは、平面視において前記第1リードの前記第1端部の長さよりも小であり、
前記第1リードは、前記第1リードの主面上において、前記第1ワイヤ接続部と前記第2端部の間であって、前記封止体の内部に第2溝を有し、
前記第1溝の深さは、前記第1リードの膜厚方向において前記第2溝の深さよりも大である、
半導体装置。 - 請求項9において、
前記第2ワイヤ接続部の面積は、前記第1ワイヤ接続部の面積よりも大きい、半導体装置。 - 請求項9において、さらに、
前記封止体内の前記第2リードの主面において、前記第2ワイヤ接続部と前記第4端部との間に第3溝を有する、半導体装置。 - 請求項9において、
前記第2方向において、前記第1リードの前記第1溝の長さは、前記第2溝の長さよりも大きい、半導体装置。 - 請求項9において、
平面視において、前記第2リードは、前記第2方向に延在する第1部分と、前記第1部分から前記第1方向に沿って延在する複数の第2部分と、を有し、
前記第2リードの前記複数の第2部分のそれぞれの一部および前記第1部分は、前記封止体の内部に位置し、
平面視において、前記第2リードの前記第1部分と前記第2リードの前記複数の第2部分とで囲まれた領域には、前記封止体の前記封止樹脂が介在する、半導体装置。 - 請求項9において、
前記第1溝の断面形状はV字形状であり、
前記第2溝の断面形状はV字形状である、半導体装置。 - 請求項11において、
前記第3溝の断面形状はV字形状である、半導体装置。 - 請求項11において、
前記第2方向において、前記第1溝の長さは、前記第3溝の長さよりも大きい、半導体装置。
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CN201510289444.6A CN105304600B (zh) | 2014-06-30 | 2015-05-29 | 半导体装置以及半导体装置的制造方法 |
US14/752,884 US10553525B2 (en) | 2014-06-30 | 2015-06-27 | Semiconductor device and manufacturing method of semiconductor device |
HK16104291.0A HK1216358A1 (zh) | 2014-06-30 | 2016-04-14 | 半導體裝置以及半導體裝置的製造方法 |
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EP4401128A2 (en) | 2017-03-23 | 2024-07-17 | Kabushiki Kaisha Toshiba | Ceramic metal circuit board and semiconductor device using same |
CN108039342A (zh) * | 2017-12-01 | 2018-05-15 | 泰州友润电子科技股份有限公司 | 一种改进的to-220d7l引线框架 |
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CN108520872A (zh) * | 2018-05-02 | 2018-09-11 | 泰州友润电子科技股份有限公司 | 一种具有绝缘保护性能的多装载型引线框架 |
JP7304145B2 (ja) * | 2018-11-07 | 2023-07-06 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
US11502045B2 (en) * | 2019-01-23 | 2022-11-15 | Texas Instruments Incorporated | Electronic device with step cut lead |
JP7381168B2 (ja) * | 2019-12-09 | 2023-11-15 | 日清紡マイクロデバイス株式会社 | 半導体装置の設計方法 |
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US11715678B2 (en) * | 2020-12-31 | 2023-08-01 | Texas Instruments Incorporated | Roughened conductive components |
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JPS6142856U (ja) * | 1984-08-23 | 1986-03-19 | 日本電気株式会社 | 半導体装置 |
JPH05315512A (ja) * | 1992-05-07 | 1993-11-26 | Nec Corp | 半導体装置用リードフレーム |
JPH06140563A (ja) | 1992-10-23 | 1994-05-20 | Rohm Co Ltd | 半導体装置 |
JPH08107172A (ja) | 1994-10-04 | 1996-04-23 | Hitachi Cable Ltd | リードフレームの製造方法 |
JPH104170A (ja) | 1996-06-14 | 1998-01-06 | Nec Corp | リードフレーム |
JPH10303352A (ja) * | 1997-04-22 | 1998-11-13 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP2915892B2 (ja) * | 1997-06-27 | 1999-07-05 | 松下電子工業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
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JP2003318348A (ja) * | 2002-04-19 | 2003-11-07 | Denso Corp | 樹脂封止型電子装置 |
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JP2006108306A (ja) | 2004-10-04 | 2006-04-20 | Yamaha Corp | リードフレームおよびそれを用いた半導体パッケージ |
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JP2010283252A (ja) * | 2009-06-08 | 2010-12-16 | Denso Corp | 半導体装置およびその製造方法 |
JP2013062338A (ja) * | 2011-09-13 | 2013-04-04 | Toshiba Corp | 発光装置 |
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JP2015153987A (ja) * | 2014-02-18 | 2015-08-24 | 株式会社デンソー | モールドパッケージ |
CN203910779U (zh) * | 2014-06-26 | 2014-10-29 | 三垦电气株式会社 | 半导体装置 |
JP6253531B2 (ja) * | 2014-06-30 | 2017-12-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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CN105304600B (zh) | 2020-06-26 |
CN205016506U (zh) | 2016-02-03 |
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US10553525B2 (en) | 2020-02-04 |
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