CN108074901A - 具有可湿拐角引线的半导体器件及半导体器件组装方法 - Google Patents
具有可湿拐角引线的半导体器件及半导体器件组装方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000000465 moulding Methods 0.000 claims abstract description 15
- 239000002131 composite material Substances 0.000 claims abstract description 11
- 238000005520 cutting process Methods 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 9
- 238000004070 electrodeposition Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910001092 metal group alloy Inorganic materials 0.000 claims 3
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 12
- 238000007689 inspection Methods 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000002390 adhesive tape Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H—ELECTRICITY
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- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
本发明涉及具有可湿拐角引线的半导体器件及半导体器件组装方法。所述半导体器件具有可湿拐角引线。半导体裸片被安装在引线框架上。裸片接合焊盘与所述引线框架的引线电连接。利用模塑复合物封装所述裸片和电连接部。所述引线暴露并与所述器件的所述拐角齐平。所述引线包括使其可湿的凹坑,其有助于在将所述器件安装在电路板或基板上时的检查。
Description
技术领域
本发明涉及半导体封装,更具体来说涉及一种半导体器件,所述半导体器件具有焊料可湿的拐角引线或“侧面(flank)”,以在利用表面贴装技术(SMT)工艺将所述半导体器件安装在基板或电路板上时便于检查焊点。
背景技术
典型的半导体器件包括附接至引线框架标记的半导体裸片(die)。裸片上的接合焊盘通过接合导线与引线框架的引线电连接。该组装件由模塑复合物封装,该模塑复合物保护裸片和导线接合免受环境损坏和物理损坏。在一些封装件中,引线从封装件的侧面向外延伸,而在诸如方形扁平无引线(QFN)封装件或双侧扁平无引线(DFN)封装件的另一些封装件中,引线与封装件主体的侧面齐平。例如,在组装期间,同时组装一批封装件。在模塑或封装的步骤后,通过切割分离步骤形成各个单独的器件,其中使用切割刀分离相邻的器件。由于暴露且与器件侧壁齐平的未经处理的铜表面,使得这些器件在其侧面是不可湿的。也就是说,由于利用切割刀分离半导体封装件的方式,暴露的引线或侧面的表面与器件的模塑复合物齐平,使得焊料不容易爬上或“依靠毛细作用传送到(wick)”封装件的侧面,这意味着QFN封装件是侧面不可湿的。这使得在封装件已附接至基板或电路板后难以检查焊点。
为了克服这个缺点,当前的具有侧面可焊端子的无引线塑料封装件在封装件侧壁上具有可焊侧面。然而,该设计不能应用于具有多个I/O端子和大I/O间距(≥0.4mm)的超小型封装件(≤1mm×1mm),因为这种封装件不够大,无法容纳侧壁上的多个端子。
因此,期望拥有具有可湿侧面的超小型无引线封装件,以在将封装件诸如使用SMT工艺安装到印刷电路板(PCB)时便于检查焊点。
发明内容
在一个实施例中,本发明提供一种组装侧面可湿的半导体器件的方法。该方法包括提供矩形引线框架的阵列,其中各个单独的引线框架被切割道(saw streets)隔开,且每个引线框架具有延伸到该引线框架的拐角的引线,使得每个引线具有与两个相邻且垂直的切割道邻接的端部。沿切割道蚀刻引线框架,以使得在每个引线的端部形成凹坑。各半导体裸片被安装并附接至相应的引线框架。然后,裸片上的接合焊盘与其上安装有裸片的引线框架的相应引线电连接。用模塑复合物将裸片和电连接部封装,然后沿切割道切割引线框架阵列,以将各个器件与相邻的器件分开。每个器件具有与模塑复合物齐平的拐角接合焊盘,且每个引线的凹坑在切割之后暴露。
在另一个实施例中,本发明提供一种侧面可湿的半导体器件。该器件包括包含多个引线的引线框架以及安装在该引线框架上的半导体裸片。裸片上的接合焊盘电连接至相应的引线。用模塑复合物封装裸片、引线和电连接部。引线的端部在器件的拐角侧壁处暴露。每个引线的暴露部分与器件的两个相邻侧面齐平,并且在所述暴露部分中包括凹坑,以使得引线是可湿的。
附图说明
当结合附图阅读时,将更好地理解本发明的优选实施例的以下详细说明。本发明以示例的方式示出,并不受附图的限制,附图中相同的附图标记表示相似的元件。应当理解,为了易于理解本发明,附图不是按比例绘制的,并且已经进行简化。
图1A和图1B是根据本发明的实施例的半导体器件的透视的正视等角投影(isometric)图和仰视等角投影图;
图2是用于组装图1A和图1B的器件的引线框架阵列的俯视图;
图3A、图3B和图3C是示出图1A至图1B的器件附接到基板的主视图、俯视图和侧视图;
图4是根据本发明的另一个实施例的半导体器件的侧视图;
图5是示出根据本发明的实施例的引线框架的制造方法的流程图;以及
图6是示出根据本发明的实施例的组装半导体器件的方法的流程图。
具体实施方式
现在参照图1A和图1B,示出了根据本发明的优选实施例的半导体器件10。图1A是透视的正视等角投影图,图1B是半导体器件10的仰视等角投影图。器件10通常为矩形且通常非常小。例如,在一个实施例中,器件10为0.6mm×0.6mm(L×W)的量级。
器件10具有由模塑复合物形成的主体12和四个引线14。在本实施例中,主体12通常为正方形,引线14在器件10的底表面和侧表面的四个拐角处暴露。引线14还与器件10的底表面和侧表面齐平,并且包括位于拐角处的凹坑,其在将器件10附接至基板或电路板(未示出)时促进焊料的依靠毛细作用的传送。在一个实施例中,引线14彼此间隔约0.4mm。
从图1A可以看出,器件10还包括安装并附接至引线14的半导体裸片16。在本实施例中,裸片16的接合焊盘电连接至具有接合导线18的引线14。在其他实施例中,裸片16可包括倒装芯片裸片,该倒装芯片裸片具有在其接合焊盘上的凸块,以使得裸片可通过将裸片接合焊盘与引线14接触而电连接至引线14。裸片16、接合导线18和引线14的部分被模塑复合物12封装。
图2示出了用于组装器件10的引线框架阵列20的一部分,其中示出了四个单独的引线框架22。引线框架22通过沿X方向延伸的切割道24和沿Y方向延伸的切割道26彼此分隔开。每个引线框架22包括四个引线14,引线14从引线框架的拐角向引线框架的中心延伸。在切割道24、26处,各个引线14延伸到框架的拐角处,使得每个引线14邻接两个相邻且垂直的切割道。引线框架阵列20可由诸如铜的导电金属的片材形成,并且可预镀(PPF),或在PPF或铜表面上用锡进行后镀。此外,在引线14的外部拐角处蚀刻引线框架阵列20,以在引线14中形成凹坑28。在标准引线框架半蚀刻工艺之后,凹坑深度通常为引线框架厚度的一半。引线14和引线框架22的尺寸和形状适合于容纳裸片16。在所示的实施例中,裸片16安装并附接至引线14。在其他实施例中,引线框架22可包括用于接收和支撑裸片16的裸片标记。由铜片形成的引线框架阵列、对引线框架阵列蚀刻、以及对引线框架阵列镀层在本领域中是已知的,因此进一步的描述对于完全理解本发明不是必要的。
现在参照图3A,示出了器件10安装在基板30上的侧视图。如本领域所知,基板30可包括印刷电路板(PCB),该PCB具有用于将安装在其上的器件彼此连接的内部金属线路。基板30包括焊盘32,器件10的引线14将电连接至焊盘32。图3B是安装在基板30上的器件10的等角投影图,其中引线14通过焊料34电连接至基板的焊盘32。焊料34接触引线14并填充凹坑28。图3C是附接至基板30的器件10的俯视图。可以看到,目视检查将器件10耦接至基板30的焊点相对容易。
图4是根据本发明的另一实施例的经封装的半导体器件40的侧视图。器件40与器件10相似,并且包括由用于封装半导体裸片(未示出)的模塑复合物形成的主体42。器件40具有拐角引线44,拐角引线44与主体42的侧表面齐平且在器件40的两个相邻侧表面和底表面处暴露。器件40还具有仅在器件40的一个侧表面和底表面上暴露的侧引线46。拐角引线44和侧引线46都包括凹坑48,凹坑48在器件40附接至基板或电路板时用于容纳焊料。
图5是示出制造引线框架或引线框架阵列的方法50的流程图,所述引线框架阵列类似于图2中示出的引线框架阵列20。
在步骤52,提供诸如铜的导电金属的片材。在步骤54,将抗蚀剂施加到金属片上,然后在步骤56,半蚀刻金属片以形成一个或多个引线框架(例如,引线框架阵列)。根据本发明,引线框架包括拐角引线,如同图2中示出的引线框架22。引线框架由在X轴方向和Y轴方向两者上延伸的切割道分隔开。在步骤56,在引线中形成凹坑,如图2和图4所示的凹坑28和48。在半蚀刻引线框架后,可执行镀层步骤58来为引线镀上诸如钯或者银以防止腐蚀。根据需要,镀层步骤58可镀整个引线框架或仅镀引线框架的选定部分。镀层步骤58优选使用电镀或电沉积工艺进行,在电镀或电沉积工艺期间包括引线44a、44b的端部或边缘的引线框架涂覆有诸如镍/钯/金的可焊层。在镀层处理中,引线可连接至电势源,使得引线在电镀或电沉积工艺中形成阴极。电镀或电沉积工艺导致导电可湿的金属层沉积在引线框架的暴露表面上。镀层在诸如SMT(表面贴装技术)的焊接工艺中赋予可焊性或焊料可湿性,并保护引线框架的暴露表面免受腐蚀。应当注意,引线框架可包括裸铜,或者引线框架可在接合表面(例如用银)预镀(背面通常保持为裸铜),并且在将引线框架切割成单独的半导体器件之前或之后,可将锡涂层或锡合金涂层施加至暴露的引线端部。在步骤59,用胶带粘贴引线框架或引线框架阵列,也就是说,在引线框架背面涂布一层胶带。该胶带防止引线框架在使用前变形。方法50通常由引线框架供应商执行。但是,方法50也可以在测试和组装设施处执行。
图6是示出组装诸如半导体器件10和40的半导体器件的方法60的流程图。
所述方法从提供有引线框架(例如图2所示的被预镀的引线框架阵列)的步骤62开始。所提供的引线框架包括位于在组装后将外露的引线部分中的凹坑。在步骤64,将裸片安装并附接至引线框架(例如根据方法50制造的引线框架)的引线。在目前的优选实施例中,裸片的非有效侧(non-active side)的拐角位于并附接至引线的内侧部分。可使用裸片附接剂或双面胶带将裸片附接至引线。
步骤64之后是导线接合步骤66,在步骤66中利用接合导线将裸片的接合焊盘与相应的引线电连接。在替代实施例中,裸片可以是倒装芯片裸片,并在裸片接合焊盘上具有焊料凸块;然后将裸片安装在引线框架上,其中裸片的有效侧(active side)面向引线框架,使得裸片的接合焊盘与引线直接接触。
导线接合步骤66之后是封装或模塑步骤68,在封装或模塑步骤68中,如本领域已知的,引线框架、裸片和接合导线被模塑复合物覆盖。模塑步骤68优选地包括同时对引线框架阵列上形成的多个组装件全部进行模塑的模塑阵列工艺(MAP)。在塑封步骤68之后,执行激光打标,如果在引线框架阵列的底表面上存在胶带,则在除带步骤中去除该胶带。然后在分离步骤69中将各组装件彼此分隔开,其中切割刀沿切割道行进,从而切割同时组装的器件并使其彼此分离。然后可以检查分离好的QFN(方形扁平无引线)器件并将其打包以进行装运。
从前面的讨论可以看出,本发明提供了生产侧面可湿的半导体器件的方法。虽然已经说明和描述了本发明的优选实施例,但是应当清楚本发明不仅限于这些实施例。在不脱离权利要求所限定的本发明的精神和范围的情况下,许多修改、变化、变型、替换和等同物对于本领域技术人员将是显而易见的。
Claims (14)
1.一种组装侧面可湿的半导体器件的方法,包括步骤:
提供矩形引线框架的阵列,其中各个单独的引线框架被切割道隔开,并且每个引线框架具有延伸到该引线框架的拐角的引线,以使得每个拐角引线具有邻接两个相邻且垂直的切割道的端部,并且其中每个拐角引线具有形成在其外表面处的凹坑;
将半导体裸片安装并附接至各个引线框架中的相应引线框架;
将所述半导体裸片上的接合焊盘与其上安装有所述半导体裸片的引线框架的引线中的相应引线电连接;
利用模塑复合物将所述半导体裸片和所述电气连接部封装;
沿所述切割道切割所述引线框架以将各个单独的半导体器件与相邻的半导体器件分离,使得每个半导体器件具有与该半导体器件的模塑复合物齐平的拐角接合焊盘,并且其中每个拐角引线的所述凹坑在切割步骤之后暴露。
2.根据权利要求1所述的方法,还包括:在将所述引线框架切割成各个单独的半导体器件之前,将涂层金属或涂层金属合金施加至暴露的引线端部。
3.根据权利要求2所述的方法,其中通过电镀或电沉积施加所述涂层金属或涂层金属合金。
4.根据权利要求3所述的方法,其中所述涂层金属或涂层金属合金包括锡或锡合金。
5.根据权利要求1所述的方法,其中电连接步骤包括将接合导线附接至裸片接合焊盘和所述引线中的相应引线。
6.根据权利要求1所述的方法,其中将所述半导体裸片的非有效侧附接至相应引线框架中的每一个的引线。
7.根据权利要求1所述的方法,其中每个单独的引线框架具有四个拐角引线,所述四个拐角引线中的每一个延伸至该引线框架的单独的拐角处。
8.根据权利要求7所述的方法,其中每个单独的引线框架包括一个或多个附加引线,其设置在所述半导体器件的一侧并位于所述一侧上的拐角引线之间。
9.一种通过根据权利要求1所述的方法组装的半导体器件。
10.一种侧面可湿的半导体器件,包括:
包括多个引线的引线框架;
安装在所述引线框架上的半导体裸片,其中所述半导体裸片上的接合焊盘与所述引线中的相应引线电连接;
封装所述半导体裸片、所述引线和电连接部的模塑复合物,其中所述引线的端部在所述半导体器件的拐角侧壁处暴露,并且
其中所述引线中的每一个的暴露部分与所述半导体器件的两个相邻侧面齐平,并在所述暴露部分中包括凹坑以使得所述引线可湿。
11.根据权利要求10所述的半导体器件,还包括在所述引线的暴露部分上的保护性金属或保护性金属合金的涂层。
12.根据权利要求11所述的半导体器件,其中所述涂层包括锡或锡合金。
13.根据权利要求10所述的半导体器件,其中在组装过程中在将所述半导体器件与相邻的半导体器件分离前,通过电镀或电沉积将所述涂层施加至所述引线的暴露部分。
14.根据权利要求10所述的半导体器件,还包括将裸片接合焊盘与所述引线电连接的多个接合导线。
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