CN102742009A - 裸片附着垫接地接合增强 - Google Patents
裸片附着垫接地接合增强 Download PDFInfo
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- CN102742009A CN102742009A CN2010800427420A CN201080042742A CN102742009A CN 102742009 A CN102742009 A CN 102742009A CN 2010800427420 A CN2010800427420 A CN 2010800427420A CN 201080042742 A CN201080042742 A CN 201080042742A CN 102742009 A CN102742009 A CN 102742009A
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- Prior art keywords
- die attach
- attach pad
- nude film
- lead frame
- lead
- Prior art date
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Abstract
本发明描述改进将裸片向下接合到裸片附着垫的接合线的可靠性的多种半导体封装布置及封装方法。在一个方面中,对引线框架(其可呈嵌板形式)的顶部表面的选定部分进行镀敷(例如,镀银)以促进线接合。镀层覆盖所述裸片附着垫的裸片附着表面中的一些表面而非全部。在一些优选实施例中,将所述裸片附着垫上的所述镀层布置为环绕裸片支撑表面的未经镀敷中心区的外围环。在其它实施例中,所述裸片附着垫上的所述镀层采取条或不完全覆盖所述裸片支撑表面的其它几何图案的形式。将所述裸片支撑表面的未经镀敷部分粗糙化以改进所述裸片到所述裸片附着垫的粘附,借此减小裸片附着垫脱层及与向下接合的接合线相关联的风险的概率。可在多种封装中使用所述所描述的引线框架。最常见地,将裸片附着到所述裸片附着垫的所述裸片支撑表面且视情况通过线接合电连接到引线框架引线。将所述裸片的接合垫中的至少一者(通常为接地接合垫)向下接合到所述裸片附着垫。接着,通常用塑料囊封剂材料囊封所述裸片、所述接合线以及所述引线框架的至少若干部分,同时使所述裸片附着垫的接触表面暴露以促进将所述裸片附着垫电耦合到外部装置。
Description
技术领域
本发明大体来说涉及基于引线框架的半导体封装。更特定来说,本发明描述增强电耦合到裸片附着垫的接合线的可靠性的布置。
背景技术
许多半导体封装利用金属引线框架来提供集成电路裸片与外部组件之间的电互连件。通常使用称为“接合线”的极小电线将裸片上的I/O垫(经常称为“接合垫”)电连接到引线框架中的对应引线。通常,以塑料囊封裸片、接合线及引线框架的若干部分以进行保护,同时使引线框架的若干部分暴露以促进到外部装置的电连接。
许多引线框架包含在封装的组装期间支撑裸片的裸片附着垫(DAP)。在一些封装中,在封装的表面(通常为底部表面)上暴露裸片附着垫。经暴露裸片附着垫可有助于对封装的热管理,因为所述裸片附着垫提供用于耗散由裸片产生的过量热的良好热传导路径。在一些经暴露DAP封装中,裸片附着垫还用作封装的电触点。最常见地,裸片附着垫用作接地垫,但在几种封装中,其可用作电力垫且理论上其可替代地用作信号垫。
在一些应用中,例如,当裸片附着垫用作电触点时,使用接合线将裸片上的一个或一个以上接地I/O垫电连接到裸片附着垫(经常称为“向下接合”的工艺)。最常见地,使用极细金线作为接合线,且引线框架由铜或基于铜的合金形成。由于金不能良好地粘附到铜,因此通常用银薄膜对裸片附着垫(及引线框架的其它相关部分)进行镀敷,银比铜好得多地粘附到金接合线。偶尔发生的问题是在装置的使用期间裸片有时将从裸片附着垫脱层。当裸片附着垫脱层发生时,裸片相对于裸片附着垫的移动有时可能将向下接合线与裸片附着垫拆离或以其它方式使向下接合线断裂。
虽然现有向下接合技术很有效,但仍不断努力地以具成本效益的方式进一步改进向下接合可靠性。
发明内容
本发明描述改进将裸片向下接合到裸片附着垫的接合线的可靠性的多种半导体封装布置及封装方法。在一个方面中,对引线框架(其可呈嵌板形式)的顶部表面的选定部分(包含裸片附着垫的若干部分(而非全部))进行镀敷(例如,镀银)以促进线接合。在一些优选实施例中,将所述裸片附着垫上的镀层布置为环绕裸片支撑表面的开放中心区的外围环。在其它实施例中,可在裸片附着垫上的任何所期望及适当位置上选择性地镀敷条或其它几何图案。将所述裸片支撑表面的未经镀敷部分粗糙化以改进所述裸片到所述裸片附着垫及模制化合物到所述裸片附着垫的粘附性,借此减小裸片附着垫脱层及与向下接合的接合线相关联的风险的概率。可在多种封装中使用所描述的引线框架。最常见地,将裸片附着到所述裸片附着垫的所述裸片支撑表面且视情况通过线接合电连接到引线框架引线。将裸片的接合垫中的至少一者(通常为接地接合垫)向下接合到所述裸片附着垫。接着,通常用塑料囊封剂材料囊封所述裸片、所述接合线及所述引线框架的至少若干部分,同时使所述裸片附着垫的接触表面暴露以促进将所述裸片附着垫电耦合到外部装置。
可在多种封装工艺中使用所描述的引线框架。最常见地,将裸片附着到所述裸片附着垫的所述裸片支撑表面且视情况通过线接合电连接到引线框架引线。将裸片的接合垫中的至少一者(通常为接地接合垫)向下接合到所述裸片附着垫。接着,通常用塑料囊封剂材料囊封所述裸片、所述接合线及所述引线框架的至少若干部分。在经暴露裸片附着垫封装中,使裸片附着垫的接触表面暴露以促进将裸片附着垫电耦合到外部装置。当裸片的接地垫向下接合到裸片附着垫时,经暴露裸片附着垫变为封装的接地触点。
在本发明的各种设备方面中,描述多种新颖封装设计。在一些实施例中,裸片安装于引线框架裸片附着垫上。裸片附着垫的第一部分镀敷有导电镀敷材料。裸片附着垫的第二未镀敷部分以改进裸片到裸片附着垫的粘附的方式粗糙化,借此减小裸片从裸片附着垫脱层的概率。在一些优选实施例中,导电镀层为基于银的镀敷材料,其形成为环绕裸片支撑表面的经粗糙化第二部分的环。在其它实施例中,可在裸片附着垫上的适当位置处形成镀敷材料条。裸片上的选定接合垫(通常为接地垫)向下接合到裸片附着垫的经镀敷部分。
附图说明
可通过参考结合附图进行的以下描述来最佳地理解本发明及其优点,附图中:
图1(a)是根据本发明的一个实施例具有镀银裸片附着垫环的引线框架嵌板的示意性俯视图。
图1(b)是图1(a)中所图解说明的引线框架嵌板中的单个装置区域的示意性俯视图。
图2(a)是图解说明根据本发明的一个实施例制备引线框架嵌板及封装集成电路装置的方法的流程图。
图2(b)是图解说明根据本发明的另一实施例制备引线框架嵌板及封装集成电路装置的方法的流程图。
图3(a)到3(g)是图解说明单个装置区域的示意性横截面图,其图解说明根据本发明的图2(a)中所图解说明的实施例的形成图1的引线框架嵌板及随后封装集成电路中的数个步骤。
图4是根据本发明的实施例形成的经单个化封装的示意性横截面图。
图5是根据本发明的另一实施例的引线框架嵌板的单个装置区域的示意性俯视图,所述引线框架嵌板具有镀敷于裸片附着垫上的多个条。
在图式中,相似参考编号有时用以标示相似结构元件。还应了解,各图中的描绘为示意性且并非按比例绘制。
具体实施方式
本发明大体来说涉及增强电耦合到裸片附着垫的接合线的可靠性的封装方法及布置。一般来说,对引线框架的顶部表面的选定部分进行镀敷以促进线接合。镀层覆盖裸片附着垫的裸片附着表面中的一些表面而非全部。在一些优选实施例中,所述裸片附着垫上的镀层布置为环绕裸片支撑表面的未经镀敷中心区的外围环。在其它实施例中,可在裸片附着垫上的适合位置处形成条或其它几何镀层条。所述裸片支撑表面的未经镀敷部分经粗糙化以改进裸片到裸片附着垫的粘附,借此减小裸片附着垫脱层及与向下接合的接合线相关联的风险的概率。
首先参考图1(a)及1(b),将描述根据本发明的一个实施例布置的引线框架嵌板100。如图1(a)中最佳所见,引线框架嵌板100包含多个装置区域105。所述装置区域在所述嵌板上布置成一个或一个以上二维阵列,但可能有多种其它布置(例如,一维阵列、非线性布置等)。在所图解说明的实施例中,展示装置区域的四个二维阵列。然而,应了解,可提供更多或更少的阵列。所述引线框架嵌板通常由铜或基于铜的合金形成,但可在各种替代实施例中使用其它适合材料(例如,铝)。
装置区域的特定配置将根据任何特定封装的需要而变化。举例来说,图1(b)图解说明装置区域105的一个可能配置,其采取适合在封装无引线引线框架(LLP)型封装(也称作QFN型封装)时使用的形式。虽然展示LLP型封装,但应了解,可结合利用到裸片附着垫的向下接合或其它线接合或者以其它方式具有在裸片附着垫的区上提供镀层的原因的几乎任何基于引线框架的封装来使用本发明。举例来说,所描述的发明非常适合在SOIC、TSSOP、QFP、TO-220及TO-263型封装及多种多样的其它封装式样中使用。
主要参考图1(b),每一装置区域105包含裸片附着垫110及多个引线触点113。系条(支撑条)116的矩阵经布置以支撑裸片附着垫110及引线触点113。引线框架的顶部表面的选定部分镀敷有经设计以改进接合线粘附的导电镀敷材料120。当使用铜或铜合金来形成引线框架时,导电镀层通常为良好粘附到金接合线的银。然而,应了解,可使用其它适合镀敷材料来代替银,只要所述镀敷材料改进接合线到引线框架嵌板的粘附即可。
裸片附着垫110的顶部表面的一部分而非全部镀敷有导电镀敷材料120。裸片附着垫上的镀层的几何形状可根据任何特定设计的需要而广泛地变化。最重要的点是镀层应存在于裸片附着垫的将向下接合到的区中。在所图解说明的实施例中,裸片附着垫上的导电镀敷材料布置为环绕裸片附着垫的未镀敷中心区123的外围环122。此镀层几何形状在许多应用中很有效,因为其允许向下接合到裸片附着垫的任何外部部分。引线触点113上的镀层125至少覆盖所述引线触点的既定充当用于线接合的附着点的区。
图5中图解说明替代镀层几何形状。在此实施例中,在裸片附着垫的选定区而非外围环122上镀敷银条124。此布置尤其适于在其中多个装置(例如,IC、无源组件等)由裸片附着垫承载及/或附着到裸片附着垫的多芯片模块(MCM)中使用。所述条可位于裸片附着垫的外围边缘处(例如条124(a)及124(b))及/或可适于任何特定封装要求的其它较中心位置处(例如124(c))。在又一些实施例(例如具有并不在裸片的所有侧上均具有接地I/O垫的裸片的封装)中,可能期望仅对裸片的外围边缘进行镀敷(例如,仅使用外围条124(a)及124(b))。外围条可沿着裸片附着垫的一个、两个、三个或所有四个侧的一部分或全部定位。较居中定位的图案(例如,条124(c))可定位于裸片附着垫上的任何适当位置处。应了解,镀层的几何形状并不限于矩形条,而是可使用任何适当镀层几何形状。
可使用数种不同镀敷工艺来镀敷图1中所图解说明的引线框架嵌板100且此后利用所述引线框架嵌板来封装集成电路。将参考图2(a)的流程图及图3(a)到3(g)的图式来描述本文中称为掩模镀敷工艺的一种适合工艺。将参考图2(b)的流程图来描述本文中称为选择性镀敷工艺的第二镀敷工艺。当然,也可使用多种其它镀敷工艺。
接下来参考图2(a)及图3(a)到3(g),将描述掩模镀敷工艺。在此实施例中,首先对引线框架嵌板100进行图案化以界定引线/引线触点113、裸片附着垫110及引线框架嵌板的其它特征。(步骤202,图3(a))。可使用例如蚀刻、模压或两者的组合的常规技术对嵌板进行图案化。
在已对引线框架嵌板进行图案化之后,将图案化的引线框架安装于载体130上(步骤203,图3(b))。可使用多种载体。在所图解说明的实施例中,使用例如基于聚酰亚胺的胶带的载体胶带,但在替代实施例中可使用任何其它适合载体。
在已施加载体之前或之后,使用常规镀银技术对引线框架的顶部表面的选定部分进行镀银。以常规方式(例如,电镀)将镀银材料施加到引线触点的线接合焊盘区以形成引线镀层125。同时,还对裸片附着垫的部分而非全部进行镀敷以形成裸片附着垫镀层122。(步骤204,图3(c))。在图3(c)中所图解说明的实施例中,裸片附着垫上的镀层布置为外围环,其覆盖裸片附着垫的顶部表面的外部部分,从而使裸片附着垫的中心区123未被镀敷。所述外围环为有用的几何形状,因为所述环在裸片附着垫的的所有侧上均提供向下接合区。环几何形状易于掩蔽且可与附着到裸片附着垫110的几乎任何裸片一起使用。虽然外围环在许多实施方案中为有用的,但应了解,许多裸片将并非在裸片的所有侧上均具有接地接合垫。在此些实施方案中,可能不需要在裸片附着垫的所有侧上提供银镀层。因此,在替代实施例中,可仅在裸片附着垫的较小区中放置银镀层,例如沿着裸片附着垫的仅仅一个或两个侧、仅沿着裸片附着垫的一个或一个以上侧的在待向下接合到的特定区域中的部分,或者在任何其它所要几何形状中。
应了解,可使用多种镀敷技术来镀敷引线框架的所期望部分。在所图解说明的实施例中,使用掩模(未展示)来覆盖引线框架的顶部表面的将不镀敷的部分。所述掩模可采取任何适合形式。举例来说,常规机械掩模(例如,橡胶印模)对于此用途很有效,但也可使用其它适当掩模。
在所描述的实施例中,使用银作为导电镀敷材料,因为与铜引线框架相比金接合线更好地粘附到银。虽然在所描述的实施例中使用银,但应了解,导电镀敷材料的主要功能为改进接合线到引线框架的附着。因此,在替代实施例中,引线框架的适当部分可镀敷有改进用作接合线的特定材料到用作引线框架的特定材料的粘附的其它适合导体。
在已对引线框架进行镀银之后,使所述引线框架经受引线框架处理,所述处理“纹理化”或“粗糙化”引线框架的未经镀银的经暴露表面。(步骤206,图3(d))。引线框架的经暴露部分包含裸片附着垫110的裸片支撑表面的中心区123、引线的侧边缘117及裸片附着垫的侧边缘118,且可能地包含引线113的顶部表面的未经镀银的部分。在所图解说明的实施例中,在载体附着到引线框架的底部表面的情况下执行引线框架处理,使得引线框架的底部表面不被暴露于引线框架处理且因此不被粗糙化。
裸片附着垫110的顶部表面的经粗糙化区(例如,中心区123)改进在随后将裸片附着到裸片附着垫时裸片到裸片附着垫的粘附。裸片附着垫及引线的经粗糙化侧表面有助于改进在随后囊封裸片时模制材料到引线框架的粘附。
在一些经暴露裸片附着垫塑料模制封装中,可能不期望粗糙化引线框架的既定被暴露且用作触点的表面,因为模制材料可能在囊封期间穿透到经纹理化表面中的通孔中,借此显著降低接触表面的电性能。然而,如果不暴露裸片附着垫,那么处理裸片附着垫的底部表面使得模制材料更好地粘附到裸片附着垫可为可接受及/或所期望的。在此些实施例中,放弃载体130的附着(步骤203)或在引线框架表面处理之前移除载体可为所期望的。类似地,如果所使用的表面处理不容易出现显著模制材料穿透担忧问题,那么可在不附着载体130的情况下容易地执行表面处理。
如熟悉引线框架领域的人员将了解,存在可用以纹理化引线框架的经暴露部分的数种商业上可行的铜引线框架表面处理。优选地,选择不显著侵蚀银镀层的引线框架表面处理。因此,银镀层不会被粗糙化或在其它方面受所述处理的不利影响。大多数商业上可行的引线框架处理满足此要求,因此可利用多种商业上可行的引线框架处理中的任一者来进行引线框架处理步骤206。举例来说,由Possehl Electronics出售的L1表面处理工艺、由Dynacraft执行的微蚀刻工艺或由ASM执行的氧化铜工艺全部为对于既定用途很有效的适合引线框架表面处理。
在已完成引线框架处理之后,所述引线框架可用以使用多种不同封装技术来封装集成电路。举例来说,可在步骤208中将裸片140安装于每一裸片附着垫110上并使用常规裸片附着技术(例如,使用裸片附着粘合剂141)将裸片140以粘附方式紧固到每一裸片附着垫110(图3(e))。在所图解说明的实施例中,裸片140在裸片附着垫110上居中,以便在裸片的每一侧上暴露银镀层。然而,在替代实施例中,裸片不需要相对于裸片附着垫居中。银镀层条带的宽度可任选地经选择使得裸片不上覆在银镀层上。此布置具有提供最强裸片附着的优点,因为用以安装裸片的粘合剂将不像其粘着到经粗糙化铜表面123一样好地粘着到银镀层。然而,此并非一要求且在各种实施例中,裸片可部分地上覆在银镀层中的一些银镀层(优选地所述银镀层的仅相对小的量)上。实际上,允许某一小重叠有时为所期望的,因为其允许在施加导电镀敷材料时使用更灵活容限。
在已将裸片140附着到裸片附着垫110之后,可使用常规线结合技术将其电连接到引线框架。(步骤210)。通常,每一接合线的一端附着到裸片上的相关联接合垫141,且每一接合线的第二端附着到引线框架的镀银部分120,如图3(f)中所图解说明。通常,接合线中的大多数(图3(f)中标示为145)各自连接到相关联引线116。然而,接合线中的至少一者(及通常为一者以上)(图3(f)中标示为146)向下接合到裸片附着垫的镀银部分122。通常,裸片上的接地I/O垫向下接合到裸片附着垫,使得所述裸片附着垫变为用于最终封装的接地触点。然而,此并非一要求,因此在其它实施例中,裸片附着垫可为电力触点或甚至可能为信号触点。
在已附着裸片并将其线接合到引线框架之后,可使用例如塑料模制的常规囊封技术在步骤212中囊封裸片及接合线连同引线框架的若干部分,如图3(g)中所展示。所图解说明的实施例为LLP型封装,因此引线触点116的底部表面及裸片附着垫113的底部表面既定保持暴露。在所图解说明的实施例中,载体胶带130在整个封装过程(包含囊封)中保持粘附到引线框架嵌板100的底部表面。因此,所述载体胶带防止在囊封过程期间模制材料覆盖触点。
在囊封及任何其它所期望嵌板级处理之后,可在步骤214中将嵌板单个化以形成个别半导体封装。单个化可经布置以牺牲系条116。图4中示意性地图解说明经单个化封装。
图2(b)中图解说明替代镀敷工艺。在此实施例中,首先对坯料(未经图案化)引线框架条带或嵌板的选择性部分进行镀银(步骤201)。以在其中期望镀层且使引线框架的其它部分暴露的区中提供镀层的方式对镀层进行图案化。与先前所描述的工艺一样,可使用任何适合掩模(例如基于光致抗蚀剂的掩模)来实现选择性镀敷。
在已选择性地镀敷引线框架坯料之后,对引线框架进行图案化(步骤202)以界定引线框架的所期望特征(例如,引线、触点、裸片附着垫等)。如上文所论述,可使用任何适合技术(例如,模压或蚀刻)来对引线框架进行图案化。在图案化之后,可使整个引线框架嵌板经受引线框架处理(步骤206)。在引线框架处理之前或之后,可将引线框架嵌板安装于适当载体上(步骤207)。在图2(b)中所图解说明的实施例中,在引线框架处理之后附着载体,但如先前所论述,在替代实施例中,可在引线框架处理之前施加载体,且可能有充分的理由来如此操作。
在引线框架处理及载体附着之后,图2(b)的封装工艺可采取类似于上文关于图2(a)所描述的工艺的流程。
图4中图解说明根据所描述的工艺中的任一者形成的代表性经单个化封装。如其中所见,封装400包含具有裸片附着垫110及多个引线触点113的引线框架107。导电镀层环122覆盖裸片附着垫的顶部表面的外围表面。引线触点113的顶部表面的若干部分也为镀银的。多个接合线145将裸片140上的选定接合垫电连接到相关联引线触点113,且一个或一个以上向下接合的接合线146从裸片140向下接合到裸片附着垫110以将裸片上的接地接合垫电连接到所述裸片附着垫。裸片、接合线145、146及引线框架107的若干部分囊封于塑料囊封剂150中,从而使引线触点及裸片附着垫的底部接触表面暴露以促进到外部装置的电连接。
在上文所描述的实施例中,主要因以下事实而大致减少向下接合故障:裸片附着垫110的裸片支撑表面的大部分(例如,经粗糙化中心区123)的表面处理显著减小裸片附着垫脱层的概率,裸片附着垫脱层被认为是向下接合故障的主要原因。如果期望,那么还可做出额外努力来改进向下接合的接合线146到裸片附着垫110的粘附。举例来说,裸片140上的接地I/O垫可使用楔形倒缝球球接合(RBSOB)技术耦合到经接地裸片附着垫110。在此方法中,首先在裸片140上的适当接地I/O垫上形成线接合凸块。通过使用标准线接合毛细管将球接合超声波沉积到选定接合垫上来制成所述凸块。并非继续线的挤出,而是毛细管在球接合的顶部附近将线截断,使得仅线接合“球”或“凸块”保持在接合垫顶部。
接着使用倒线接合将接地I/O垫电耦合到裸片附着垫。在线接合过程期间,在裸片附着垫上形成第二球接合,且在接地I/O垫上的凸块的顶部上形成缝合接合。在此布置的情况下,向下接合线经由位于凸块顶部的缝合接合电耦合到接地I/O垫。凸块的高度可根据特定实施例的需要而变化。举例来说,在一些实施例中,具有大约为常规球接合的高度的三分之一的高度的凸块很有效。所描述的倒缝球线接合技术改进接地接合线到引线框架的粘附。这是因为球接合比缝合接合将实现的情况更好地粘附到裸片附着垫的镀银部分。
虽然已详细地描述本发明的仅几个实施例,但应了解,可以许多其它形式实施本发明,此并不背离本发明的精神或范围。虽然已图解说明LLP型封装的形成,但应了解,本发明可与并入有到裸片附着垫的向下接合的任何封装一起使用。此外,虽然在描述所图解说明的实施例时明确表达了特定步骤及特定次序,但应了解,在许多实例中,所使用的特定步骤以及其次序可变化,此并不背离本发明的范围。
认为在许多应用中,所描述的裸片附着垫表面处理技术将充分地消除裸片与裸片附着垫之间的脱层问题,使得将不需要进一步过程来改进向下接合可靠性。然而,在期望时,除上文所描述的缝球技术以外,可与所描述的方法并行地采用其它互补技术(向下接合增强技术)以进一步改进向下接合可靠性。因此,本发明实施例应视为说明性而非限制性,且本发明不应限于本文中所给出的细节而是可在所附权利要求书的范围内加以修改。
Claims (25)
1.一种集成电路封装,其包括:
引线框架,其包含裸片附着垫及与所述裸片附着垫物理且电隔离的多个引线,所述裸片附着垫包含裸片支撑表面,其中所述裸片支撑表面的第一部分镀敷有导电镀敷材料,且所述裸片支撑表面的第二部分被粗糙化;
裸片,其附着到所述裸片附着垫的所述裸片支撑表面,所述裸片具有多个接合垫,其中所述裸片支撑表面的所述经粗糙化第二部分经布置以改进所述裸片到所述裸片支撑表面的粘附;
第一组接合线,其中所述第一组接合线中的每一接合线具有附着到相关联接合垫的第一端及附着到相关联引线的第二端,借此将所述相关联接合垫电连接到所述相关联引线;及
至少一个向下接合线,其中每一向下接合线具有附着到相关联接合垫的第一端及附着到所述裸片附着垫上的导电镀层的第二端。
2.根据权利要求1所述的集成电路封装,其进一步包括塑料囊封剂,所述塑料囊封剂囊封所述裸片、所述接合线以及所述引线框架的至少若干部分,同时使所述裸片附着垫的接触表面暴露以促进将所述裸片附着垫电耦合到电触点。
3.根据权利要求2所述的集成电路封装,其中所述裸片附着垫电连接到接地。
4.根据前述权利要求中任一权利要求所述的集成电路封装,其中所述导电镀层布置为环绕所述裸片支撑表面的所述经粗糙化第二部分的环。
5.根据权利要求4所述的集成电路封装,其中所述镀层为基于银的镀层,且所述接合线由金形成。
6.根据前述权利要求中任一权利要求所述的集成电路封装,其中多个向下接合线耦合到所述裸片附着垫上的所述导电镀层。
7.根据前述权利要求中任一权利要求所述的集成电路封装,其中:
所述引线框架由铜或基于铜的合金形成;
所述引线为各自具有相关联线接合表面及相对接触表面的引线触点;
所述导电镀层为银镀层,且所述裸片附着垫上的所述银镀层界定覆盖裸片附着表面的外围部分的银镀层环,且其中银镀层进一步提供于每一引线的所述线接合表面的至少一部分上;且
所述银镀层环具有暴露所述裸片支撑表面的中心部分的中心开口,其中所述裸片支撑表面的所述中心部分以及所述裸片附着垫及引线触点的侧部分被粗糙化,且其中所述裸片附着垫的与所述裸片支撑表面相对定位的接触表面未被粗糙化,且所述引线触点的所述接触表面未被粗糙化。
8.根据权利要求7所述的集成电路封装,其进一步包括塑料囊封剂,所述塑料囊封剂囊封所述裸片、所述接合线以及所述引线框架的至少若干部分,同时使所述引线触点的所述接触表面在所述封装的底部表面上暴露且使所述裸片附着垫的接触表面在所述封装的底部表面上暴露。
9.一种使用包含裸片附着垫的导电引线框架来封装集成电路的方法,所述方法包括:
将载体粘附到所述引线框架的底部表面;
用导电镀敷材料镀敷所述引线框架的顶部表面的选定部分,其中所述引线框架的所述经镀敷部分包含所述裸片附着垫的裸片支撑表面的一部分而非全部;
在所述载体粘附到所述引线框架的所述底部表面的情况下将所述经镀敷引线框架暴露于引线框架处理以将所述引线框架的未被镀敷的经暴露部分粗糙化,所述经暴露部分包含所述裸片支撑表面的未被镀敷的部分,其中所述引线框架处理大致不将经镀敷区粗糙化;
将裸片附着到所述裸片附着垫的所述裸片支撑表面,所述裸片具有多个接合垫,其中所述裸片支撑表面的所述经粗糙化部分经布置以改进所述裸片到所述裸片支撑表面的粘附;
将所述裸片电耦合到引线中的至少一些引线;及
将所述裸片上的所述接合垫中的至少一者线接合到所述裸片附着垫的所述经镀敷部分。
10.根据权利要求9所述的方法,其中:
由铜或基于铜的合金形成所述引线框架;
由金形成接合线;且
导电镀层为银镀层。
11.根据权利要求10所述的方法,其中将所述裸片附着垫上的所述银镀层布置为环绕所述裸片支撑表面的经粗糙化第二部分的环。
12.根据权利要求9到11中任一权利要求所述的方法,其进一步包括用塑料囊封剂材料囊封所述裸片、所述接合线以及所述引线框架的至少若干部分,同时使所述裸片附着垫的接触表面暴露以促进将所述裸片附着垫电耦合到电触点。
13.根据权利要求9到12中任一权利要求所述的方法,其中将所述裸片附着垫上的所述镀层布置为环绕所述裸片支撑表面的所述经粗糙化第二部分的环。
14.一种使用根据权利要求9到13中任一权利要求所述而形成的集成电路封装的方法,其包括将所述经封装集成电路安装于其上具有电互连件的衬底板上,其中以将所述裸片附着垫以及所述引线中的至少一些引线电连接到所述板的方式来安装所述经封装集成电路。
15.根据权利要求14所述的方法,其中将所述裸片附着垫电连接到接地。
16.根据权利要求9到15中任一权利要求所述的方法,其中将多个接合线向下线接合到所述裸片附着垫。
17.根据权利要求9到16中任一权利要求所述的方法,其中:
由铜或基于铜的合金形成所述引线框架;
由金形成所述接合线;
所述引线为各自具有相关联线接合表面及相对接触表面的引线触点;
所述导电镀层为银镀层,且所述裸片附着垫上的所述银镀层界定覆盖裸片附着表面的外围部分的银镀层环,且其中在每一引线的所述线接合表面的至少一部分上进一步提供银镀层;且
所述银镀层环具有暴露所述裸片支撑表面的中心部分的中心开口,其中在所述引线框架处理期间将所述裸片支撑表面的所述中心部分以及所述裸片附着垫及引线触点的侧部分粗糙化,且其中不将所述引线触点的所述接触表面及所述裸片附着垫的所述底部表面粗糙化。
18.一种制备供在封装集成电路时使用的导电引线框架嵌板的方法,所述引线框架嵌板具有界定于其上的多个装置区域,每一装置区域包含多个引线及一裸片附着垫,所述方法包括:
将载体粘附到所述引线框架嵌板的底部表面;
对所述引线框架嵌板的顶部表面的选定部分进行镀银,其中界定于所述引线框架嵌板中的每一装置区域的所述镀银部分包含所述裸片附着垫的裸片支撑表面的一部分;
在所述载体粘附到所述引线框架嵌板的所述底部表面的情况下将所述镀银引线框架嵌板暴露于引线框架处理以将所述引线框架嵌板的未被镀银的经暴露部分粗糙化,其中所述引线框架处理大致不将所述引线框架嵌板的镀银区粗糙化。
19.根据权利要求18所述的方法,其中所述裸片附着垫中的每一者的所述镀银部分界定银镀层环,所述银镀层环覆盖相关联裸片支撑表面的外围部分同时暴露所述相关联裸片支撑表面的中心部分,其中在所述引线框架处理期间将所述裸片支撑表面的所述中心部分以及所述裸片附着垫及引线触点的侧部分粗糙化,且其中在所述引线框架处理期间不将所述引线触点的接触表面及所述裸片附着垫的底部表面粗糙化。
20.根据权利要求18或19所述的方法,其中在每一引线的线接合表面的至少一部分上进一步提供银镀层。
21.根据权利要求1所述的集成电路封装,其中所述导电镀层布置为环绕所述裸片支撑表面的所述经粗糙化第二部分的环。
22.根据权利要求1所述的集成电路封装,其中:
所述引线框架由铜或基于铜的合金形成;
所述引线为各自具有相关联线接合表面及相对接触表面的引线触点;
所述导电镀层为银镀层,且所述裸片附着垫上的所述银镀层界定覆盖所述裸片附着表面的外围部分的银镀层环,且其中银镀层进一步提供于每一引线的所述线接合表面的至少一部分上;且
所述银镀层环具有暴露所述裸片支撑表面的中心部分的中心开口,其中所述裸片支撑表面的所述中心部分以及所述裸片附着垫及引线触点的侧部分被粗糙化,且其中所述裸片附着垫的与所述裸片支撑表面相对定位的接触表面未被粗糙化,且所述引线触点的所述接触表面未被粗糙化。
23.根据权利要求9所述的方法,其进一步包括用塑料囊封剂材料囊封所述裸片、所述接合线以及所述引线框架的至少若干部分,同时使所述裸片附着垫的接触表面暴露以促进将所述裸片附着垫电耦合到电触点。
24.根据权利要求9所述的方法,其中将所述裸片附着垫上的所述镀层布置为环绕所述裸片支撑表面的所述经粗糙化第二部分的环。
25.一种使用根据权利要求9所述而形成的集成电路封装的方法,其包括将所述经封装集成电路安装于其上具有电互连件的衬底板上,其中以将所述裸片附着垫以及所述引线中的至少一些引线电连接到所述板的方式来安装所述经封装集成电路,且其中将所述裸片附着垫电连接到接地。
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US12/637,657 | 2009-12-14 | ||
US12/637,657 US20110140253A1 (en) | 2009-12-14 | 2009-12-14 | Dap ground bond enhancement |
PCT/US2010/052189 WO2011081696A2 (en) | 2009-12-14 | 2010-10-11 | Dap ground bond enhancement |
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CN102742009A true CN102742009A (zh) | 2012-10-17 |
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US (1) | US20110140253A1 (zh) |
JP (1) | JP2013513968A (zh) |
CN (1) | CN102742009A (zh) |
TW (1) | TW201126658A (zh) |
WO (1) | WO2011081696A2 (zh) |
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CN116613131A (zh) * | 2023-06-02 | 2023-08-18 | 上海类比半导体技术有限公司 | 集成电路封装框架 |
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TWI480989B (zh) * | 2012-10-02 | 2015-04-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
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CN108074901A (zh) * | 2016-11-06 | 2018-05-25 | 安世有限公司 | 具有可湿拐角引线的半导体器件及半导体器件组装方法 |
CN108074901B (zh) * | 2016-11-06 | 2023-11-03 | 安世有限公司 | 具有可湿拐角引线的半导体器件及半导体器件组装方法 |
CN116613131A (zh) * | 2023-06-02 | 2023-08-18 | 上海类比半导体技术有限公司 | 集成电路封装框架 |
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JP2013513968A (ja) | 2013-04-22 |
US20110140253A1 (en) | 2011-06-16 |
TW201126658A (en) | 2011-08-01 |
WO2011081696A2 (en) | 2011-07-07 |
WO2011081696A3 (en) | 2011-09-22 |
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