CN103985690A - 树脂密封型半导体装置及其制造方法 - Google Patents

树脂密封型半导体装置及其制造方法 Download PDF

Info

Publication number
CN103985690A
CN103985690A CN201410048433.4A CN201410048433A CN103985690A CN 103985690 A CN103985690 A CN 103985690A CN 201410048433 A CN201410048433 A CN 201410048433A CN 103985690 A CN103985690 A CN 103985690A
Authority
CN
China
Prior art keywords
lead
semiconductor device
resin molded
cut
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410048433.4A
Other languages
English (en)
Other versions
CN103985690B (zh
Inventor
木村纪幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dynafine Semiconductor Co ltd
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN103985690A publication Critical patent/CN103985690A/zh
Application granted granted Critical
Publication of CN103985690B publication Critical patent/CN103985690B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

提供一种半导体装置及其制造方法，即使引线部端面中不存在镀层，当通过焊料接合剂将半导体装置接合到印刷基板等的安装基板时也能通过从密封树脂部露出的引线部的上表面部分在引线部端面形成焊料填角。该半导体装置包括芯片焊盘部上搭载的半导体元件、芯片焊盘部中对置配置其前端部的多个引线部、连接半导体元件的电极与引线部的金属细线，将这些部分地树脂密封的树脂密封型半导体装置的芯片焊盘部的底面部、引线部的引线底面部和外侧面部以及上侧端部从密封树脂露出，在引线部上侧端部上形成不具有密封树脂的切口部之后，在引线部底面部以及引线上侧端部施加镀层。

Description

树脂密封型半导体装置及其制造方法
技术领域
本发明涉及称为QFN、DFN的无引线类型的树脂密封型半导体装置及其制造方法。尤其涉及使引线端子部的安装可靠性提高的树脂密封型半导体及其制造方法。
背景技术
近年，为了应对电子设备的小型化，要求半导体零件的高密度安装，半导体零件的小型化和薄型化也随之得到发展。与BGA、CSP封装并列地，DFN、QFN型的半导体装置作为使用引线框架的小型封装而被实用化。
图7（a）是现有的DFN封装的背面图，图7（b）是其A-A线截面图。DFN封装将引线部13和在芯片焊盘（die pad）部12搭载的半导体元件11通过密封树脂16进行密封，使多个引线部13和芯片焊盘部12从其背面露出。在封装背面中多个引线部13在对置的两个方向中排列，它们形成外部引线。此外，多个引线部13在密封树脂16内通过金属细线14电连接到半导体元件11的表面电极。
因为使得多个引线部13不从树脂16向外部突出，所以DFN封装拥有能够使到安装基板的安装面积变小的优点。此外，通过使芯片焊盘部12从密封树脂16露出，能够高效率地使内部的发热向外部散发。但是，DFN封装中也有将芯片焊盘部12密封在密封树脂16内的构造。QFN封装是在封装背面中在四个方向使外部引线露出的结构。
图8是从上方观看树脂密封后的框架的俯视图，接着图9是图8中图示的框架的切断后的B-B截面图。采用如下方法，即如图8以及图9所示，通过密封树脂16将框架框的各芯片焊盘部12中搭载的半导体元件11密封之后，沿切断线利用切割（dicing）装置的旋转刀（blade）同时切断密封树脂16和引线部13，而单片化为如图10所示的各个半导体装置（例如，参照专利文献1）。
现有技术文献
专利文献
专利文献1：日本特表2002-519848号公报（图7）。
发明内容
发明要解决的问题
然而，虽然这种树脂密封型半导体装置在树脂密封后，通过旋转刀将引线部13的切断部位切断而从框架分离，从而得到各个半导体装置，但是因为是从框架切断引线部13而形成，所以如图11所示引线部13的切断部的端面中不存在镀层17，当使用焊料18将半导体装置接合到印刷基板等的安装基板20时，从引线部13的密封树脂部露出的侧面部分中不能通过焊料18形成焊料填角（fillet），有安装强度变弱安装可靠性降低的担忧。
参照图来说明安装的状态，图11是图10所示的圆内的放大图，示出半导体装置的引线部13。在引线被切断的引线部13从密封树脂16露出的引线部13的端面部，不存在其它引线部13的外部表面形成的镀层17。由此，如放大安装的状态的示意截面图的图12所示，通过焊料18等的接合剂将半导体装置安装到安装基板20时，在引线部13的端面部分不会形成焊料填角而安装强度降低。
本发明提供能够解决上述问题，改善DFN或者QFN类型的树脂密封型半导体装置的基板安装的强度以及提高安装可靠性的半导体装置及其制造方法。
解决问题的方案
为了解决上述问题，采用以下的方案。
首先，是一种树脂密封型半导体装置，其特征在于包括：芯片焊盘部；所述芯片焊盘部上搭载的半导体元件；所述芯片焊盘部中对置配置的多个引线部；连接所述半导体元件的多个电极与所述多个引线部的金属细线；以及以使所述多个引线部部分地露出的方式密封所述芯片焊盘部、所述半导体元件以及所述多个引线部的密封树脂，所述多个引线部具备从所述密封树脂露出的作为底面的引线底面部、作为前端的引线外侧面部和作为上表面的一部分的引线上侧端部，所述引线底面部与所述密封树脂的底面在同一面内，所述引线底面部以及所述引线上侧端部具有镀层，所述引线上侧端部的铅垂上方所述密封树脂隔着不具有所述密封树脂的切口部而存在。
此外，所述树脂密封型半导体装置的特征在于：所述引线外侧面部比所述密封树脂的侧面更加向外侧突出。
此外，所述树脂密封型半导体装置的特征在于：所述引线外侧面部与所述密封树脂的侧面为同一面。
此外，所述树脂密封型半导体装置的特征在于：所述引线底面部的镀层以及所述引线上侧端部的镀层由铅、铋、锡、铜、银、钯、金中的任何一个的金属层或者两个以上的合金层构成。
此外，所述树脂密封型半导体装置的特征在于：所述切口部为“コ”字型。
此外，所述树脂密封型半导体装置的特征在于：所述芯片焊盘部的底面部从所述密封树脂露出。
此外，所述树脂密封型半导体装置的特征在于：所述引线部由内部引线部和外部引线部构成，内部引线部以比外部引线部高的方式进行折弯。
此外，采用的树脂密封型半导体装置的制造方法，其特征在于包括：
将芯片焊盘部以及在所述芯片焊盘部对置配置的多个引线部作为一个单元，准备具有多个该单元的框架或者电铸基板的工序；
在所述框架或者电铸基板的第一面贴上密封片（sheet）的工序；在所述引线部的与所述第一面相反侧的第二面形成可溶性膜的工序；在所述框架或者电铸基板的所述芯片焊盘部各自搭载半导体元件，通过金属细线将所述引线部和所述半导体元件的表面的电极连接的工序；以使所述多个引线部的引线底面部露出的方式通过密封树脂来树脂密封所述芯片焊盘部、所述半导体元件和所述引线部的工序；溶解去除所述可溶性膜，形成空洞部的工序；
将所述框架或者电铸基板浸入镀液以在所述引线底面部和所述引线上侧端部形成镀层的工序；从所述第一面一侧对所述引线部施行第一切断，形成到达所述空洞部的第一槽的工序；从与所述第一面相反侧的第二面一侧对所述密封树脂施行第二切断，从所述框架或者电铸基板分离树脂密封型半导体装置的工序。
此外，采用的树脂密封型半导体装置的制造方法，其特征在于：所述第一切断是冲孔切断，所述第二切断是旋转刀切断。
此外，采用的树脂密封型半导体装置的制造方法，其特征在于：所述第一切断是冲孔切断，所述第二切断也是冲孔切断。
此外，采用的树脂密封型半导体装置的制造方法，其特征在于：所述第一切断是旋转刀切断，所述第二切断也是冲孔切断。
此外，采用的树脂密封型半导体装置的制造方法，其特征在于：所述旋转刀情况下的切断宽度比所述冲孔切断情况下的切断宽度宽，比所述空洞部的宽度窄。
此外，采用的树脂密封型半导体装置的制造方法，其特征在于：所述旋转刀情况下的切断宽度与所述冲孔切断情况下的切断宽度相同，比所述空洞部的宽度窄。
发明效果
通过采用上述方案，在将本发明的树脂密封型半导体装置焊料接合到印刷基板等安装基板的凸台（land）部时，因为设在引线部的引线上侧端部的镀层也形成焊料填角，所以能够改善安装强度，提高安装可靠性。而且，在基板安装时，通过在引线端面部形成形状良好的焊料填角，而能够改善安装后的接合部外观检查时的识别精度，防止识别不良。
附图说明
图1是本发明一个实施例的搭载半导体元件的框架的俯视图。
图2示出本发明的一个实施方式的树脂密封型半导体装置的制造方法，（a）是俯视图，（b）~（d）是截面图。
图3是接着图2示出本发明的一个实施方式的树脂密封型半导体装置的制造方法的截面图（e）~（i）。
图4是接着图3示出本发明的一个实施方式的树脂密封型半导体装置的制造方法的截面图（j）~（k）。
图5是示出本发明的一个实施方式的树脂密封型半导体装置的截面图。
图6是示出本发明的一个实施方式的树脂密封型半导体装置的截面图（安装状态放大图）。
图7是示出现有的树脂密封型半导体装置的图。
图8是示出现有的树脂密封型半导体装置的制造方法的框架俯视图。
图9是示出现有的树脂密封型半导体装置的制造方法的截面图。
图10是现有的树脂密封型半导体装置的截面图。
图11是示出现有的树脂密封型半导体装置的截面图（引线部放大图）。
图12是示出现有的树脂密封型半导体装置的截面图（安装状态放大图）。
图13是示出现有的树脂密封型半导体装置的截面图（安装状态放大图）。
具体实施方式
以下关于本发明的树脂密封型半导体装置及其制造方法的一个实施方式参照图进行说明。
首先，关于本实施例的框架进行说明。
图1是本实施例的搭载半导体元件的框架或者电铸基板的俯视图，图2（a）是半导体元件搭载前的框架俯视图，图2（b）~图4（k）是示出半导体装置的制造方法的截面图。本实施例的半导体装置如图1所示，框架由铜（Cu）材料构成，将芯片焊盘部12上搭载的半导体元件11和在芯片焊盘部12中对置配置其前端部的多个引线部13作为一个单元，该框架为具有多个该单元的结构。图中的虚线示出在搭载半导体元件11构成树脂密封型半导体装置的情况下的通过密封树脂16密封的区域，此外双点划线所示的线示出搭载半导体元件11之后、进行树脂密封、构成树脂密封型半导体装置之后分离为各个半导体装置的切断线。
接着关于本实施例的树脂密封型半导体装置进行说明。图5是示出使用图1所示的框架制造的一个树脂密封型半导体装置的图，是沿图1中的右上示出的B-B切断线的截面图。
如图5所示，框架的芯片焊盘部12上搭载半导体元件11，该半导体元件11上的电极与引线部13的内部引线部通过金属细线14电连接。引线部13由内部引线部和外部引线部构成，内部引线部以比外部引线部高的方式进行折弯。然后，芯片焊盘部12上的半导体元件11、金属细线14、引线部13通过密封树脂16进行密封。芯片焊盘部12的与半导体元件11搭载面相反侧的背面从密封树脂16露出，其露出面通过镀层17进行覆盖。镀层17由铅、铋、锡、铜、银、钯、金中的任何金属或者多个金属的合金构成，通过电解镀法或者无电解镀法形成。在芯片焊盘部12的端面设有使芯片焊盘的厚度变薄的薄壁部25，密封树脂16迂回进入薄壁部25的背面以成为难以从密封树脂16抽出芯片焊盘部12的结构。
引线部13的内部引线部通过密封树脂16进行密封，但是与芯片焊盘部12背面以及密封树脂16底面为同一平面的外部引线部的引线底面部19a从密封树脂16露出，在其露出面覆盖镀层17。密封树脂16的侧面以引线部13的外部引线部的引线上侧端部19b露出的方式设有“コ”字型的切口部22，外部引线部的引线上侧端部19b上也形成镀层17，并被覆盖。引线的前端是引线被切断的引线外侧面部19c，未进行镀膜。
图6是示出将图5中示出的树脂密封型半导体装置安装在基板上的状态的图。安装基板20上设有导电性的凸台部21，通过镀层17以及焊料18与树脂密封型半导体装置的芯片焊盘部12的背面以及引线部13的外部引线部的引线底面部19a进行接合。因为镀层17表面具有焊料18易润湿的性质，以覆盖引线底面部19a、引线上侧端部19b和引线外侧面部19c的方式形成焊料填角，所以能够改善安装强度，提高安装可靠性。为了比较，在图13中示出不具有切口部的现有的树脂密封型半导体装置的基板安装的情况。该示例为引线部13从密封树脂16大量突出的结构。与之相对，在图6所示的树脂密封型半导体装置的情况下，从密封树脂16的外形（端面）突出的引线部13极小，为也贡献于树脂密封型半导体装置的小型化的结构。此外，极小的引线突出在从树脂密封型半导体装置的上面进行外观检查时也是有效的特征。
以上以内部引线部以比外部引线部高的方式进行折弯的引线部为例进行了说明。但是引线扁平类型的树脂密封型半导体装置也能够采用同样的结构。
接着关于本实施方式的树脂密封型半导体装置的制造方法进行说明。
首先，如图2（a）所示，将框架内搭载半导体元件的矩形状的芯片焊盘部12和在该芯片焊盘部12中对置配置前端部的多个引线部13作为一个单元，准备具有多个该单元的铜材料构成的引线框架。引线框架的底面侧贴有密封片15，该密封片15以密封树脂不能迂回到引线部13的底面的方式提供保护，是用于使引线部13的底面露出的功能部件。
图2（b）是沿图2（a）所示的C-C切断线的截面图。密封片15上粘接芯片焊盘部12的背面与引线部13的外部引线部的引线底面部，内部引线部以比外部引线部高的方式进行折弯，不粘接到密封片15。
图2（c）是示出在外部引线部的上表面选择性地贴上水溶性带23的状态的图。这里使用截面为矩形的水溶性带23。也可以用保护层（resist）或者涂层（coating）材料代替水溶性带。水溶性带23跨过图1中虚线所示的密封树脂16的整个宽度而设置。
如图2（d）所示，引线框架的各单元的芯片焊盘部12上通过银焊膏（paste）等的粘接剂（未图示），分别对半导体元件11进行芯片焊接，之后，如图3（e）所示，通过引线接合（wire bonding）法，将半导体元件11上的电极焊盘（未图示）和引线部13的内部引线部通过金属细线14进行电连接。
接着如图3（f）所示，通过传递模塑（transfer mold）法，利用环氧类树脂构成的密封树脂16，密封作为引线框架的外围的芯片焊盘部12、半导体元件11、引线部13的内部引线部和外部引线部的一部分以及金属细线14，并且去除紧贴引线框架的芯片焊盘部12以及引线部13的底面的密封片15。该状态下，芯片焊盘部12以及引线部13从密封树脂16露出。
接着如图3（g）所示，通过水处理使水溶性带23溶解而形成空洞部24。因为使用了截面为矩形的水溶性带23，所以空洞部24的截面也为矩形。使用保护层代替水溶性带的情况下，能够通过用异丙醇等溶剂进行处理来使保护层溶解而形成空洞部24。涂层材料的情况下也能够通过使用溶解其的溶剂来形成空洞部24。
接着如图3（h）所示，在芯片焊盘部12的背面和引线部13的外部引线部的引线底面部，以及在空洞部24中露出的外部引线部的上表面形成镀层17。这里，通过电解镀法来形成100%锡组成的镀层。镀层17的形成除了通过电解镀法的方法，也可以使用无电解镀。
接着如图3（i）所示，若从外部引线部的引线底面部一侧使用冲孔模具（金型パンチ）冲孔切断引线部13的外部引线部，则如图4（j）所示，该切断线成为到达空洞部24的窄槽。
接着如图4（k）所示，从与冲孔切断为相反侧的密封树脂16一侧（图中为下侧）通过旋转刀进行切割，形成到达空洞部24的槽。这时的槽宽优选为比冲孔切断形成的窄槽更宽，而比空洞部24的宽度更窄。
由此，各个进行分离而成为图5所示的树脂密封型半导体装置。这时，空洞部24被分割而成为密封树脂16的侧面的所设的切口部22。然后，如从通过冲孔切断形成的槽的槽宽和通过旋转刀形成的槽的槽宽所能够理解地，引线部13的前端的引线外侧面部19c比密封树脂的侧面稍微突出。
以上，虽然说明了旋转刀情况下的切断宽度比冲孔切断情况下的切断宽度更宽的情况的实施例，但是也可以是从外部引线部一侧的切断与从密封树脂一侧的切断为相同的宽度、这些切断宽度比空洞部的宽度更窄。该情况下，引线外侧面部与密封树脂的侧面为同一面。为了实现该情况，从外部引线部一侧的切断和从密封树脂一侧的切断的两者也可以都使用冲孔切断的方法，两者也还可以都使用旋转刀切断的方法。
以上说明中，关于使用截面是矩形的水溶性带23的实施例进行说明，因此空洞部24的截面也为矩形，切口部22为“コ”字型。如上所述，也可以使用保护层、涂层材料来代替水溶性带23，这样的情况下，选择性地配置的保护层、涂层材料的截面不一定是矩形，也可以是圆或者椭圆切断为一半那样的形状。由此，空洞部24的截面也为圆或者椭圆切断为一半那样的形状，空洞部24为进一步等分这些的、圆或者椭圆切断为四分之一那样的形状。
以上，在本发明的树脂密封型半导体装置及其制造方法中，树脂密封型半导体装置在将半导体装置通过焊料18接合到印刷基板等的安装基板20的凸台部21时，因为引线部13中所设的引线上侧端部19b具有镀层17，所以引线部13的侧面部分中形成焊料填角，能够改善安装强度，提高安装可靠性。此外，在基板安装时，通过在引线端面部形成形状良好的焊料填角，而能够改善安装后的接合部外观检查时的识别精度，防止识别不良。
附图标记
11 半导体元件；12 芯片焊盘部；13 引线部；14 金属细线；15 密封片；16 密封树脂；17 镀层；18 焊料；19a 引线底面部；19b 引线上侧端部；19c 引线外侧面部；20 安装基板；21 凸台部；22 切口部；23 水溶性带；24 空洞部；25 薄壁部。

Claims (13)

1. 一种树脂密封型半导体装置，其特征在于包括：
芯片焊盘部；
所述芯片焊盘部上搭载的半导体元件；
在所述芯片焊盘部的至少两边中对置配置的多个引线部；
连接所述半导体元件的表面中所设的多个电极与所述多个引线部的金属细线；以及
以使所述多个引线部部分地露出的方式密封所述芯片焊盘部、所述半导体元件以及所述多个引线部的密封树脂，
所述多个引线部具备从所述密封树脂露出的作为底面的引线底面部、作为前端的引线外侧面部和作为上表面的一部分的引线上侧端部，
所述引线底面部与所述密封树脂的底面在同一面内，
所述引线底面部以及所述引线上侧端部具有镀层，
所述引线上侧端部的铅垂上方所述密封树脂隔着不具有所述密封树脂的切口部而存在。
2. 根据权利要求1所述的树脂密封型半导体装置，其特征在于：
所述切口部的截面为“コ”字型。
3. 根据权利要求1所述的树脂密封型半导体装置，其特征在于：
所述芯片焊盘部的底面部从所述密封树脂露出。
4. 根据权利要求1所述的树脂密封型半导体装置，其特征在于：
所述引线外侧面部比所述密封树脂的侧面更加向外侧突出。
5. 根据权利要求1所述的树脂密封型半导体装置，其特征在于：
所述引线外侧面部与所述密封树脂的侧面为同一面。
6. 根据权利要求1所述的树脂密封型半导体装置，其特征在于：
所述引线底面部的镀层以及所述引线上侧端部的镀层为由从铅、铋、锡、铜、银、钯以及金中选择的一种金属构成的金属层或者由两种以上的金属的合金构成的合金层。
7. 根据权利要求1所述的树脂密封型半导体装置，其特征在于：
所述多个引线部分别由内部引线部和外部引线部构成，所述内部引线部以比所述外部引线部高的方式进行折弯。
8. 一种树脂密封型半导体装置的制造方法，其特征在于包括：
将芯片焊盘部以及在所述芯片焊盘部对置配置的多个引线部作为一个单元，准备具有多个该单元的框架或者电铸基板的工序；
在所述框架或者电铸基板的第一面贴上密封片的工序；
在所述多个引线部的与所述第一面相反侧的第二面形成可溶性膜的工序；
在所述框架或者电铸基板的所述芯片焊盘部各自搭载半导体元件，通过金属细线将所述多个引线部与所述半导体元件表面的电极连接的工序；
以使所述多个引线部的引线底面部露出的方式通过密封树脂来树脂密封所述芯片焊盘部、所述半导体元件和所述多个引线部的工序；
溶解去除所述可溶性膜，在所述密封树脂中形成空洞部的工序；
将所述框架或者电铸基板浸入镀液以在所述引线底面部和引线上侧端部形成镀层的工序；
从所述第一面一侧对所述多个引线部施行第一切断，形成到达所述空洞部的第一槽的工序；以及
从与所述第一面相反侧的第二面一侧对所述密封树脂施行第二切断，从所述框架或者电铸基板分离树脂密封型半导体装置的工序。
9. 根据权利要求8所述的树脂密封型半导体装置的制造方法，其特征在于：
所述第一切断是冲孔切断，所述第二切断是旋转刀切断。
10. 根据权利要求8所述的树脂密封型半导体装置的制造方法，其特征在于：
所述第一切断是冲孔切断，所述第二切断也是冲孔切断。
11. 根据权利要求8所述的树脂密封型半导体装置的制造方法，其特征在于：
所述第一切断是旋转刀切断，所述第二切断是冲孔切断。
12. 根据权利要求8所述的树脂密封型半导体装置的制造方法，其特征在于：
所述第二切断的切断宽度比所述第一切断的切断宽度宽，比所述空洞部的宽度窄。
13. 根据权利要求8所述的树脂密封型半导体装置的制造方法，其特征在于：
所述第二切断的切断宽度与所述第一切断的切断宽度相同，比所述空洞部的宽度窄。
CN201410048433.4A 2013-02-12 2014-02-12 树脂密封型半导体装置及其制造方法 Expired - Fee Related CN103985690B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013024972A JP6030970B2 (ja) 2013-02-12 2013-02-12 樹脂封止型半導体装置およびその製造方法
JP2013-024972 2013-02-12

Publications (2)

Publication Number Publication Date
CN103985690A true CN103985690A (zh) 2014-08-13
CN103985690B CN103985690B (zh) 2018-09-25

Family

ID=51277603

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410048433.4A Expired - Fee Related CN103985690B (zh) 2013-02-12 2014-02-12 树脂密封型半导体装置及其制造方法

Country Status (5)

Country Link
US (2) US9275972B2 (zh)
JP (1) JP6030970B2 (zh)
KR (1) KR102082941B1 (zh)
CN (1) CN103985690B (zh)
TW (1) TWI591775B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107154362A (zh) * 2016-03-03 2017-09-12 英飞凌科技股份有限公司 制造具有光学检测特征的模制的半导体封装体的方法
CN107534027A (zh) * 2015-06-15 2018-01-02 索尼公司 半导体装置、电子设备和制造方法
CN109427960A (zh) * 2017-09-04 2019-03-05 罗姆股份有限公司 半导体器件
CN110709970A (zh) * 2017-05-30 2020-01-17 青井电子株式会社 半导体装置及半导体装置的制造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITTO20120854A1 (it) * 2012-09-28 2014-03-29 Stmicroelectronics Malta Ltd Contenitore a montaggio superficiale perfezionato per un dispositivo integrato a semiconduttori, relativo assemblaggio e procedimento di fabbricazione
JP2017079215A (ja) * 2014-02-27 2017-04-27 パナソニックＩｐマネジメント株式会社 樹脂封止型半導体装置、およびその製造方法、ならびにその実装体
JP2015176907A (ja) * 2014-03-13 2015-10-05 ルネサスエレクトロニクス株式会社 半導体装置
CN205282448U (zh) * 2015-05-28 2016-06-01 意法半导体股份有限公司 表面安装类型半导体器件
US20170047271A1 (en) * 2015-08-10 2017-02-16 Freescale Semiconductor, Inc. Method for making a semiconductor device having an interposer
JP6840466B2 (ja) * 2016-03-08 2021-03-10 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
DE112016006677B4 (de) 2016-03-29 2021-12-16 Mitsubishi Electric Corporation Verfahren zum Herstellen einer mit Harz versiegelten Leistungs-Halbleitervorrichtung
US10388616B2 (en) * 2016-05-02 2019-08-20 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
JP6851239B2 (ja) 2017-03-29 2021-03-31 エイブリック株式会社 樹脂封止型半導体装置およびその製造方法
US11444048B2 (en) * 2017-10-05 2022-09-13 Texas Instruments Incorporated Shaped interconnect bumps in semiconductor devices
DE102019120886A1 (de) * 2019-08-02 2021-02-04 Infineon Technologies Ag Halbleitergehäuse mit einem Hohlraum in seinem Gehäusekörper
WO2021074978A1 (ja) * 2019-10-15 2021-04-22 三菱電機株式会社 半導体装置
CN113035721A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 用于侧壁镀覆导电膜的封装工艺
EP4340020A1 (en) * 2022-09-16 2024-03-20 Nexperia B.V. A method for manufacturing a semiconductor package assembly as well as a semiconductor package assembly obtained with this method

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020038714A1 (en) * 1998-06-24 2002-04-04 Glenn Thomas P. Method of making an integrated circuit package
CN1381886A (zh) * 2001-04-13 2002-11-27 雅马哈株式会社 半导体器件和封装及其制造方法
US20060192294A1 (en) * 2004-11-15 2006-08-31 Chippac, Inc Chip scale package having flip chip interconnect on die paddle
CN101273452A (zh) * 2005-09-06 2008-09-24 宇芯（毛里求斯）控股有限公司 用于半导体封装的裸片焊盘
US20080251898A1 (en) * 2002-04-01 2008-10-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US20090250807A1 (en) * 2006-11-14 2009-10-08 Infineon Technologies Ag Electronic Component and Method for its Production
TW201128758A (en) * 2010-02-12 2011-08-16 Siliconware Precision Industries Co Ltd Quad flat non leaded package structure capable of preventing electromagnetic interference and method for forming the same
CN103681577A (zh) * 2012-09-24 2014-03-26 精工电子有限公司 树脂密封型半导体装置及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0531252U (ja) * 1991-09-30 1993-04-23 テイアツク株式会社 半導体集積回路装置
JP3230348B2 (ja) * 1993-09-06 2001-11-19 ソニー株式会社 樹脂封止型半導体装置及びその製造方法
KR970008530A (ko) * 1995-07-07 1997-02-24 김광호 표면 실장용 리드프레임 및 그를 이용한 반도체 패키지와 그 제조방법
JP3405202B2 (ja) * 1998-06-26 2003-05-12 松下電器産業株式会社 リードフレームおよびそれを用いた樹脂封止型半導体装置およびその製造方法
JP4387566B2 (ja) * 2000-07-05 2009-12-16 パナソニック株式会社 樹脂封止型半導体装置
US6281047B1 (en) * 2000-11-10 2001-08-28 Siliconware Precision Industries, Co., Ltd. Method of singulating a batch of integrated circuit package units constructed on a single matrix base
JP3915794B2 (ja) * 2003-04-02 2007-05-16 ヤマハ株式会社 半導体パッケージ、その製造方法、および、これに使用するリードフレーム
JP2005203469A (ja) * 2004-01-14 2005-07-28 Sony Corp 半導体パッケージ
US20050248259A1 (en) * 2004-05-10 2005-11-10 Roger Chang Bent lead light emitting diode device having a heat dispersing capability
JP4418764B2 (ja) * 2005-02-24 2010-02-24 三菱電機株式会社 樹脂封止型半導体パッケージの製造方法
JP2008098478A (ja) * 2006-10-13 2008-04-24 Renesas Technology Corp 半導体装置及びその製造方法
WO2010036051A2 (en) * 2008-09-25 2010-04-01 Lg Innotek Co., Ltd. Structure and manufacture method for multi-row lead frame and semiconductor package

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020038714A1 (en) * 1998-06-24 2002-04-04 Glenn Thomas P. Method of making an integrated circuit package
CN1381886A (zh) * 2001-04-13 2002-11-27 雅马哈株式会社 半导体器件和封装及其制造方法
US20080251898A1 (en) * 2002-04-01 2008-10-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US20060192294A1 (en) * 2004-11-15 2006-08-31 Chippac, Inc Chip scale package having flip chip interconnect on die paddle
CN101273452A (zh) * 2005-09-06 2008-09-24 宇芯（毛里求斯）控股有限公司 用于半导体封装的裸片焊盘
US20090250807A1 (en) * 2006-11-14 2009-10-08 Infineon Technologies Ag Electronic Component and Method for its Production
TW201128758A (en) * 2010-02-12 2011-08-16 Siliconware Precision Industries Co Ltd Quad flat non leaded package structure capable of preventing electromagnetic interference and method for forming the same
CN103681577A (zh) * 2012-09-24 2014-03-26 精工电子有限公司 树脂密封型半导体装置及其制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107534027A (zh) * 2015-06-15 2018-01-02 索尼公司 半导体装置、电子设备和制造方法
CN107534027B (zh) * 2015-06-15 2021-08-17 索尼公司 半导体装置、电子设备和制造方法
CN107154362A (zh) * 2016-03-03 2017-09-12 英飞凌科技股份有限公司 制造具有光学检测特征的模制的半导体封装体的方法
CN107154362B (zh) * 2016-03-03 2020-05-19 英飞凌科技股份有限公司 制造具有光学检测特征的模制的半导体封装体的方法
CN110709970A (zh) * 2017-05-30 2020-01-17 青井电子株式会社 半导体装置及半导体装置的制造方法
CN109427960A (zh) * 2017-09-04 2019-03-05 罗姆股份有限公司 半导体器件

Also Published As

Publication number Publication date
US20160086826A1 (en) 2016-03-24
KR20140101686A (ko) 2014-08-20
TWI591775B (zh) 2017-07-11
US9431273B2 (en) 2016-08-30
JP2014154785A (ja) 2014-08-25
US9275972B2 (en) 2016-03-01
US20140225239A1 (en) 2014-08-14
TW201448127A (zh) 2014-12-16
CN103985690B (zh) 2018-09-25
JP6030970B2 (ja) 2016-11-24
KR102082941B1 (ko) 2020-02-28

Similar Documents

Publication Publication Date Title
CN103985690A (zh) 树脂密封型半导体装置及其制造方法
US9136247B2 (en) Resin-encapsulated semiconductor device and method of manufacturing the same
US6720207B2 (en) Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
US7042068B2 (en) Leadframe and semiconductor package made using the leadframe
CN107170716B (zh) 半导体封装件及半导体封装件的制造方法
EP1237187A2 (en) Resin-encapsulated semiconductor device and method for manufacturing the same
US20110057298A1 (en) Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging
US11342252B2 (en) Leadframe leads having fully plated end faces
CN106449421B (zh) 引线框、半导体装置以及引线框的制造方法
US9363901B2 (en) Making a plurality of integrated circuit packages
US8076181B1 (en) Lead plating technique for singulated IC packages
CN104854695A (zh) 具有印刷形成的端子焊盘的引线载体
JP2003174131A (ja) 樹脂封止型半導体装置及びその製造方法
JP4651218B2 (ja) 半導体装置の製造方法
JP2017038051A (ja) 半導体パッケージ及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20160304

Address after: Chiba County, Japan

Applicant after: DynaFine Semiconductor Co.,Ltd.

Address before: Chiba, Chiba, Japan

Applicant before: Seiko Instruments Inc.

CB02 Change of applicant information
CB02 Change of applicant information

Address after: Chiba County, Japan

Applicant after: ABLIC Inc.

Address before: Chiba County, Japan

Applicant before: DynaFine Semiconductor Co.,Ltd.

GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180925