CN107154362B - 制造具有光学检测特征的模制的半导体封装体的方法 - Google Patents

制造具有光学检测特征的模制的半导体封装体的方法 Download PDF

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CN107154362B
CN107154362B CN201710116951.9A CN201710116951A CN107154362B CN 107154362 B CN107154362 B CN 107154362B CN 201710116951 A CN201710116951 A CN 201710116951A CN 107154362 B CN107154362 B CN 107154362B
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semiconductor package
molding compound
molded semiconductor
molded
metal pad
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CN107154362A (zh
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H·H·张
S·L·吴
S·K·李
F·M·卢姆
M·穆罕默特萨努西
M·C·吴
A·索里亚诺
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Infineon Technologies AG
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Abstract

一种模制的半导体封装体包括：模制化合物，其具有第一主表面、与所述第一主表面相反的第二主表面以及在所述第一与第二主表面之间延伸的边缘。半导体芯片嵌入在所述模制化合物中。多个金属焊垫也嵌入在所述模制化合物中并电连接至所述半导体芯片。所述金属焊垫具有在所述模制化合物的所述第二主表面处未被所述模制化合物覆盖的底面。设置在所述模制的封装体的周边的所述金属焊垫具有在所述模制化合物的所述边缘处未被所述模制化合物覆盖的侧面。所述金属焊垫的未被所述模制化合物覆盖的所述面被镀覆。设置在所述模制的封装体的周边的每个金属焊垫的所述侧面从所述模制化合物的所述边缘向内凹进。还对一种相应的制造方法进行了描述。

Description

制造具有光学检测特征的模制的半导体封装体的方法
技术领域
本申请涉及模制的半导体封装体，更特别地涉及具有光学检测特征的模制的半导体封装体。
背景技术
许多类型的模制的半导体封装体在模制的封装体的边缘处具有所谓的LTI(leadtip inspection：引线末端检测)特征，以允许对模制的封装体的金属焊垫之间的接合部或结合部进行光学检测，并且所述模制的半导体封装体具有诸如电路板的衬底，模制的封装体附接至所述衬底。所述LTI特征是模制的封装体的外围处的金属焊垫的一部分，所述部分延伸至模制的封装体的边缘并且未被模制化合物覆盖，因而允许从侧面进行光学检测。
单个的模制的封装体通常由模制的衬底形成，所述模制的衬底包括多个半导体芯片以及电连接至所述芯片的金属焊垫。所述半导体芯片和所述金属焊垫嵌入在模制化合物中。金属焊垫在模制化合物的底部表面处露出。相邻的封装体的金属焊垫连接。这些连接通过机械锯切工艺切断。每个切割的金属焊垫的暴露部分在单个的模制的封装体的侧面形成LTI特征，所述侧面由于封装体单个化工艺而未被模制化合物覆盖。
然而，通常使用两步锯切工艺来实现LTI特征。此外，由于两步锯切工艺，金属毛刺经常存在于LTI特征上。在锯切期间会弄脏焊盘的金属材料。在这两种情况下，由于被降级的LTI特征，因而降低了成功的光学检测的可能性。替代地，可通过使用非电解镀覆的选择性蚀刻工艺来实现LTI特征。然而，选择性蚀刻限于引线框架供应商并且需要合适的各向异性的铜蚀刻剂。
鉴于此，需要一种更简单且更具成本效益的技术来制造具有光学检测特征的模制的半导体封装体。
发明内容
根据一种制造模制的半导体封装体的方法的一个实施例，所述方法包括：提供包括模制化合物的模制的半导体衬底，半导体芯片和金属焊垫嵌入在所述模制化合物中，每个金属焊垫电连接至所述半导体芯片中的相应的一个并且在所述模制化合物的第一主表面处未被所述模制化合物覆盖；将所述模制的半导体衬底单个化成单个的模制的封装体，所述单个的模制的封装体中的每个均包括一个或一个以上的半导体芯片以及相应的金属焊垫，每个金属焊垫均具有在所述第一主表面处未被模制化合物覆盖的底面，设置在每个模制的封装体的周边的金属焊垫还具有在单个化所述模制的封装体所沿的边缘处未被所述模制化合物覆盖的侧面；将所述模制的封装体浸渍于化学浴中，所述化学浴使每个金属焊垫的所述底面变粗糙并从设置在每个模制的封装体的周边的所述金属焊垫的所述侧面去除毛刺；以及在将所述模制的封装体浸渍于所述化学浴中之后，对所述金属焊垫的未被所述模制化合物覆盖的面进行镀覆。
根据一种模制的半导体封装体的一个实施例，所述模制的半导体封装体包括：模制化合物，所述模制化合物具有第一主表面、与所述第一主表面相反的第二主表面以及在所述第一主表面与所述第二主表面之间延伸的边缘；嵌入在所述模制化合物中的半导体芯片；以及嵌入在所述模制化合物中并电连接至所述半导体芯片的多个金属焊垫。所述金属焊垫具有在所述模制化合物的所述第二主表面处未被所述模制化合物覆盖的底面。设置在所述模制的封装体的周边的所述金属焊垫具有在所述模制化合物的所述边缘处未被所述模制化合物覆盖的侧面。所述金属焊垫的未被所述模制化合物覆盖的所述面被镀覆。设置在所述模制的封装体的周边的每个金属焊垫的所述侧面从所述模制化合物的所述边缘向内凹进。
本领域技术人员在阅读下文的详细描述并在查看附图时，将认识到附加的特征和优点。
附图说明
附图中的元件不一定相对彼此按比例绘制。相似的附图标记表示相应的类似部分。除非各种示出的实施例的特征彼此排斥，否则它们可结合起来。附图中示出各实施例并在下文中对其进行详细描述。
图1示出制造具有光学检测特征的模制的半导体封装体的一种方法的一个实施例的流程图。
图2和图3示出图1中所示的制造工艺的不同阶段期间模制的半导体衬底的相应的自上而下的俯视图。
图4示出图1中所示的方法中的粗糙化/去毛刺和镀覆工艺的更加详细的流程图。
图5示出具有用于实现图4中所示的粗糙化/去毛刺和镀覆工艺的分离的隔室或浸渍槽的多级工具的一个实施例。
图6示出根据依照图1至图5描述的方法制造的模制的半导体封装体的底部透视图。
图7示出焊接至电路板的图6中的模制的半导体封装体的侧透视图。
图8示出根据依照图1至图5描述的方法制造的并具有倒装芯片配置的模制的半导体封装体的剖视图。
图9示出根据依照图1至图5描述的方法制造的并具有焊线配置的模制的半导体封装体的剖视图。
具体实施方式
根据本文描述的实施例，诸如QFN(四面扁平无引线：quad-flat no-leads)、DFN(两面扁平无引线：dual-flat no-leads)、TSNP(薄型无引线封装：Thin Small Non LeadedPackage)等无引线模制的半导体封装体由模制的衬底制造，并且具有在单个的模制的封装体的边缘处的本文中也被称为引线末端检测(LTI)特征的光学检测特征。无引线半导体封装技术，也通常被称为MLP(微引线框架：micro leadframe)和SON(小外形无引线：small-outline no leads)，是一种用于将集成电路(IC：integrated circuit)连接至印刷电路板(PCB：printed circuit board)的表面而没有通孔连接的表面安装技术。本文所述的无引线半导体封装体是通过使用单步锯切工艺将模制的半导体衬底单个化成单个的模制的封装体，然后镀覆所述LTI特征来制造的。这样，在单个化之后单个的封装体的金属焊垫的暴露表面可被粗糙化，并且LTI特征被镀覆。
图1示出由模制的半导体衬底200制造模制的半导体封装体的方法100的一个实施例。所述方法100参照图2和图3进行描述，所述图2和图3示出在制造工艺的不同阶段期间的多个模制的半导体衬底200。
方法100包括提供模制的半导体衬底200(方框102)，每个所述模制的半导体衬底200均包括模制化合物202，半导体芯片(视线之外)和金属焊垫204嵌入所述模制化合物202中。每个金属焊垫204电连接至半导体芯片中的相应的一个并且在模制化合物202的底部表面处未被模制化合物202覆盖，所述模制化合物202的底部表面是模制化合物202的在图2和图3的分解图中可见的表面。可使用用于制造模制的半导体衬底200的任何标准工艺。例如，金属焊垫204可通过引线框架条的引线来实现。在焊线配置的情况下，半导体芯片可附接至引线框架条的芯片焊盘。在倒装芯片配置的情况下，半导体芯片的端子可例如通过金属柱连接至芯片之下的金属焊垫204。在任一芯片配置中，芯片和金属焊垫204都嵌入在模制化合物202中。在制造模制的衬底200期间，金属焊垫204的底部表面接触衬底，因而在模制化合物202的底部主表面处未被模制化合物202覆盖。
可将一个以上的模制的半导体衬底200暂时地固定至诸如衬底的载体206或UV可固化带208(方框104)。在UV可固化带208的情况下，UV可固化带208具有耐热性和耐化学性，使得UV可固化带208可承受化学浴。UV可固化带208可包括基膜、基膜上的粘附剂和粘附剂上的衬垫。在一个实施例中，所述基膜包括聚烯烃，所述粘附剂包括丙烯酸，以及所述衬垫包括聚对苯二甲酸乙二醇酯。
将由每个模制的半导体衬底200形成的单个的模制的半导体封装体210由图2中的虚线框示出，因为在制造工艺中此时它们还没有被单个化，即还没有例如通过锯切而被分离成单个的封装体。图2和图3中的分解图示出单个化之前(图2)和单个化之后(图3)的单个的模制的封装体210中的一个。
然后沿锯切道212将模制的半导体衬底200单个化成单个的模制的封装体210(方框106)。本文所使用的术语“单个化”通常指代将联合的单元分离成单个的模制的封装体210的行为或工艺。在一个实施例中，使用单步锯切工艺来单个化模制的半导体衬底200，在所述单步锯切工艺中，锯片仅一次沿每个锯切道212切断模制化合物202。这样，避免了两步锯切工艺，在所述两步锯切工艺中，模制化合物被部分地切割，执行诸如化学蚀刻的进一步处理，然后沿相同锯切道对模制化合物进行第二次切割以完成单个的模制的封装体的单个化。避免这种两步锯切工艺降低了单个的模制的封装体的总成本。模制的半导体衬底200由图3中的虚线框示出，因为在工艺中此时它们已经被单个化，因而被分离成单个的模制的封装体210。
每个单个的模制的半导体封装体210均包括一个或一个以上的半导体芯片(未示出)，以及电连接至各个芯片的相应的金属焊垫204。如图2和图3的分解图中示出的，每个金属焊垫204均具有在模制化合物202的底部表面处未被模制化合物202覆盖的底面。设置在每个模制的封装体210的周边的金属焊垫204还具有在边缘216处(沿所述边缘模制的封装体210被单个化)未被模制化合物202覆盖的侧面214。设置在每个模制的封装体210的周边的金属焊垫204的未被覆盖的侧面214形成了LTI特征，其通过作为单步锯切工艺的一部分的沿锯切道212切断连接的金属焊垫204而实现。
如图3中示出的，在单个化之后，载体206仍然保持着单个的模制的半导体封装体210。然后将暂时附接有单个的模制的半导体封装体210的载体206浸渍于化学浴中(方框108)。所述化学浴使每个金属焊垫204的底面和设置在每个模制的封装体210的周边的金属焊垫204的侧面214变粗糙。通过使金属焊垫204的未被模制化合物202覆盖的面变粗糙，增加了用于镀覆的表面面积，这确保了镀覆更有可能附接/粘合至金属焊垫204的暴露的面。设置在每个模制的封装体210的周边的金属焊垫204的侧面214有可能具有毛刺，即通过锯片的作用留下的粗糙边缘或脊状物。化学浴从设置在每个模制的封装体210的周边的金属焊垫204的侧面214去除毛刺。金属焊垫204的未被模制化合物202覆盖的面在化学浴中的浸渍之后被镀覆(方框110)。模制的半导体封装体210可经受诸如自动检测、测试、载体去除、带粘贴等等的后镀覆工艺(方框112)。
图4更详细地示出包括在图1的方法100中的粗糙化/去毛刺和镀覆工艺108、110的一个实施例。参考图5描述图4，图5一般性地示出具有用于实现图4中所示的粗糙化/去毛刺和镀覆工艺108、110的分离的隔室或浸渍池402-414的多级工具400。
在单个化之后且在化学浴中浸渍之前，模制的半导体封装体210通过清洁溶液进行清洁(方框400)。这可包括将附接有模制的半导体封装体210的载体206浸渍于图5中示出的多级工具400的第一隔室/浸渍池402中，所述第一隔室/浸渍池402由诸如像浓度为例如10％的HCI的酸性溶液的清洁溶液填充。
接下来，附接有模制的半导体封装体210的载体206被转移至图5中示出的多级工具400的第二隔室/浸渍池404，所述第二隔室/浸渍池404具有用于冲洗模制的封装体210一次或一次以上的喷嘴，以便去除清洁过程中的清洁溶液和残留物(方框402)。
然后将附接有模制的半导体封装体210的载体206转移至图5中示出的多级工具400的第三隔室/浸渍池406(方框404)。第三隔室/浸渍池406填充有化学浴，该化学浴使每个金属焊垫204的底面变粗糙并从设置在每个模制的封装体210的周边的金属焊垫204的侧面214去除毛刺。当将模制的封装体210浸渍于化学浴中时，从金属焊垫204的未被模制化合物202覆盖的面蚀掉约3至15微米的金属。在一个实施例中，化学浴包括过硫酸钠，其是过硫酸盐的钠盐，也被称为过二硫酸盐。更一般地，化学浴可选自以下组：过氧化氢溶液；氯化铁溶液；盐溶液；硫酸铜；和硫酸铁。
然后将附接有模制的半导体封装体210的载体206转移回图5中示出的多级工具400的第二隔室/浸渍池404，用于实施一个或一个以上的冲洗循环以去除粗糙化/去毛刺工艺中的化学浴溶液和残留物(方框406)。然后通过非电解镀覆来镀覆金属焊垫204的未被模制化合物202覆盖的面。
在一个实施例中，非电解镀覆工艺是非电解镀镍浸金(ENIG：electroless nickelimmersion gold)工艺，在该工艺中，将镍-磷或镍-硼合金层沉积在金属焊垫204的未被模制化合物202覆盖的面上，然后用金层覆盖。所述ENIG工艺可包括将附接有模制的半导体封装体210的载体206转移至图5中示出的多级工具400的第四隔室/浸渍池408(方框408)。将用于非电解镀覆的催化剂引入第四隔室/浸渍池408中。例如，在金属焊垫204包括铜的情况下，所述催化剂可包括钯。这样，金属焊垫204的未被模制化合物202覆盖的面可在镀覆工艺之前具有钯催化的铜表面。可镀覆附加的非电解镀覆钯层用于磁敏产品。
再一次将附接有模制的半导体封装体210的载体206转移回图5中示出的多级工具400的第二隔室/浸渍池404，用于实施一个或一个以上的冲洗循环以去除钯表面活化工艺中的失活的钯和残留物(方框410)。
然后将附接有模制的半导体封装体210的载体206转移至图5中示出的多级工具400的第五隔室/浸渍池410。作为在第五隔室/浸渍池410中进行的非电解镀镍工艺的一部分，在金属焊垫204的未被模制化合物202覆盖的面上沉积镍-磷或镍-硼合金层。
将附接有模制的半导体封装体210的载体206转移回图5中示出的多级工具400的第二隔室/浸渍池404，用于实施一个或一个以上的冲洗循环以去除非电解镀镍沉积工艺中的残留物(方框414)。
然后将附接有模制的半导体封装体210的载体206转移至图5中示出的多级工具400的第六隔室/浸渍池412(方框416)。将模制的封装体210浸渍于第六隔室/浸渍池412中的金溶液中，以便形成金属焊垫204的镀覆镍的面的金层。该金层保护下面的镍免受氧化。在非电解镀镍/钯浸金(ENEPIG：electroless nickel/palladium immersion gold)镀覆工艺的情况下，在非电解镀镍层与金层之间提供防止镍腐蚀的屏障。此外，可为磁敏产品增加可选的非电解镀钯层。
将附接有模制的半导体封装体210的载体206转移回图5中示出的多级工具400的第二隔室/浸渍池404，用于实施一个或一个以上的冲洗循环以去除金浸渍工艺中的残留物(方框418)。
然后将附接有模制的半导体封装体210的载体206转移至图5中示出的多级工具400的第七隔室/浸渍池414(方框420)。在第七隔室/浸渍池414中，金属焊垫204的镍-金镀覆的面被保护层覆盖。在一个实施例中，所述保护层是高温抗氧化涂层。保护层可包括诸如有机磷、有机硅烷或有机磷和有机硅烷的混合物的有机化合物。
将附接有模制的半导体封装体210的载体206转移回图5中示出的多级工具400的第二隔室/浸渍池404，用于实施一个或一个以上的冲洗循环以去除保护层涂覆工艺中的残留物(方框422)。然后载体206和模制的半导体封装210例如在烘箱中干燥(方框424)。
图6示出依照上文结合图1至图5描述的方法制造的模制的半导体封装体210的底部透视图。图7示出焊接至电路板500上的模制的半导体封装体210的侧透视图。对于设置在模制的封装体210的周边的金属焊垫204，连续镀覆表面从金属焊垫204的底面(即，邻近电路板500的面)延伸至在(切割的)模制化合物202的边缘216处未被模制化合物202覆盖的侧面214。这样，在镀覆中没有阶梯形轮廓，在模制的封装体210的所有四侧上的LTI特征中也没有阶梯形轮廓。此外，金属焊垫204的镀覆的表面可由诸如抗氧化涂层的保护层覆盖，其可包括如上所述的有机化合物。抗氧化涂层可以用作粘附促进剂，因而使得能够将模制的封装体210无焊剂焊接至电路板500。这样，可实现直接的金属焊垫至焊料连接。在图7中附接至电路板500之后，在设置在模制的封装体210的周边的金属焊垫204的侧面214处的镀覆的LTI特征是可见的。
图8示出依照上文结合图1至图5描述的方法制造的并具有倒装芯片配置的模制的半导体封装体210的剖视图。根据此实施例，模制的半导体封装体210包括模制化合物202，其具有第一主表面201、与所述第一主表面201相反的第二主表面203以及在所述第一与所述第二主表面201、203之间延伸的边缘216。一个或一个以上的半导体芯片600嵌入在模制化合物202中，同样嵌入在模制化合物202中的多个金属焊垫204与每个半导体芯片600电连接。
在倒装芯片配置中，嵌入在模制化合物202中的半导体芯片600的底侧具有用于提供至半导体芯片600的电连接的端子。可将诸如氮化硅的钝化层602施加至半导体芯片600的底侧。金属焊垫204可以是引线框架的引线。可在半导体芯片600的端子与引线框架的引线(即金属焊垫204)之间通过铜柱604来提供连接，所述铜柱604通过焊接接合部606附接至相应的引线。
金属焊垫204具有在模制化合物202的第二主表面203处未被模制化合物202覆盖的底面215。设置在模制的封装体210的周边的金属焊垫204还具有在模制化合物202的边缘216，即模制化合物202的切割面处未被模制化合物202覆盖的侧面214。在如前文结合图1至图5所描述的封装体单个化工艺之后，对金属焊垫204的未被模制化合物202覆盖的面214、215先进行粗糙化、然后利用例如镍-磷或镍-硼合金层608和金层610进行镀覆。单个化后的粗糙化/去毛刺工艺从金属焊垫204的未被模制化合物202覆盖的面214、215蚀刻掉约3至15微米的金属。这样，设置在模制的封装体210的周边的每个金属焊垫204的侧面214从模制化合物202的边缘216向内凹进值为r的量。所有金属焊垫204的底面215也都从模制化合物202的底面203向内凹进相同的量。
在一些实施例中，金属焊垫204包括铜。金属焊垫204的未被模制化合物202覆盖的面214、215可具有钯催化的铜表面，其被镀有如前文所述的镍-磷或镍-硼合金层608。金属焊垫204的镀覆的面214、215可覆盖有诸如高温抗氧化涂层的保护层612，其可包括如也在前文中描述的诸如有机磷、有机硅烷或有机磷和有机硅烷的混合物的有机化合物。在每种情况下，设置在模制的封装体210的周边的金属焊垫204的镀覆的侧面214均提供LTI特征。
图9示出依照上文结合图1至图5描述的方法制造的并具有焊线配置的模制的半导体封装体210的剖视图。根据此实施例，模制的半导体封装体210包括模制化合物202，其具有第一主表面201、与所述第一主表面201相反的第二主表面203以及在所述第一与第二主表面201、203之间延伸的边缘216。一个或一个以上的半导体芯片700嵌入在模制化合物202中，同样嵌入在模制化合物202中的多个金属焊垫204电连接至每个半导体芯片700。
在焊线配置中，嵌入在模制化合物202中的半导体芯片700的底侧例如通过焊接接合部704附接至引线框架的芯片焊盘702。半导体芯片700的底侧可在垂直器件的情况下形成芯片700的一个端子，或者在横向器件的情况下没有端子。在任一情况下，在半导体芯片700的背向芯片焊盘702顶侧处存在一个或一个以上的附加的端子706。顶侧的端子706通过焊线708连接至引线框架的引线。引线框架的引线形成模制的封装体210的金属焊垫204。在一个实施例中，如图9所示，设置在模制的封装体210的周边的每个金属焊垫204的侧面214均具有与引线框架相同的高度h。
金属焊垫204具有在模制化合物202的第二主表面203处未被模制化合物202覆盖的底面215。设置在模制的封装体210的周边的金属焊垫204还具有在模制化合物202的边缘216，即模制化合物202的切割面处未被模制化合物202覆盖的侧面214。在如前文结合图1至图5描述的封装体单个化工艺之后，对金属焊垫204的未被模制化合物202覆盖的面214、215进行粗糙化以及利用例如镍-磷或镍-硼合金层608和金层610进行镀覆。单个化后的粗糙化/去毛刺工艺从金属焊垫204的未被模制化合物202覆盖的面214、215蚀刻掉约3至15微米的金属。这样，设置在模制的封装体210的周边的每个金属焊垫204的侧面214从模制化合物202的边缘216向内凹进值为r的量。所有金属焊垫204的底面215也都从模制化合物202的底面203向内凹进相同的量。
在一些实施例中，金属焊垫204包括铜。金属焊垫204的未被模制化合物202覆盖的面214、215可具有钯催化的铜表面，其被镀有如前文所述的镍-磷或镍-硼合金层608。金属焊垫204的镀覆的面214、215可覆盖有诸如高温抗氧化涂层的保护层612，其可包括如也在前文中描述的诸如有机磷、有机硅烷或有机磷和有机硅烷的混合物的有机化合物。在每种情况下，金属焊垫204的镀覆的侧面214均提供LTI特征。
为便于描述，使用诸如“之下”，“下方”，“下”，“上方”，“上”等等的空间相对术语，来解释一个元件相对于第二元件的位置。这些术语还旨在涵盖器件的与图中所描绘的取向不同的各种取向。另外，诸如“第一”、“第二”等术语也用于描述各种元件、区域、部分等，并且也不旨在于限制的意义。通篇中，相似的术语指代相似的元件。
如本文所使用的，术语“具有”、“含有”、“包括”、“包含”等等是表示所陈述的元件或特征的存在性的开放性术语，而不排除附加的元件或特征。除非文中明确表示，否则词语“一”、“一个”和“所述”旨在包括复数以及单数。
考虑到以上范围的变化和应用，应当理解的是，本发明不受以上描述的限制，也不受附图的限制。相反，本发明仅由所附权利要求及其法律意义上的等同方案限制。

Claims (21)

1.一种模制的半导体封装体，包括：
模制化合物，所述模制化合物具有第一主表面、与所述第一主表面相反的第二主表面以及在所述第一主表面与所述第二主表面之间延伸的边缘；
嵌入在所述模制化合物中的半导体芯片；以及
嵌入在所述模制化合物中并电连接至所述半导体芯片的多个金属焊垫；
其中，所述金属焊垫具有在所述模制化合物的所述第二主表面处未被所述模制化合物覆盖的底面；
其中，设置在所述模制的半导体封装体的周边的所述金属焊垫具有在所述模制化合物的所述边缘处未被所述模制化合物覆盖的侧面；
其中，设置在所述模制的半导体封装体的周边的每个金属焊垫的整个侧面被镀覆且从所述模制化合物的所述边缘向内凹进。
2.根据权利要求1所述的模制的半导体封装体，其中，设置在所述模制的半导体封装体的周边的每个金属焊垫的整个侧面镀覆有镍-磷或镍-硼合金层和金层。
3.根据权利要求2所述的模制的半导体封装体，其中，所述金属焊垫包括铜，设置在所述模制的半导体封装体的周边的每个金属焊垫的整个侧面具有钯催化的铜表面，所述钯催化的铜表面镀覆有镍-磷或镍-硼合金层。
4.根据权利要求1所述的模制的半导体封装体，其中，设置在所述模制的半导体封装体的周边的所述金属焊垫的镀覆的侧面由保护层覆盖。
5.根据权利要求4所述的模制的半导体封装体，其中，所述保护层是抗氧化涂层。
6.根据权利要求4所述的模制的半导体封装体，其中，所述保护层包括有机磷、有机硅烷或有机磷与有机硅烷的混合物。
7.根据权利要求1所述的模制的半导体封装体，其中，设置在所述模制的半导体封装体的周边的每个金属焊垫的整个侧面从所述模制化合物的所述边缘向内凹进3至15微米。
8.根据权利要求1所述的模制的半导体封装体，其中，所述金属焊垫是引线框架的引线，且设置在所述模制的半导体封装体的周边的每个金属焊垫的所述侧面与所述引线框架具有相同的高度。
9.一种模制的半导体封装体，包括：
模制化合物，所述模制化合物具有第一主表面、与所述第一主表面相反的第二主表面以及在所述第一主表面与所述第二主表面之间延伸的边缘；
嵌入在所述模制化合物中的半导体芯片；以及
嵌入在所述模制化合物中并电连接至所述半导体芯片的多个金属焊垫；
其中，所述金属焊垫具有在所述模制化合物的所述第二主表面处未被所述模制化合物覆盖的底面；
其中，设置在所述模制的半导体封装体的周边的所述金属焊垫具有在所述模制化合物的所述边缘处未被所述模制化合物覆盖的侧面；
其中，每个金属焊垫的整个底面被镀覆且从所述模制化合物的所述第二主表面向内凹进。
10.根据权利要求9所述的模制的半导体封装体，其中，所述金属焊垫包括铜，每个金属焊垫的整个底面具有钯催化的铜表面，所述钯催化的铜表面镀覆有镍-磷或镍-硼合金层。
11.根据权利要求9所述的模制的半导体封装体，其中，每个金属焊垫的底面由保护层覆盖。
12.根据权利要求11所述的模制的半导体封装体，其中，所述保护层是抗氧化涂层。
13.根据权利要求11所述的模制的半导体封装体，其中，所述保护层包括有机磷、有机硅烷或有机磷与有机硅烷的混合物。
14.根据权利要求9所述的模制的半导体封装体，其中，所述金属焊垫是引线框架的引线，且设置在所述模制的半导体封装体的周边的每个金属焊垫的所述侧面与所述引线框架具有相同的高度。
15.一种模制的半导体封装体，包括：
模制化合物，所述模制化合物具有第一主表面、与所述第一主表面相反的第二主表面以及在所述第一主表面与所述第二主表面之间延伸的边缘；
嵌入在所述模制化合物中的半导体芯片；以及
嵌入在所述模制化合物中并电连接至所述半导体芯片的多个金属焊垫；
其中，所述金属焊垫具有在所述模制化合物的所述第二主表面处未被所述模制化合物覆盖的底面；
其中，设置在所述模制的半导体封装体的周边的所述金属焊垫具有在所述模制化合物的所述边缘处未被所述模制化合物覆盖的侧面；
其中，设置在所述模制的半导体封装体的周边的每个金属焊垫的整个侧面被镀覆且从所述模制化合物的所述边缘向内凹进；
其中，每个金属焊垫的整个底面被镀覆且从所述模制化合物的所述第二主表面向内凹进。
16.根据权利要求15所述的模制的半导体封装体，其中，所述金属焊垫的未被所述模制化合物覆盖的每个面镀覆有镍-磷或镍-硼合金层和金层。
17.根据权利要求16所述的模制的半导体封装体，其中，所述金属焊垫包括铜，所述金属焊垫的未被所述模制化合物覆盖的每个面具有钯催化的铜表面，所述钯催化的铜表面镀覆有镍-磷或镍-硼合金层。
18.根据权利要求15所述的模制的半导体封装体，其中，所述金属焊垫的每个镀覆的面由抗氧化涂层覆盖。
19.根据权利要求15所述的模制的半导体封装体，其中，所述金属焊垫的每个镀覆的面由有机磷、有机硅烷或有机磷与有机硅烷的混合物覆盖。
20.根据权利要求15所述的模制的半导体封装体，其中，设置在所述模制的半导体封装体的周边的每个金属焊垫的整个侧面从所述模制化合物的所述边缘向内凹进第一量，且每个金属焊垫的整个底面从所述模制化合物的所述第二主表面向内凹进相同的第一量。
21.根据权利要求15所述的模制的半导体封装体，其中，所述金属焊垫是引线框架的引线，且设置在所述模制的半导体封装体的周边的每个金属焊垫的所述侧面与所述引线框架具有相同的高度。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10242912B2 (en) * 2016-07-08 2019-03-26 Analog Devices, Inc. Integrated device dies and methods for singulating the same
US10083866B2 (en) * 2016-07-27 2018-09-25 Texas Instruments Incorporated Sawn leadless package having wettable flank leads
US10483239B2 (en) 2016-12-20 2019-11-19 Sandisk Semiconductor (Shanghai) Co. Ltd. Semiconductor device including dual pad wire bond interconnection
CN108206169B (zh) * 2016-12-20 2020-06-02 晟碟半导体（上海）有限公司 包含在裸芯边缘处的裸芯接合垫的半导体装置
JP2018107416A (ja) * 2016-12-28 2018-07-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
DE102017212457A1 (de) * 2017-07-20 2019-01-24 Infineon Technologies Ag Halbleitergehäuse mit Nickelplattierung und Verfahren zum Herstellen desselben
US10741466B2 (en) 2017-11-17 2020-08-11 Infineon Technologies Ag Formation of conductive connection tracks in package mold body using electroless plating
US11545418B2 (en) * 2018-10-24 2023-01-03 Texas Instruments Incorporated Thermal capacity control for relative temperature-based thermal shutdown
US11133281B2 (en) 2019-04-04 2021-09-28 Infineon Technologies Ag Chip to chip interconnect in encapsulant of molded semiconductor package
CN112018052A (zh) 2019-05-31 2020-12-01 英飞凌科技奥地利有限公司 具有可激光活化模制化合物的半导体封装
US20200395272A1 (en) 2019-06-11 2020-12-17 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing a semiconductor device
DE102019119521A1 (de) * 2019-07-18 2021-01-21 Infineon Technologies Ag Chipgehäuse und verfahren zur herstellung eines chipgehäuses
US11587800B2 (en) 2020-05-22 2023-02-21 Infineon Technologies Ag Semiconductor package with lead tip inspection feature
US11848258B2 (en) 2020-12-31 2023-12-19 Texas Instruments Incorporated Semiconductor package with nickel-silver pre-plated leadframe
US20230170226A1 (en) * 2021-11-29 2023-06-01 Infineon Technologies Ag Semiconductor package with metal posts from structured leadframe

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362089B1 (en) * 1999-04-19 2002-03-26 Motorola, Inc. Method for processing a semiconductor substrate having a copper surface disposed thereon and structure formed
CN103985690A (zh) * 2013-02-12 2014-08-13 精工电子有限公司 树脂密封型半导体装置及其制造方法
CN104685615A (zh) * 2014-03-27 2015-06-03 瑞萨电子株式会社 半导体器件的制造方法及半导体器件

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5816478A (en) 1995-06-05 1998-10-06 Motorola, Inc. Fluxless flip-chip bond and a method for making
JP2000133761A (ja) * 1998-08-20 2000-05-12 Fujitsu Ltd 半導体装置及びその製造方法
GB0001918D0 (en) 2000-01-27 2000-03-22 Marconi Caswell Ltd Flip-chip bonding arrangement
US6580170B2 (en) * 2000-06-22 2003-06-17 Texas Instruments Incorporated Semiconductor device protective overcoat with enhanced adhesion to polymeric materials
TWI246760B (en) 2004-12-22 2006-01-01 Siliconware Precision Industries Co Ltd Heat dissipating semiconductor package and fabrication method thereof
JP2008258411A (ja) 2007-04-05 2008-10-23 Rohm Co Ltd 半導体装置および半導体装置の製造方法
JP2009071156A (ja) * 2007-09-14 2009-04-02 Toshiba Corp 半導体装置及びその製造方法
US7642135B2 (en) 2007-12-17 2010-01-05 Skyworks Solutions, Inc. Thermal mechanical flip chip die bonding
US20130017652A1 (en) 2008-04-04 2013-01-17 Gem Services, Inc. Method of manufacturing a semiconductor device package with a heatsink
US8227908B2 (en) * 2008-07-07 2012-07-24 Infineon Technologies Ag Electronic device having contact elements with a specified cross section and manufacturing thereof
US8008784B2 (en) 2008-10-02 2011-08-30 Advanced Semiconductor Engineering, Inc. Package including a lead frame, a chip and a sealant
US8071427B2 (en) 2009-01-29 2011-12-06 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
KR101686199B1 (ko) 2010-03-26 2016-12-14 삼성전자주식회사 반도체 패키지 구조물
US8496159B2 (en) 2011-06-06 2013-07-30 International Business Machines Corporation Injection molded solder process for forming solder bumps on substrates
US8933545B2 (en) 2011-07-28 2015-01-13 Alpha & Omega Semiconductor, Inc. Double-side exposed semiconductor device
US8716066B2 (en) 2012-07-31 2014-05-06 Freescale Semiconductor, Inc. Method for plating a semiconductor package lead
US8890301B2 (en) 2012-08-01 2014-11-18 Analog Devices, Inc. Packaging and methods for packaging
CN103646938B (zh) 2013-12-05 2016-02-24 江苏长电科技股份有限公司 一次先镀后蚀金属框减法埋芯片倒装凸点结构及工艺方法
TWI666746B (zh) 2014-02-17 2019-07-21 矽品精密工業股份有限公司 覆晶式封裝基板、覆晶式封裝件及其製法
US20150262918A1 (en) 2014-03-14 2015-09-17 Texas Instruments Incorporated Structure and method of packaged semiconductor devices with bent-lead qfn leadframes
EP2980845B1 (en) 2014-08-01 2019-11-27 Nexperia B.V. A leadless semiconductor package and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362089B1 (en) * 1999-04-19 2002-03-26 Motorola, Inc. Method for processing a semiconductor substrate having a copper surface disposed thereon and structure formed
CN103985690A (zh) * 2013-02-12 2014-08-13 精工电子有限公司 树脂密封型半导体装置及其制造方法
CN104685615A (zh) * 2014-03-27 2015-06-03 瑞萨电子株式会社 半导体器件的制造方法及半导体器件

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CN107154362A (zh) 2017-09-12
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US10431560B2 (en) 2019-10-01
DE102017104430A1 (de) 2017-09-07
US20200006267A1 (en) 2020-01-02
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US9806043B2 (en) 2017-10-31
US20180033752A1 (en) 2018-02-01

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