JP7089388B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP7089388B2 JP7089388B2 JP2018063641A JP2018063641A JP7089388B2 JP 7089388 B2 JP7089388 B2 JP 7089388B2 JP 2018063641 A JP2018063641 A JP 2018063641A JP 2018063641 A JP2018063641 A JP 2018063641A JP 7089388 B2 JP7089388 B2 JP 7089388B2
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- lead
- plating layer
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- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C18/31—Coating with metals
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- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F17/00—Multi-step processes for surface treatment of metallic material involving at least one process provided for in class C23 and at least one process covered by subclass C21D or C22F or class C25
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- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Description
10 :半導体素子
10a :素子主面
10b :素子裏面
101 :ゲート電極
102 :ドレイン電極
103 :ソース電極
104 :センス電極
20 :封止樹脂
21 :樹脂主面
22 :樹脂裏面
23 :樹脂側面
231 :第1樹脂側面
232 :第2樹脂側面
30 :リードフレーム
30a :リード主面
30b :リード裏面
30c :リード端面
391 :素子ボンディング部
392,393,394:ワイヤボンディング部
31 :第1リード
31a :第1リード主面
31b :第1リード裏面
31c :第1リード端面
311 :第1ボンディングパッド部
312 :第1端子部
32 :第2リード
32a :第2リード主面
32b :第2リード裏面
32c :第2リード端面
321 :第2ボンディングパッド部
322 :延出部
33 :第3リード
33a :第3リード主面
33b :第3リード裏面
33c :第3リード端面
331 :第3ボンディングパッド部
332 :第3端子部
34 :第4リード
34a :第4リード主面
34b :第4リード裏面
34c :第4リード端面
341 :第4ボンディングパッド部
342 :第4端子部
35 :リード
41 :第1ワイヤ
42 :第2ワイヤ
43 :第3ワイヤ
50 :導電性接合材
61 :第1めっき層
62 :第2めっき層
63 :第3めっき層
64 :内部めっき層
70 :保護テープ
Claims (16)
- 半導体素子と、
各々が厚さ方向において互いに反対側を向くリード主面およびリード裏面を有しており、前記半導体素子に導通するとともに、いずれかの前記リード主面によって前記半導体素子を支持する複数のリードと、
前記複数のリードの一部ずつおよび前記半導体素子を覆う封止樹脂と、
各々が前記封止樹脂から露出する第1めっき層および第2めっき層と、
前記第1めっき層と同じ素材であり、かつ、前記封止樹脂に覆われる内部めっき層と、
を備えており、
前記封止樹脂は、前記厚さ方向に直交する第1方向を向く樹脂側面を有し、
前記複数のリードの少なくともいずれかは、前記リード裏面に繋がり、かつ、前記樹脂側面と面一であるリード端面を有し、
前記第1めっき層は、前記リード裏面を覆っており、
前記第2めっき層は、前記リード端面を覆い、かつ、前記第1方向において前記樹脂側面よりも突き出ており、
前記第2めっき層の前記リード裏面が向く方向の端縁は、前記第1方向に見て、前記第1めっき層に重なり、
前記半導体素子は、前記リード主面と同じ方向を向き、かつ、第1電極が形成された素子主面および前記リード裏面と同じ方向を向き、かつ、第2電極が形成された素子裏面を有し
前記複数のリードは、互いに離間した第1リードおよび第2リードを含んでおり、
前記第1リードは、第1ワイヤを介して、前記第1電極に導通しており、
前記第2リードは、導電性接合材を介して、前記第2電極に導通しており、
前記内部めっき層は、前記第2リードのリード主面を覆い、前記半導体素子と前記第2リードのリード主面との間に介在しており、かつ、前記第1めっき層に繋がる、
ことを特徴とする半導体装置。 - 前記リード端面および前記樹脂側面はともに、前記第2めっき層の表面よりも粗い、
請求項1に記載の半導体装置。 - 前記第2めっき層の素材は、前記複数のリードの素材よりもはんだ濡れ性が高い、
請求項1または請求項2に記載の半導体装置。 - 前記複数のリードの前記素材は、主成分がCuである、
請求項3に記載の半導体装置。 - 前記第2めっき層は、Au層を含んでいる、
請求項4に記載の半導体装置。 - 前記第2めっき層は、さらにNi層およびPd層を含んでおり、
前記Ni層、前記Pd層および前記Au層は、互いに積層されている、
請求項5に記載の半導体装置。 - 前記第1めっき層の素材は、前記第2めっき層の素材と異なる、
請求項1ないし請求項6のいずれか一項に記載の半導体装置。 - 前記第1めっき層の前記素材は、主成分がSnである、
請求項7に記載の半導体装置。 - 前記封止樹脂は、前記リード裏面と同じ方向を向き、かつ、前記リード裏面と面一である樹脂裏面を有しており、
前記第1めっき層は、前記厚さ方向において前記樹脂裏面よりも突き出ている、
請求項8に記載の半導体装置。 - 前記封止樹脂は、前記リード裏面と同じ方向を向く樹脂裏面を有しており、
前記リード裏面は、前記厚さ方向において、前記樹脂裏面よりも、前記リード主面が向く方向側に位置し、
前記第1めっき層は、前記厚さ方向において前記樹脂裏面と面一である、
請求項1ないし請求項8のいずれか一項に記載の半導体装置。 - 前記素子主面は、前記第1電極と異なる第3電極がさらに形成されており、
前記複数のリードは、前記第1リードおよび前記第2リードから離間した第3リードをさらに含んでおり、
前記第3リードは、第2ワイヤを介して、第3電極に導通している、
請求項1ないし請求項10のいずれか一項に記載の半導体装置。 - 前記半導体素子は、MOSFETである、
請求項11に記載の半導体装置。 - 厚さ方向において互いに反対側を向く主面および裏面を有するリードフレームを用意する用意工程と、
前記リードフレームの前記主面に半導体素子を搭載する素子搭載工程と、
前記リードフレームの一部および前記半導体素子を覆う封止樹脂を形成する樹脂形成工程と、
前記リードフレームの前記裏面を覆う第1めっき層を電解めっきにより形成する電解めっき工程と、
少なくとも前記リードフレームの前記裏面および前記第1めっき層を覆う保護テープを貼り付ける工程と、
前記保護テープを貼り付けた状態で、前記リードフレームの一部と前記封止樹脂の一部を切断することで、前記封止樹脂に前記厚さ方向に直交する第1方向を向く樹脂側面を形成するとともに、前記リードフレームに前記樹脂側面から露出し、かつ前記樹脂側面と面一であるリード端面を形成する工程と、
前記保護テープを貼り付けた状態で、前記リード端面を覆う第2めっき層を無電解めっきにより形成する無電解めっき工程と、
を含み、
前記電解めっき工程は、前記素子搭載工程前に行われ、
前記電解めっき工程では、前記第1めっき層および内部めっき層を含む表層めっき層を前記用意工程後のリードフレームの表面全体に形成し、
前記素子搭載工程では、前記表層めっき層を介して、前記主面に前記半導体素子を搭載し、
前記樹脂形成工程では、前記内部めっき層を覆い、かつ、前記第1めっき層を露出させるように、前記封止樹脂を形成する、
ことを特徴とする半導体装置の製造方法。 - 前記第2めっき層の素材は、前記リードフレームの素材よりもはんだ濡れ性が高い、
請求項13に記載の半導体装置の製造方法。 - 前記リードフレームの素材は、主成分がCuであり、
前記第2めっき層は、少なくともAu層を含んでいる、
請求項14に記載の半導体装置の製造方法。 - 前記第1めっき層の素材は、主成分がSnである、
請求項13ないし請求項15のいずれか一項に記載の半導体装置の製造方法。
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