TWI421998B - Semiconductor device, lead frame and semiconductor device manufacturing method - Google Patents

Semiconductor device, lead frame and semiconductor device manufacturing method Download PDF

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TWI421998B
TWI421998B TW097106850A TW97106850A TWI421998B TW I421998 B TWI421998 B TW I421998B TW 097106850 A TW097106850 A TW 097106850A TW 97106850 A TW97106850 A TW 97106850A TW I421998 B TWI421998 B TW I421998B
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groove
wire
semiconductor device
semiconductor wafer
lead frame
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TW097106850A
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TW200845351A (en
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Yasumasa Kasuya
Motoharu Haga
Shoji Yasunaga
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Rohm Co Ltd
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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Description

半導體裝置、導線架及半導體裝置之製造方法
本發明係關於半導體裝置、導線架及半導體裝置之製造方法。
隨著電子機器之小型化，適用QFN(Quad Flat Non-leaded Package：扁平式四邊無接腳型封裝)之半導體裝置之需求日益提高。
適用QFN之半導體裝置例如係藉MAP(Molded Array Packaging：模製陣列封裝)方式製作。在MAP方式中，利用封裝樹脂將複數半導體晶片一併封裝在導線架上以後，切開分成具有1個半導體晶片之半導體裝置之個體。
導線架例如係由銅所構成。此導線架具有格子狀之支持部。在被支持部所包圍之各矩形狀區域內，形成有矩形狀之晶粒墊(die pad)、與複數導線。導線配置於晶粒墊之周圍。各導線之基端部連接於支持部，遊端部形成向晶粒墊延伸之長條形狀。
半導體晶片被晶粒接合(die bonding)在各晶粒墊上後，經由接合線連接(線接合，wire bonding)形成在各半導體晶片之端子與其周圍之導線之上面。當所有半導體晶片之線接合完成時，將導線架設置於成型模具，利用樹脂將該導線架上之所有半導體晶片一併封裝。其後，沿著設定在支持部上之切割線將切割鋸由導線架下面側置入，除去支持部及支持部上之封裝樹脂。藉此，各導線被自支持部切離 而獲得半導體裝置之個體。
在此半導體裝置中，各導線之下面露出於封裝樹脂之下面，使各導線之下面接合於安裝基板(布線基板)上之接合面(land)，藉以達成半導體裝置對安裝基板之安裝。在適用QFN之半導體裝置中，由於導線並未由封裝樹脂之側面延伸，故與適用QFP(Quad Flat Package：扁平式四邊有接腳型封裝)之半導體裝置相比，可大幅減少安裝面積。
[專利文獻1]日本特開2001-257304號公報
然而，利用切割鋸將各導線自支持部切離之際，導線材料之銅會被拉扯而延伸，而在導線之端部有可能產生向下方延伸之溢料。產生此種溢料時，溢料會抵接到安裝基板上之接合面，半導體裝置會因該溢料之部份而由安裝基板翹起，故半導體裝置會以傾斜之狀態被安裝於安裝基板。此種安裝狀態會因周圍之溫度變化而造成安裝基板之翹曲之原因，而有發生因此翹曲引起之導線與接合面之連接不良等安裝不良之虞。
因此，本發明之目的在於可防止溢料引起之安裝不良之發生之半導體裝置及導線架、以及使用該導線架之半導體裝置之製造方法。
本發明之一局面之半導體裝置係包含：半導體晶片；及 導線，其係配置於前述半導體晶片之周圍而向與前述半導體晶片之側面交叉之方向延伸，至少遠離前述半導體晶片之側之端部被接合於安裝基板。在前述導線中，在對前述安裝基板之接合面及在遠離前述半導體晶片之側之端部開放之溝係在與厚度方向正交且沿著前述端面之寬度方向之全寬中形成，在前述溝中埋設由焊料構成之埋設體。
在導線中，形成有在對安裝基板之接合面及遠離半導體晶片之側之端部(外端面)開放之溝。在此溝中，埋設由焊料構成之埋設體。因此，在自導線架切離導線之際，切斷刀(例如切割鋸)會接觸到導線之外端面及埋設體之端面。溝沿著寬度方向之全寬中形成，故即使產生因埋設體之材料之焊料被切斷刀拉扯而延伸之溢料，也不會產生因導線之材料被切斷刀拉扯而延伸之溢料。即使有焊料構成之溢料存在，該溢料也會被半導體裝置對安裝基板之安裝時之回流(reflow)所熔化，故不會有發生半導體裝置以傾斜之狀態被安裝於安裝基板之虞。故半導體裝置不會發生溢料引起之安裝不良。又，因埋設體係由焊料所構成，故可使用作為導線與安裝基板之接合劑之焊料濕潤達到埋設體之端面，可在導線之端面形成所謂焊料嵌條。因此，容易從外觀檢查導線與布線基板之接合(焊接)狀態。
本發明之另一局面之導線架係包含：晶粒墊，其係在一方側之面裝載有半導體晶片；導線，其係配置於前述晶粒墊之周圍而向與前述晶粒墊之對向方向延伸；及支持部，其係連接前述導線之遠離前述晶粒墊之側之端部。在前述 導線中，在與遠離前述晶粒墊之側之端部之前述一方側相反側之面，在與該導線之長側方向正交且與厚度方向正交之寬度方向之全寬中形成有溝。
利用此導線架，藉由包含下列步驟之製造方法，可製造可防止溢料引起之安裝不良之發生之半導體裝置：接合步驟，其係將半導體晶片晶粒接合在前述晶粒墊上，以接合線電性連接前述半導體晶片與前述導線；封裝步驟，其係在前述接合步驟後，以使埋入前述溝之前述焊料由封裝樹脂露出之方式，藉前述封裝樹脂將前述半導體晶片與前述導線架同時封裝；及切割步驟，其係藉使用切割鋸之切斷，除去前述支持部及前述支持部上之前述封裝樹脂。
在導線架之與配置半導體晶片之一方側相反側之面，於導線之遠離晶粒墊之側之端部形成溝。此溝被焊料所完全填埋。因此，在除去支持部及支持部上之封裝樹脂之切割步驟中，切割鋸之側面會接觸到導線、埋在溝中之焊料及封裝樹脂。由於溝沿著導線之寬度方向之全寬中形成，故即使產生因埋入溝中之焊料被切割鋸拉扯而延伸之溢料，導線之材料也不會產生因被切斷刀拉扯而延伸之溢料。即使有焊料構成之溢料存在，該溢料也會被半導體裝置對安裝基板之安裝時之回流所熔化，故不會有發生半導體裝置以傾斜之狀態被安裝於安裝基板之虞。故依據前述之製造方法，可製造可防止溢料引起之安裝不良之發生之半導體裝置。
本發明之上述或其他目的、特徵及效果可由參照附圖之 後述之實施型態之說明獲得更明確之瞭解。
以下，參照附圖詳細說明本發明之實施型態。
圖1係本發明之一實施型態之半導體裝置之圖解的剖面圖。
半導體裝置1係適用QFN之半導體裝置。半導體裝置1係包含半導體晶片2、支持此半導體晶片2之晶粒墊3、與半導體晶片2電性連接之複數導線4、及將此等封裝之封裝樹脂5。
半導體晶片2係在形成功能元件之側之表面(元件形成面)朝向上方之狀態下，被晶粒接合於晶粒墊3上。又，在半導體晶片2之表面，藉使布線層之一部分由表面保護膜露出而形成複數個墊(未圖示)。各墊係經由細金線構成之接合線6與導線4電性連接。
晶粒墊3及導線4如後所述，係由金屬薄板所形成。
晶粒墊3一體地包含有平面視呈矩形狀之本體部7與包圍本體部7之周圍之平面視呈矩形框狀之脫落防止部8。
本體部7係使其下面7A由封裝樹脂5之下面5A露出。在由此封裝樹脂5之下面5A露出之本體部7之下面7A，例如形成有焊料電鍍層(未圖示)。
脫落防止部8係形成薄於本體部7。脫落防止部8之上面係與本體部7之上面形成同一平面。在與半導體晶片2同時樹脂封裝導線4之狀態下，封裝樹脂5會環繞進入脫落防止部8之下方，故可謀求防止晶粒墊3由封裝樹脂5脫落。
導線4係在與晶粒墊3之各側面正交之各方向之兩側，分別各設有相同數量。與晶粒墊3之各側面對向之導線4係等間隔地配置於與該對向之側面平行之方向。
各導線4係在與晶粒墊3之側面正交之方向(與晶粒墊3之對向方向)形成為長條之平面視呈矩形狀。而，各導線4係一體地包含本體部9、及由下面側對晶粒墊3側之端部擠壓加工所形成之脫落防止部10。
本體部9係使其下面9A由封裝樹脂5之下面5A露出，長側方向之端面9B由封裝樹脂5之側面5B露出。在由封裝樹脂5之下面5A露出之本體部9之下面9A，例如形成有焊料電鍍層(未圖示)，此下面9A係執行作為焊料接合於安裝基板(布線基板)上之接合面之外部端子之功能。另一方面，本體部9之上面係被封裝樹脂5所封裝。本體部9之上面擔負作為內導線之任務，連接有接合線6。
在本體部9之與脫落防止部10側相反側之端部，將在下面9A及端面9B開放之溝11形成在與導線4之長側方向正交且與厚度方向正交之寬度方向(沿著端面5B之方向)之全寬中。
在溝11，埋設有由焊料構成之埋設體12。此埋設體12具有與本體部9之下面9A形成同一平面之下面12A及與本體部9之端面9B形成同一平面之端面12B。又，埋設體12係在下面12A之端面12B側之端面，具有使埋設體12之材料之焊料向下方延伸所形成溢料13。
脫落防止部10係形成薄於本體部9。脫落防止部10之上 面係與本體部9之上面形成同一平面。在與半導體晶片2同時樹脂封裝導線4之狀態下，封裝樹脂5會環繞進入脫落防止部10之下方，故可謀求防止導線4由封裝樹脂5脫落。
圖2係表示使用於半導體裝置1之製造之導線架之一部分之底面圖。
半導體裝置1如後所述，係由使用之導線架21之MAP方式所製造。
導線架21係由對金屬(例如，銅、42合金等)之薄板加工所形成。此導線架21係一體地包含格子狀之支持部22、配置於被支持部22所包圍之各矩形區域內之晶粒墊3、及配置於晶粒墊3之周圍之複數導線4。
各導線4係將與晶粒墊3側相反側之端部連接於支持部22。在互相相鄰之晶粒墊3之間，配置於一方之晶粒墊3之周圍之各導線4與配置於他方之晶粒墊3之周圍之各導線4係在導線4之長側方向夾著支持部22而相對向，且延伸成一直線狀。而，夾著支持部22而相對向各導線4之溝11係藉由與溝11同樣深度及寬度形成在支持部22之溝23而連通。即，在夾著支持部22而相對向各導線4之端部間，將溝11及溝23形成作為向導線4之長側方向延伸之1條溝。又，在圖2中，為容易瞭解起見，在溝11及溝23上附上交叉影線。
圖3A~3E係依序表示半導體裝置1之製造步驟之圖解的剖面圖。
在半導體裝置1之製造步驟中，如圖3A所示，準備導線 架21。
又，在圖3A~3E中，導線架21僅顯示其切剖面。
首先，如圖3B所示，在導線架21之溝11及溝23中，填埋焊料31。焊料31例如可藉電鍍而形成。又，焊料31也可藉膏印刷及回流而形成。另外，焊料31也可在將球狀焊料配置於溝11及溝23後藉施行回流而形成。
其次，如圖3C所示，在導線架21之晶粒墊3上，例如，經由高熔點焊料(熔點260℃以上之焊料)構成之接合劑(未圖示)晶粒接合半導體晶片2。接著，將接合線6之一端連接於半導體晶片2之墊，將接合線6之他端連接(線接合)於導線4之上面。
所有之半導體晶片2之線接合完成時，如圖3D所示，將導線架21安置於成型模具，並將導線架21上之所有之半導體晶片2與導線架21同時利用封裝樹脂32一併加以封裝。而，在由封裝樹脂32露出之導線架21之下面(晶粒墊3之本體部7之下面7A、導線4之本體部9之下面9A)形成焊料電鍍層(未圖示)。
其後，如圖3E所示，沿著設定於導線架21之支持部22上之切割線，將切割鋸33由導線架22之下面側置入，除去支持部22、支持部22上之封裝樹脂32、以及存在於支持部22之兩側之特定寬度之區域之導線4之一部分及封裝樹脂32。即，除去存在於圖2所示之二點鏈線所夾之帶狀區域之導線架21及封裝樹脂32。藉此，各導線4被自支持部22切離，埋設於溝11之焊料31成為埋設體12，切離分開之封 裝樹脂32成為封裝樹脂5而獲得圖1所示之半導體裝置1之個體。
在利用此切割鋸33之切斷時(切割時)，切割鋸33之側面會接觸到導線4、焊料31(埋設體12)及封裝樹脂32(封裝樹脂5)。因此，埋在溝11之焊料31會被切割鋸33之側面拉扯而延伸，如圖1所示，在埋設體12之下面12A之端面12B側之端部有可能產生溢料13。但，因溝11係沿著導線4之寬度方向之全寬中形成，故導線4之材料不會產生因被切斷刀拉扯而延伸之溢料。即使有焊料構成之溢料13存在，該溢料13也會被半導體裝置1對安裝基板之安裝時之回流所熔化，故不會有發生半導體裝置1以傾斜之狀態被安裝於安裝基板之虞。故半導體裝置1不會發生溢料13引起之安裝不良。
又，因埋設體12係由焊料所構成，故可使利用作為導線4與安裝基板之接合劑之焊料濕潤達到埋設體12之端面12B，可在導線4之端面形成所謂焊料嵌條。因此，容易從外觀檢查導線4與布線基板之接合(焊接)狀態。
又，在本實施型態中，在導線架21中，夾著支持部22而相對向各導線4之溝11係藉由與溝11同樣深度及寬度形成在支持部22之構23而連通。但，在導線架21中，若形成在各導線4之溝11達到支持部22之兩側之特定寬度之區域(夾在圖2所示之二點鏈線間之帶狀區域)，則也可不在支持部22形成構23。即，只要將溝11形成使切割鋸33之側面可接觸到埋入溝11之焊料31之長度，則也可不在支持部22形成 構23。
以上，說明本發明之一實施型態，但本發明也可以其他之型態實施。例如，雖提到適用QFN之半導體裝置，但，本發明也可適用於適用SON(Small Outlined Non-leaded Package：無接腳小外形封裝)等其他種類之無接腳封裝之半導體裝置。
又，不限於導線之端面與封裝樹脂之側面形成同一平面之所謂切割獨立型，本發明也可適用於適用導線由封裝樹脂之側面突出之導線切斷型之無接腳封裝之半導體裝置。
另外，不限於無接腳封裝，本發明也可適用於適用導線由封裝樹脂突出之具有外導線之封裝之半導體裝置。
再者，半導體裝置不限於MAP方式，也可利用個別地封裝各個半導體晶片之個別封裝法製造。
以上，雖已就本發明之實施型態予以詳細說明，但此等僅不過係用於說明本發明之技術的內容之具體例，本發明不應被限定於此等具體例而作解釋，本發明之精神及範圍僅受到後附之申請專利範圍所限定。
本申請案對應於2007年2月27日向日本國特許廳提出之特願2007-47394號，該申請案之所有揭示可經由引用而納入於此。
1‧‧‧半導體裝置
2‧‧‧半導體晶片
3‧‧‧晶粒墊
4‧‧‧導線
5‧‧‧封裝樹脂
6‧‧‧接合線
9A‧‧‧下面(接合面)
9B‧‧‧端面
11‧‧‧溝
12‧‧‧埋設體
21‧‧‧導線架
22‧‧‧支持部
23‧‧‧溝
31‧‧‧焊料
32‧‧‧樹脂
33‧‧‧切割鋸
圖1係本發明之一實施型態之半導體裝置之圖解的剖面圖。
圖2係表示使用於半導體裝置之製造之導線架之一部分
之底面圖。
圖3A係表示半導體裝置之製造步驟(準備導線架之步驟)之圖解的剖面圖。
圖3B係表示圖3A之次一步驟(埋設焊料之步驟)之圖解的剖面圖。
圖3C係表示圖3B之次一步驟(接合步驟)之圖解的剖面圖。
圖3D係表示圖3C之次一步驟(封裝步驟)之圖解的剖面圖。
圖3E係表示圖3D之次一步驟(切割步驟)之圖解的剖面圖。
1‧‧‧半導體裝置
2‧‧‧半導體晶片
3‧‧‧晶粒墊
4‧‧‧導線
5‧‧‧封裝樹脂
5A‧‧‧封裝樹脂之下面
5B‧‧‧封裝樹脂之側面
6‧‧‧接合線
7‧‧‧本體部
7A‧‧‧本體部之下面
8、10‧‧‧脫落防止部
9‧‧‧本體部
9A‧‧‧下面(接合面)
9B‧‧‧端面
11‧‧‧溝
12‧‧‧埋設體
12A‧‧‧埋設體之下面
12B‧‧‧埋設體之端面
13‧‧‧溢料

Claims (6)

  1. 一種半導體裝置，其係包含：半導體晶片；及導線，其係配置於前述半導體晶片之周圍而向與前述半導體晶片之側面交叉之方向延伸，至少遠離前述半導體晶片之側之端部被接合於安裝基板；其中在前述導線中，形成有在前述安裝基板之接合面及在遠離前述半導體晶片之側之端面開放之溝，該溝係遍及與長側方向正交且與厚度方向正交而沿著前述端面之寬度方向之全寬地形成；且於前述溝，埋設有包含焊料之埋設體。
  2. 如請求項1之半導體裝置，其中前述導線之溝，係由前述導線之厚度方向之一半深度的溝、及與該溝連通之前述導線之厚度方向之剩餘另一半深度的溝所形成，成為向前述導線之長側方向延伸之1條溝。
  3. 如請求項1或2之半導體裝置，其中前述埋設體係包含焊料延伸而形成之溢料。
  4. 一種導線架，其係包含：晶粒墊，其係在一方側之面裝載有半導體晶片；導線，其係配置於前述晶粒墊之周圍而向與前述晶粒墊之對向方向延伸；及支持部，其係連接有前述導線之遠離前述晶粒墊之側之端部；其中在前述導線中，在與遠離前述晶粒墊之側之端部之前 述一方側相反側之面形成有溝，該溝係遍及與該導線之長側方向正交且與厚度方向正交之寬度方向之全寬地形成；且前述溝係被焊料完全填埋。
  5. 如請求項4之導線架，其中前述導線之溝，係與形成於前述支持部且與前述溝同樣深度及寬度之連通用溝連通，成為向前述導線之長側方向延伸之1條溝。
  6. 一種半導體裝置之製造方法，其係利用如請求項4或5之導線架製造半導體裝置之方法，包含：接合步驟，其係在前述晶粒墊上晶粒接合半導體晶片，以接合線電性連接前述半導體晶片與前述導線；封裝步驟，其係在前述接合步驟後，以使埋入前述溝之前述焊料由封裝樹脂露出之方式，藉前述封裝樹脂將前述半導體晶片與前述導線架一起封裝；及切割步驟，其係藉使用切割鋸之切斷，除去前述支持部及前述支持部上之前述封裝樹脂。
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