TWI573235B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI573235B
TWI573235B TW099130820A TW99130820A TWI573235B TW I573235 B TWI573235 B TW I573235B TW 099130820 A TW099130820 A TW 099130820A TW 99130820 A TW99130820 A TW 99130820A TW I573235 B TWI573235 B TW I573235B
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Taiwan
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island
semiconductor wafer
semiconductor device
lead
pin
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TW099130820A
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English (en)
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TW201125088A (en
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安永尚司
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羅姆股份有限公司
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description

半導體裝置及其製造方法
本發明係關於半導體裝置及其製造方法
典型之半導體裝置包含晶片焊墊；配置於晶片焊墊上之半導體晶片；配置於晶片焊墊之周圍之引腳；及連接半導體晶片與引腳之導線。
架設導線時，通常先將導線接合於半導體晶片(第一接合)，其次，進行接合於引腳(第二接合)之正常接合。但半導體晶片之連接導線之部分(焊墊)與引腳之高低差較大之情況時，由於難以將導線良好地接合於引腳，故進行所謂的逆向接合。在逆向接合中，將導線對引腳進行第一接合，再對半導體晶片進行第二接合。
圖34係藉由逆向接合而架設導線之半導體裝置之模式性側視圖。
半導體晶片201在將元件形成面即表面朝向上方的狀態下，使其背面接合於晶片焊墊202之上面。於半導體晶片201之表面之周緣部，配置有焊墊203。且，在焊墊203與配置於晶片焊墊202之周圍之引腳204之上面之間，架設有導線205。
導線接合時，為將晶片焊墊202及引腳204固定於打線機，藉由壓板208按壓引腳204。壓板208抵接於引腳204之上面之相對於導線205(球部206)之接合位置與半導體晶片201之相反側上隔以微小之間隔之位置。且，在被保持於打線機之焊針C(以虛線表示)之導線205之前端，形成FAB(Free Air Ball：結球)，使該FAB接合於引腳204之上面。其後，使焊針C向焊墊203移動，使導線205壓抵於焊墊203，進而被扯開。藉此，於焊墊203與引腳204之間架設導線205。藉由逆向接合所架設之導線205於引腳204上具有葫蘆形狀之球部206，且於焊墊203上具有側視楔狀之針腳部207。
樹脂密封型半導體裝置具有將半導體晶片以導線架與樹脂封裝一起密封之構造。導線架係藉由沖切金屬薄板而形成，其具備島狀物(晶片焊墊)、與配置於該島狀物之周圍之複數個引腳。半導體晶片被晶片接合於島狀物之上面，且藉由架設於其表面與各引腳之間之接合線，與各引腳電性連接。
半導體晶片對島狀物之晶片接合可使用例如焊膏等之糊狀之接合劑。於島狀物之上面塗布糊狀之接合劑後，於接合劑上配置半導體晶片，對半導體晶片施加負載。藉此將接合劑於半導體晶片與島狀物之間壓平擴散，而接合半導體晶片與島狀物，達成半導體晶片對島狀物之晶片接合。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特開2004-207292號公報
[專利文獻2]日本特開2003-249616號公報
參照圖34，於引腳204接合FAB後，若焊針C向焊墊203直線性移動，則導線205會有接觸到半導體晶片201之角部之虞。因此，如圖34中虛線所示，焊針C一旦向與半導體晶片201遠離之側移動後，會向焊墊203移動。然而，此時，焊針C與壓板208恐有接觸之虞。
因此，為防止焊針C與壓板208之接觸，於FAB(球部206)之接合位置與壓板208之間，設置充分之空隙。因此，即使縮小半導體裝置之封裝尺寸，亦可增加能夠從1個導線架獲得之半導體裝置(晶片焊墊202及引腳204)之個數。
在正常接合中，不存在焊針C與壓板208接觸之問題。因此，只要可藉由正常接合獲得導線對引腳之良好之接合，則可增加能夠從1個導線架獲得之半導體裝置之個數。
另一方面，使用糊狀之接合劑(焊錫)之情況下，在對半導體晶片施加負載時，會有從半導體晶片與島狀物之間向其周圍大量溢出接合劑之情形。該接合劑之露出會產生如下所示之各種不良情況。
例如，當島狀物小之情況時，該露出之接合劑會從島狀物上溢出。又，即使島狀物相較於半導體晶片形成得夠大，於半導體晶片與島狀物之間架設導線之情況時，接合劑亦會擴散到島狀物之用於導線接合(壓合)之空間，成為壓合之阻礙。再者，無論島狀物之大小為何，當半導體晶片為薄型之情況時，接合劑均會從半導體晶片之側方回捲至表面。
為解決因接合劑之擴散所引起之問題，考慮使用DAF(Die Attach Film：晶片黏著薄膜)。DAF為薄膜狀之接合材。在半導體晶片為晶圓之狀態下，於其背面貼附DAF。然後，將半導體晶圓與DAF一起予以切片，藉此獲得其背面貼附有DAF之半導體晶片。藉由將該半導體晶片壓抵於島狀物上，使島狀物與半導體晶片接合，達成半導體晶片對島狀物之晶片接合。
然而，在於晶圓之背面貼附有DAF之狀態下，難以將該晶圓切分成小尺寸(例如550 μm平方)，故小尺寸之半導體晶片之對島狀物之接合無法使用DAF。
本發明之一目的在於提供一種藉由正常接合使導線良好地接合於引腳之半導體裝置。
又，本發明之另一目的在於提供一種即使為小尺寸之半導體晶片，亦可防止因產生焊錫之擴散所引起之各種問題之半導體裝置及其製造方法。
本發明之一觀點之半導體裝置具備：半導體晶片；配置於上述半導體晶片之側方之引腳；及導線，其一端及另一端分別接合於上述半導體晶片及上述引腳，且於上述半導體晶片及上述引腳上分別具有球部及側視楔狀之針腳部。即，在本發明之半導體裝置中，藉由正常接合，將導線架設於半導體晶片(設置於半導體晶片之表面之焊墊)與配置於其側方之引腳之間。因此，導線於半導體晶片上具有球部，於引腳上具有側視楔狀之針腳部。
且，在一實施形態之半導體裝置中，導線對引腳之進入角度，即導線之針腳部側之端部與引腳所成之角度為50°以上。
該情況，只要針腳部之長度(導線與引腳之接觸部分之沿著導線之方向上的長度)為33 μm以上，則不會於導線之針腳部之附近產生龜裂，從而達成導線對引腳之良好之接合。
又，針腳部之上面與引腳之上面所成之角度為15°以上之情況，亦不會於導線之針腳部之附近產生龜裂，從而達成導線對引腳之良好之接合。
當然，即使針腳部之長度為33 μm以上，且針腳部之上面與引腳之上面所成之角度為15°以上，亦不會於導線之針腳部之附近產生龜裂，從而達成導線對引腳之良好之接合。
又，在一實施形態之半導體裝置中，導線之長度為400 μm以下，半導體晶片之球部之接合部分與引腳之上述針腳部之接合部分的高低差為200 μm以上。
該情況下，只要針腳部之長度為33 μm以上，則不會於導線之針腳部之附近產生龜裂，從而達成導線對引腳之良好之接合。
又，在針腳部之上面與引腳之上面所成之角度為15°以上之情況下，亦不會於導線之針腳部之附近產生龜裂，從而達成導線對引腳之良好之接合。
當然，即使針腳部之長度為33 μm以上，且針腳部之上面與引腳之上面所成之角度為15°以上，亦不會於導線之針腳部之附近產生龜裂，從而達成導線對引腳之良好之接合。
又，本發明之一觀點之半導體裝置之製造方法包含以下步驟：支撐體配置步驟，於島狀物上配置包含固體之焊錫之支撐體；晶片支撐步驟，在上述支撐體配置步驟後，於上述支撐體上載置半導體晶片，由上述支撐體支撐上述半導體晶片；及接合步驟，在上述晶片載置步驟後，藉由熱處理，使上述支撐體熔融而接合上述島狀物與上述半導體晶片。
根據該半導體裝置之製造方法，首先，於島狀物上配置包含固體之焊錫之支撐體。然後於支撐體上載置半導體晶片。藉此由支撐體支撐半導體晶片。其後，藉由熱處理，使支撐體(焊錫)熔融，而接合島狀物與半導體晶片。
於熱處理時，藉由焊錫所具有之表面張力及濡濕性，使熔融之焊錫於半導體晶片與島狀物之間擴散。因此，與將半導體晶片與島狀物接合所使用之糊狀之接著劑之方法不同，在將半導體晶片對島狀物接合時，無需對半導體晶片施加負載。不對半導體晶片施加負載，藉此可防止該負載所引起之焊錫之擴散。又，根據半導體晶片之尺寸而變更支撐體之大小、形狀及個數，藉此無論半導體晶片之尺寸為何，均不會產生從半導體晶片與島狀物之間大幅溢出之焊錫，而可接合半導體晶片與島狀物。因此，即使是小尺寸之半導體晶片，亦不會產生因焊錫之擴散所引起之各種問題，從而可達成對島狀物之晶片接合。
較佳為在支撐體配置步驟之前，進而包含於島狀物上包含銀之薄膜之步驟，且在支撐體配置步驟中，於薄膜上配置支撐體。由於焊錫對銀之濡濕性較高，故當熱處理時使支撐體熔融，則該熔融之支撐體(焊錫)會在形成包含銀之薄膜之範圍內擴散。因此，藉由形成包含銀之薄膜，可控制焊錫之擴散，從而可確實防止因焊錫之擴散所引起之各種問題產生。
又，亦可於島狀物形成有從其上面往下挖之凹部，且在支撐體配置步驟中，將支撐體配置於凹部內。藉此可使支撐體穩定配置於島狀物。
又，亦可於支撐體配置步驟後、晶片支撐步驟之前，進而包含於支撐體塗布助焊劑之助焊劑塗布步驟。藉此可防止支撐體之表面被氧化，且可提高熱處理時之支撐體(焊錫)之濡濕性。又，由於半導體晶片及島狀物之與助焊劑之接觸部分係利用助焊劑之作用而被洗淨，故可進一步提高半導體晶片與島狀物之接著性。
半導體裝置之製造方法包含助焊劑塗布步驟之情況下，在藉由該製造方法而製造之半導體裝置中，於接合半導體晶片與島狀物之焊錫接合劑附著有助焊劑。即，藉由包含助焊劑塗布步驟之製造方法製造之半導體裝置包含：半導體晶片；於上面接合上述半導體晶片之島狀物；及包含焊錫，且介存於上述半導體晶片與上述島狀物之間，使上述半導體晶片與上述島狀物接合之焊錫接合劑；且，於上述焊錫接合劑附著有助焊劑。
本發明之上述之或進而其他之目的、特徵及效果參照附加圖式，藉由後述之實施形態之說明予以闡明。
 <第1實施形態>
圖1A係本發明之第1實施形態之半導體裝置之平面圖。圖1B係對圖1A應用變形例之圖。在圖1A~圖1B中，以實線顯示穿透由樹脂封裝所密封之各構件。圖2A係顯示從圖1A所示之半導體裝置中省略半導體晶片、導線及焊錫接合劑之狀態之模式平面圖。圖2B係於圖2A適用變形例之圖。圖3係以切斷線III-III切斷圖1A所示之半導體裝置時之模式剖面圖。圖4係圖1A所示之切斷線IV-IV之半導體裝置之模式剖面圖。在圖4中，省略了樹脂封裝之圖式。
半導體裝置1具有對導線架2接合半導體晶片3，並將該等以樹脂封裝4進行密封之構造。半導體裝置1(樹脂封裝4)之外形為扁平之長方體形狀(在本實施形態中，俯視為正方形之6面體)。
如圖1A所示，導線架2具備俯視時配置於半導體裝置1之中央部之晶片焊墊(島狀物)5，與配置於晶片焊墊5之周圍之4個引腳6。導線架2係藉由沖切金屬薄板(例如銅薄板)而形成。
晶片焊墊5一體化具備中央部7、與垂吊部8。中央部7形成為俯視時其中心與樹脂封裝4之中心重疊，且相對於樹脂封裝4之各邊具有45°傾斜之4邊之俯視四角形狀。垂吊部8形成為從中央部7之各角部向該角部所對向之樹脂封裝4之側面延伸之俯視四角形狀。中央部7之下面在樹脂封裝4之背面露出。
於中央部7形成有從其上面往下挖之2個(一對)槽狀之凹部107(參照圖2A)。各凹部107形成為剖面半圓形狀，且分別與中央部7之相對之2邊平行地延伸。在中央部部7之上面、俯視時包含形成有凹部107之部分之區域，形成有包含銀(Ag)之薄膜108(參照圖2A)。具體而言，如圖3所示，薄膜108在於島狀物5上接合有半導體晶片3的狀態下，形成為與島狀物5之與半導體晶片3之對向部分大致相同之尺寸。
俯視時，引腳6分別於與晶片焊墊5之中央部7之各邊對向之部分各配置1個。各引腳6形成為俯視梯形狀。更具體而言，各引腳6具有與晶片焊墊5對向之邊平行之邊9；在樹脂封裝4之側面上延伸之邊10；與邊10正交，並與樹脂封裝4之側面平行地延伸之邊11；分別連接邊9與邊10、11之邊12、13。各引腳6之下面在樹脂封裝4之背面露出，作為用於連接配線基板(未圖示)之外部端子發揮功能。又，各引腳6之具有邊10之側面在樹脂封裝4之側面露出。再者，如圖1B及圖2B所示，各引腳6亦可形成為俯視三角形狀。
如圖3所示，半導體晶片3在使元件形成面即表面(器件形成面)朝向上方的狀態下，使其背面經由導電性焊錫接合劑109而接合於晶片焊墊5(晶片接合)。於半導體晶片3之背面覆蓋有用於提高焊錫接合劑109與半導體晶片3之接著性之金屬膜115。金屬膜115為例如藉由從半導體晶片3側依序積層Au(金)、Ni(鎳)、Ag及Au而形成之積層膜。於焊錫接合劑109之周緣部，即半導體晶片3與島狀物5之接合部分之側方，附著有固化成樹脂狀之固化助焊劑110。
半導體晶片3之厚度為200 μm以上(在本實施形態中為230 μm)於半導體晶片3之表面(詳細而言，為後述之焊墊14之表面)與引腳6之上面之間，存在對應該半導體晶片3之厚度之高低差。
如圖1A所示，於半導體晶片3之表面形成有與形成於半導體晶片3之配線(未圖示)電性連接之5個焊墊14。4個焊墊14(以下稱為「角部焊墊14」)配置於半導體晶片3之各角部。剩餘的1個焊墊14(以下稱為「剩餘焊墊14」)鄰接配置於其中1個角部焊墊14。
於各焊墊14接合有導線(接合導線)15之一端。各導線15之另一端接合於引腳6之上面。具體而言，一端接合於4個角部焊墊14之導線15之另一端分別接合於相互不同之引腳6之上面。一端接合於剩餘焊墊14之導線15之另一端接合於距離該剩餘焊墊14最近之引腳6。藉此半導體晶片3經由導線15而與引腳6電性連接。導線15之長度為400 μm以下(在本實施形態中為300~400 μm)。
再者，切割線III-III係相對於半導體晶片3之從圖1A之下端之角部焊墊14延伸的導線15、與從上述之剩餘焊墊14延伸的導線15兩者而平行地延伸。切割線III-III實際上與該等之導線15重疊，但為便於觀察該等之導線15，圖示自該等之導線15略微偏移之位置。又，切割線IV-IV與半導體晶片3之從圖1A之上端之角部焊墊14延伸之導線15平行地延伸。切割線IV-IV實際上與該導線15重疊，但為便於觀察該導線15，圖示為自該導線15略微偏移之位置。
各導線15係藉由正常接合形成。即，導線15之形成時(打線接合時)，對被保持於打線機之焊針C(參照圖34)之導線15之前端部施加電流，藉此於其前端部形成FAB(Free Air Ball：結球)。然後，藉由焊針C之移動，使FAB壓抵於焊墊14。藉由將FAB按壓於焊針C，使FAB變形，而如圖4所示，於焊墊14上形成葫蘆形狀之球部16，從而達成導線15之一端對焊墊14之接合(第一接合)。其後，使焊針C與焊墊14之上方分開特定之高度。然後，使焊針C以相對於引腳6之上面大於50°之傾斜角度向引腳6之上面移動，使導線15壓抵於引腳6之上面，進而被扯開。藉此使導線15之另一端變形，於引腳6上形成側視楔狀之針腳部17，從而達成導線15之另一端對引腳6之接合(第二接合)。因此，導線15於焊墊14上具有球部16，於引腳16上具有針腳部17。
第二接合時，焊針C以相對於引腳6之上面大於50°之傾斜角移動，藉此使導線15對引腳6之上面之進入角度，即導線15之針腳部17側之端部與引腳6之上面所成之角度β為50°以上。
且，在半導體裝置1中，針腳部17之長度(導線15與引腳6之接觸部分之沿著導線15之方向上的長度)L為33 μm以上。又，針腳部17之上面與引腳6之上面所成之角度α為15°以上。
藉此，導線15對引腳6之上面之進入角度即使為50°以上，導線15之針腳部17之附近亦不會產生龜裂，從而達成導線15對引腳6之良好之接合。又，即使導線15之長度為400 μm以下，且半導體晶片3之表面與引腳6之上面之高低差為200 μm以上，導線15之針腳部17之附近亦不會產生龜裂，從而達成導線15對引腳6之良好之接合。
圖5A~圖5E係用於依序說明圖1A及圖1B所示之半導體裝置之製造步驟的模式剖面圖。再者，在圖5A~圖5E中，省略了引腳6及接合導線15等之圖式。
首先，準備具備形成有凹部107之島狀物5之導線架2。導線架2係藉由例如將銅薄板進行衝壓加工及沖切加工而形成。且，如圖5A所示，藉由電鍍法或濺鍍法，於島狀物5上形成包含銀之薄膜108。此時，於凹部107之內面亦形成薄膜108。
其次，如圖5B所示，於凹部107內之薄膜108上，配置固體之包含焊錫之支撐體113。支撐體113俯視時形成為與凹部107大致同形狀，且剖面成圓形。
其後，如圖5C所示，於支撐體113塗布助焊劑114。助焊劑114可全部塗布於島狀物5之上面之全域，亦可選擇性塗布於支撐體113之從凹部107露出之部分。
其次，如圖5D所示，於支撐體113上載置半導體晶片3。藉此由支撐體113支撐半導體晶片3。
且，例如支撐體113為鉛焊錫之情況，在340℃之溫度條件下進行30 sec之熱處理，藉此如圖5E所示，熔融支撐體113，並藉由其表面張力及濡濕性，使支撐體113在形成有薄膜108之範圍內擴散。藉此可藉由熔融之支撐體113(焊錫接合劑109)填埋半導體晶片3與島狀物5之對向部分之間隙，從而達成半導體晶片3與島狀物5之接合。又，此時，助焊劑114一面洗淨半導體晶片3之下面(金屬膜115之表面)及島狀物5之上面，一面在半導體晶片3之側方凝聚固化，成為固化助焊劑110。
其後，於半導體晶片3與引腳6之間架設接合導線15，以僅使島狀物5及引腳6之背面露出的方式形成樹脂封裝4，藉此獲得圖1A~3所示之半導體裝置1。
如上所示，於熱處理時，藉由焊錫所具有之表面張力及濡濕性，使熔融之焊錫於半導體晶片3與島狀物5之間擴散。因此，與將半導體晶片3與島狀物5接合所使用糊狀之接著劑之方法不同，在將半導體晶片3對島狀物5接合時，無需對半導體晶片3施加負載。不對半導體晶片3施加負載，藉此可防止該負載所引起之焊錫之擴散。又，根據半導體晶片3之尺寸而變更支撐體113之大小、形狀及個數，藉此無論半導體晶片3之尺寸為何，均不會產生從半導體晶片3與島狀物5之間大幅溢出之焊錫，從而可接合半導體晶片3與島狀物5。因此，即使為小尺寸之半導體晶片3，亦不會產生因焊錫之擴散所引起之各種問題，從而可達成對島狀物5之晶片接合。
支撐體113係配置於包含銀之薄膜108上。由於焊錫對銀之濡濕性較高，故當熱處理時使支撐體113熔融，則該熔融之支撐體113會在形成有包含銀之薄膜108之範圍內擴散。因此，藉由形成包含銀之薄膜108，可控制支撐體113之擴散，從而可確實防止因焊錫之擴散所引起之各種問題。
又，於島狀物5形成從其上面往下挖之凹部107，將支撐體113配置於凹部107內。藉此可使支撐體113穩定配置於島狀物5上。
又，由於對支撐體113塗布助焊劑114，故可防止支撐體113之表面被氧化，且可提高熱處理時之支撐體113(焊錫)之濡濕性。又，由於半導體晶片3及島狀物5之與助焊劑114之接觸部分係利用助焊劑114之作用而被洗淨，故可進一步提高半導體晶片3與島狀物5之接著性。
圖6係顯示島狀物及支撐體之其他之構成之立體圖。
圖6所示之島狀物121可取代成圖1A所示之島狀物5而使用。
島狀物121成俯視四角形狀。於島狀物121形成有從其上面往下挖成半球狀之3個凹部122。各凹部122係以使連結該等之線之內側成三角形的方式，相互隔以間隔而配置。
在島狀物121之上面、俯視時包含形成有凹部122之部分之區域，形成有包含銀之薄膜123。具體而言，薄膜123在於島狀物121上接合有半導體晶片3(參照圖1A)的狀態下，形成為與島狀物121之與半導體晶片3之對向部分大致相同之尺寸。又，薄膜123亦可形成於各凹部122之內面。
於凹部122內之薄膜123上配置支撐體124。支撐體124形成為具有與凹部122大致相同之直徑之球狀。
若將半導體晶片3載置於3個支撐體124上並進行熱處理，則支撐體124會熔融，並藉由其表面張力及濡濕性，使支撐體124(焊錫)在形成有薄膜123之範圍內擴散。藉此可藉由熔融之支撐體124填埋半導體晶片3與島狀物121之對向部分之間隙，從而達成半導體晶片3與島狀物121之接合。
圖7係顯示島狀物及支撐體之進而其他之構成之立體圖。
圖7所示之島狀物131可取代圖1A所示之島狀物5而使用。
島狀物131成俯視四角形狀。於島狀物131之上面形成有包含銀之薄膜132，具體而言，薄膜132在於島狀物131上接合有半導體晶片3(參照圖1A)的狀態下，形成為與島狀物131之與半導體晶片3之對向部分大致相同之尺寸。
於薄膜132上配置2個支撐體133。支撐體133形成為俯視細長板狀(帶狀)，且相互隔以間隔平行地延伸。
若將半導體晶片3載置於2個支撐體133上並進行熱處理，則支撐體133會熔融，並藉由其表面張力及濡濕性，使支撐體133(焊錫)在形成有薄膜132之範圍內擴散。藉此，可藉由熔融之支撐體133填埋半導體晶片3與島狀物131之對向部分之間隙，從而達成半導體晶片3與島狀物131之接合。
再者，在本實施形態之半導體裝置1中，雖採用QFN(Quad Flat Non-leaded Package：四方形扁平無引腳封裝)，然本實施形態亦可應用於採用SON(Small Outlined Non-leaded Package：小外型無引腳封裝)等其他種類之無引腳封裝之半導體裝置。
又，本實施形態並不限定於引腳之端面與密封樹脂之側面齊平面地形成之所謂的去框型(Singulation Type)，亦可應用於採用使引腳從密封樹脂之側面突出之引腳切割型之無引腳封裝之半導體裝置。
再者，本實施形態並不限定於無引腳封裝，亦可應用於採用QFP(Quad Flat Package：四方形扁平封裝)等、使引腳從密封樹脂突出之具有外引腳之封裝之半導體裝置。
又，作為半導體裝置1，雖示例有從樹脂封裝之背面露出引腳及島狀物之背面之所謂的表面安裝型半導體裝置，但本實施形態亦可應用於使引腳向樹脂封裝之側方延伸之樹脂密封型半導體裝置。即，本實施形態可廣泛適用於具有於島狀物上接合半導體晶片之構造之半導體裝置。
其次，基於實施例及比較例說明本發明，但本發明並非受以下之實施例所限定者。
1.　實施例1
使用圖8所示之焊針，藉由正常接合，於半導體晶片之表面之焊墊與引腳之間架設線徑25 μm之金導線。圖8所示之焊針之T尺寸為130 μm，CD尺寸為50 μm。導線對引腳之上面之進入角度為50°
且，使用掃描型電子顯微鏡(SEM：Scanning Electron Microscope)，觀察金導線之與引腳之接合部分(針腳部)。將此時之SEM圖像顯示於圖9~11。
如圖9~11所示，在本實施例1中，確認形成長度33 μm之針腳部，且該針腳部之附近未產生龜裂等之缺陷。
2.　實施例2
使用圖12所示之焊針，藉由正常接合，於半導體晶片之表面之焊墊與引腳之間架設線徑25 μm之金導線。圖12所示之焊針之FA(Face Angle：面角)角為15°。導線對引腳之上面之進入角度為50°
且，使用掃描型電子顯微鏡，觀察金導線之與引腳之接合部分(針腳部)。將此時之SEM圖像顯示於圖13、14。
如圖13、14所示，在本實施例2中，確認形成其上面與引腳之上面所成之角度α為15°之針腳部，且該針腳部之附近未產生龜裂等之缺陷。
3.　比較例
使用圖15所示之焊針，藉由正常接合，於半導體晶片之表面之焊墊與引腳之間架設線徑25 μm之金導線。圖15所示之焊針之FA(Face Angle：面角)角為11°。導線對引腳之上面之進入角度為50°。
且，使用掃描型電子顯微鏡，觀察金導線之與引腳之接合部分(針腳部)。將此時之SEM圖像顯示於圖16。
如圖16所示，在本比較例中，確認在針腳部之附近產生龜裂。
<第2實施形態>
圖17係本發明之第2實施形態之半導體裝置之平面圖。在圖17中，以實線顯示穿透由樹脂封裝所密封之各構件。圖18係圖17所示之切割線A-A之半導體裝置之模式剖面圖。在圖18中，省略了樹脂封裝之圖式。再者，在本實施形態之說明中，對相當於第1實施形態之各部之部分使用相同之參照符號。
半導體裝置1具備對導線架2接合半導體晶片3，並將該等以樹脂封裝4密封之構造。半導體裝置1(樹脂封裝4)之外形為扁平之長方體形狀(在本實施形態中，為俯視正方形狀之6面體)。
如圖17所示，導線架2具備俯視時配置於半導體裝置1之中央部之晶片焊墊5、與配置於晶片焊墊5之周圍之4個引腳6。導線架2係藉由沖切金屬薄板(例如，銅薄板)而形成。
晶片焊墊5一體化具備中央部7、與垂吊部8。中央部7形成為俯視時其中心與樹脂封裝4之中心重疊，且具有相對於樹脂封裝4之各邊傾斜45°之邊之俯視四角形狀。垂吊部8形成為從中央部7自各角部向該角部所對向之樹脂封裝4之側面延伸之俯視四角形狀。中央部7之下面在樹脂封裝4之背面露出。
引腳6分別於與晶片焊墊5之中央部7之各邊對向之部分各配置1個。各引腳6形成為俯視梯形狀。更具體而言，各引腳6包含與晶片焊墊5所對向之邊平行之邊9；在樹脂封裝4之側面上延伸之邊10；與邊10正交，並與樹脂封裝4之側面平行地延伸之邊11；分別連接邊9與邊10、11之邊12、13。各引腳6之下面在樹脂封裝4之背面露出，並作為用於連接配線基板(未圖示)之外部端子發揮功能。又，各引腳6之具有邊10之側面在樹脂封裝4之側面露出。
半導體晶片3在使元件形成面即表面朝向上方的狀態下，經由導電性接合劑(未圖示)將其背面接合於晶片焊墊5(晶片接合)。半導體晶片3之厚度為200 μm以上(在本實施形態中，為230 μm)，且於半導體晶片3之表面(詳細而言，為後述之焊墊14之表面)與引腳6之上面之間對應該半導體晶片3之厚度之高低差。
在半導體晶片3之表面形成有與形成於半導體晶片3之配線(未圖示)電性連接之5個焊墊14。4個焊墊14(以下稱為「角部焊墊14」)配置於半導體晶片3之各角部。剩餘的1個焊墊14(以下稱為「剩餘焊墊14」)鄰接配置於1個角部焊墊14。
於各焊墊14接合有導線15之一端。各導線15之另一端接合於引腳6之上面。具體而言，一端接合於4個角部焊墊14之導線15之另一端係分別接合於相互不同之引腳6之上面。一端接合於剩餘焊墊14之導線15之另一端係接合於距離該剩餘焊墊14最近之引腳6。藉此，半導體晶片3經由導線15而與引腳6電性連接。導線15之長度為400 μm以下(在本實施形態中為300~400 μm)。
再者，切斷線A-A係與半導體晶片3之從圖17之上端之角部焊墊14延伸的導線15平行地延伸。切斷線A-A實際上與該導線15重疊，但為便於觀察該導線15，圖示為從該導線15略微偏移之位置。
各導線15係藉由正常接合形成，即，導線15之形成時(導線接合時)，對被保持於打線機之焊針C(參照圖34)之導線15之前端部施加電流，藉此於其前端部形成FAB(Free Air Ball：結球)。且，藉由焊針C之移動，使FAB壓抵於焊墊14。藉由將FAB按壓於焊針C，使FAB變形，而如圖18所示，於焊墊14上形成葫蘆形狀之球部16，從而達成導線15之一端對焊墊14之接合(第一接合)。其後，使焊針C與焊墊14於上方分開特定之高度。然後，使焊針C以相對於引腳6之上面大於50°之傾斜角度向引腳6之上面移動，使導線15壓抵於引腳6之上面，進而被扯開。藉此使導線15之另一端變形，於引腳6上形成側視楔狀之針腳部17，從而達成導線15之另一端對引腳6之接合(第二接合)。因此，導線15於焊墊14上具有球部16，於引腳6上具有針腳部17。
於第二接合時，使焊針C以相對於引腳6之上面大於50°之傾斜角移動，藉此使導線15對引腳6之上面之進入角度，即導線15之針腳部17側之端部與引腳6之上面所成之角度β為50°以上。
且，在半導體裝置1中，針腳部17之長度(導線15與引腳6之接觸部分之沿著導線15之方向上的長度)L為33 μm以上。又，針腳部17之上面與引腳6之上面所成之角度α為15°以上。
藉此，導線15對引腳6之上面之進入角度即使為50°以上，亦不會於導線15之針腳部17之附近產生龜裂，從而達成導線15對引腳6之良好之接合。又，即使導線15之長度為400 μm以下，且半導體晶片3之表面與引腳6之上面之高低差為200 μm以上，亦不會於導線15之針腳部17之附近產生龜裂，從而達成導線15對引腳6之良好之接合。
再者，在本實施形態中，雖採用QFN(Quad Flat Non-leaded Package：四方形扁平無引腳封裝)，然本實施形態亦可應用於採用SON(Small Outlined Non-leaded Package：小外型無引腳封裝)等其他種類之無引腳封裝之半導體裝置。
又，本實施形態並不限定於引腳之端面與密封樹脂之側面齊平面地形成之所謂的去框型，亦可應用於採用使引腳從密封樹脂之側面突出之引腳切割型之無引腳封裝之半導體裝置。
再者，本實施形態並不限定於無引腳封裝，亦可應用於採用QFP(Quad Flat Package：四方形扁平封裝)等使引腳從密封樹脂突出之具有外引腳之密封之半導體裝置。
其次，基於實施例及比較例說明本發明，但本發明並非受以下之實施例所限定者。
1.　實施例1
使用圖19之焊針，藉由正常接合，於半導體晶片之表面之焊墊與引腳之間架設線徑25 μm之金導線。圖19所示之焊針之T尺寸為130 μm，CD尺寸為50 μm。導線對引腳之上面之進入角度為50°
且，使用掃描型電子顯微鏡(SEM：Scanning Electron Microscope)，觀察金導線之與引腳之接合部分(針腳部)。將此時之SEM圖像顯示於圖20~22。
如圖20~22所示，在本實施例1中，確認形成長度33 μm之針腳部，且於該針腳部之附近未產生龜裂等之缺陷。
2.　實施例2
使用圖23所示之焊針，藉由正常接合，於半導體晶片之表面之焊墊與引腳之間架設線徑25 μm之金導線。圖23所示之焊針之FA(Face Angle：面角)角為15°。導線對引腳之上面之進入角度為50°
且，使用掃描型電子顯微鏡，觀察金導線之與引腳之接合部分(針腳部)。將此時之SEM圖像顯示於圖24、25。
如圖24、25所示，在本實施例2中，確認形成其上面與引腳之上面所成之角度α為15°之針腳部，且於該針腳部之附近未產生龜裂等之缺陷。
3.　比較例
使用圖26所示之焊針，藉由正常接合，於半導體晶片之表面之焊墊與引腳之間架設線徑25 μm之金導線。圖26所示之焊針之FA(Face Angle：面角)角為11°。導線對引腳之上面之進入角度為50°。
且，使用掃描型電子顯微鏡，觀察金導線之與引腳之接合部分(針腳部)。將此時之SEM圖像顯示於圖27。
如圖27所示，在本比較例中，確認於針腳部之附近產生龜裂。
<第3實施形態>
圖28係本發明之第3實施形態之半導體裝置之模式平面圖。圖29係顯示從圖28所示之半導體裝置中省略半導體晶片、導線及焊錫接合劑之狀態之模式平面圖。圖30係以切斷線B-B切斷圖28所示之半導體裝置時之模式剖面圖。再者，在本實施形態之說明中，對相當於第1及第2實施形態之各部之部分使用相同之參照符號。
半導體裝置1具有將半導體晶片3以導線架2與樹脂封裝4一起密封之構造。半導體裝置1之外形為扁平之長方體形狀(在本實施形態中，為俯視正方形狀之6面體)。
導線架2包含銅(Cu)等之金屬材料，且具備島狀物5與配置於島狀物5之周圍之4個引腳6。
島狀物5成俯視四角形狀(在本實施形態中，為俯視正方形狀)。島狀物5之下面在樹脂封裝4之背面露出。又，於島狀物5形成有從其上面往下挖之2個(一對)槽狀凹部107(參照圖29)。各凹部107形成為剖面半圓形狀，且分別與島狀物5所相對之2邊平行地延伸。在島狀物5之上面、俯視時包含形成有凹部107之部分之區域，形成有包含銀(Ag)之薄膜108(參照圖29)。具體而言，如圖28所示，薄膜108在於島狀物5上接合有半導體晶片3的狀態下，形成為與島狀物5之與半導體晶片3之對向部分大致相同之尺寸。
引腳6俯視時配置於與島狀物5之4邊分別對向之部分。各引腳6形成為俯視三角形狀。各引腳6之下面在樹脂封裝4之背面露出，並作為用於連接配線基板(未圖示)之外部端子發揮功能。
如圖30所示，半導體晶片3在使形成有功能元件之側之表面(器件形成面)朝向上方的狀態下，經由導電性焊錫接合劑109將其背面接合於島狀物5(晶片接合)。於半導體晶片3之背面覆蓋有用於提高焊錫接合劑109與半導體晶片3之接著性之金屬膜115。金屬膜115係例如藉由從半導體晶片3側依序積層Au(金)、Ni(鎳)、Ag及Au而形成之積層膜。
於焊錫接合劑109之周緣部，即半導體晶片3與島狀物5之接合部分之側方，附著有固化成樹脂狀之固化助焊劑110。
於半導體晶片3之表面，藉由與各引腳對應並使配線層之一部分從表面保護膜露出而形成焊墊14。於各焊墊14接合有接合導線15之一端。接合導線15之另一端接合於各引腳6之上面。藉此，半導體晶片3經由接合導線15而與引腳6電性連接。
再者，切斷線B-B相對於半導體晶片3之從圖28之下端之焊墊14延伸之導線15，與從圖28之右端之焊墊14之左方的焊墊14延伸之導線15兩者平行地延伸。切斷線B-B實際上與該等之導線15重疊，但為便於觀察該等之導線15，圖示為從該等之導線15略微偏移之位置。
圖31A~圖31E係用於依序說明圖28所示之半導體裝置之製造步驟之模式剖面圖。再者，在圖31A~圖31E中，省略了引腳6及接合導線15等之圖式。
首先，準備具備形成有凹部107之島狀物5之導線架2。導線架2係藉由例如將銅薄板進行衝壓加工及沖切加工而形成。且，如圖31A所示，藉由電鍍法或濺鍍法，於島狀物5上形成包含銀之薄膜108。此時，於凹部107之內面亦形成薄膜108。
其次，如圖31B所示，於凹部107內之薄膜108上配置包含固體之焊錫之支撐體113。支撐體113俯視時形成為與凹部107大致同形狀，且剖面成圓形。
其後，如圖31C所示，對支撐體113塗布助焊劑114。助焊劑114可一次塗布於島狀物5之上面之全域，亦可選擇性塗布於支撐體113之從凹部107露出之部分。
其次，如圖31D所示，於支撐體113上載置半導體晶片3。藉此由支撐體113支撐半導體晶片3。
且，例如支撐體113為鉛焊錫之情況，在340℃之溫度條件下進行30 sec之熱處理，藉此如圖31E所示，熔融支撐體113，並藉由其表面張力及濡濕性，使支撐體113在形成有薄膜108之範圍內擴散。藉此可藉由熔融之支撐體113(焊錫接合劑109)填埋半導體晶片3與島狀物5之對向部分之間隙，從而達成半導體晶片3與島狀物5之接合。又，此時，助焊劑114一面洗淨半導體晶片3之下面(金屬膜115之表面)及島狀物5之上面，一面在半導體晶片3之側方凝聚固化，成為固化助焊劑110。
其後，於半導體晶片3與引腳6之間架設接合導線15，以僅使島狀物5及引腳6之背面露出的方式形成樹脂封裝4，藉此獲得圖28~30所示之半導體裝置1。
如上所示，熱處理時，藉由焊錫所具有之表面張力及濡濕性，使熔融之焊錫於半導體晶片3與島狀物5之間擴散。因此，與將半導體晶片3與島狀物5接合所使用糊狀之接著劑之方法不同，在將半導體晶片3對島狀物5接合時，無需對半導體晶片3施加負載。不對半導體晶片3施加負載，藉此可防止因該負載所引起之焊錫之擴散。又，根據半導體晶片3之尺寸而變更支撐體113之大小、形狀及個數，藉此無論半導體晶片3之尺寸為何，均不會產生從半導體晶片3與島狀物5之間大幅溢出之焊錫，從而可接合半導體晶片3與島狀物5。因此，即使為小尺寸之半導體晶片3，亦不會產生因焊錫之擴散所引起之各種問題，從而可達成對島狀物5之晶片接合。
支撐體113係配置於包含銀之薄膜108上。由於焊錫對銀之濡濕性較高，故當熱處理時使支撐體113熔融，則該熔融之支撐體113會在形成有包含銀之薄膜108之範圍內擴散。因此，藉由形成包含銀之薄膜108，可控制支撐體113之擴散，從而可確實防止焊錫之擴散所引起之各種問題產生。
又，於島狀物5形成從其上面往下挖之凹部107，將支撐體113配置於凹部107內。藉此可使支撐體113穩定配置於島狀物5上。
又，由於對支撐體113塗布助焊劑114，故可防止支撐體113之表面被氧化，且可提高熱處理時之支撐體113(焊錫)之濡濕性。又，由於半導體晶片3及島狀物5之與助焊劑114之接觸部分係利用助焊劑114之作用而被洗淨，故可進一步提高半導體晶片3與島狀物5之接著性。
圖32係顯示島狀物及支撐體之其他之構成之立體圖。
圖32所示之島狀物121可取代圖28所示之島狀物5而使用。
島狀物121成俯視四角形狀。於島狀物121形成有從其上面往下挖成半球狀之3個凹部122。各凹部122係以使連結該等之線之內側成三角形的方式，相互隔以間隔而配置。
在島狀物121之上面、俯視時包含形成有凹部122之部分之區域，形成有包含銀之薄膜123。具體而言，薄膜123在於島狀物121上接合有半導體晶片3(參照圖28)的狀態下，形成為與島狀物121之與半導體晶片3之對向部分大致相同之尺寸。又，薄膜123亦可形成於各凹部122之內面。
於凹部122內之薄膜123上配置支撐體124。支撐體124形成為具有與凹部122大致相同之直徑之球狀。
若將半導體晶片3載置於3個支撐體124上並進行熱處理，則支撐體124熔融，並藉由其表面張力及濡濕性，使支撐體124(焊錫)在形成有薄膜123之範圍內擴散。藉此，可藉由熔融之支撐體124填埋半導體晶片3與島狀物121之對向部分之間隙，從而達成半導體晶片3與島狀物121之接合。
圖33係顯示島狀物及支撐體之進而其他之構成之立體圖。
圖33所示之島狀物131可取代圖28所示之島狀物5而使用。
島狀物131成俯視四角形狀。於島狀物131之上面形成有包含銀之薄膜132，具體而言，薄膜132在於島狀物131上接合有半導體晶片3(參照圖28)的狀態下，形成為與島狀物131之與半導體晶片3之對向部分大致相同之尺寸。
於薄膜132上配置2個支撐體133。支撐體133形成為俯視細長板狀(帶狀)，且相互隔以間隔平行地延伸。
若將半導體晶片3載置於2個支撐體133上並進行熱處理，則支撐體133熔融，並藉由其表面張力及濡濕性，使支撐體133(焊錫)在形成有薄膜132之範圍內擴散。藉此，可藉由熔融之支撐體133填埋半導體晶片3與島狀物131之對向部分之間隙，從而達成半導體晶片3與島狀物131之接合。
又，作為半導體裝置1，雖示例有從樹脂封裝之背面露出引腳及島狀物之背面之所謂的表面安裝型半導體裝置，但本實施形態亦可應用於使引腳向樹脂封裝之側方延伸之樹脂密封型半導體裝置。即，本實施形態可廣泛適用於具有於島狀物上接合半導體晶片之構造之半導體裝置。
至此雖已詳細地說明本發明之實施形態，但該等僅為用於闡明本發明之技術內容之具體例，本發明不應限定於該等之具體例而作解釋，本發明之精神及範圍僅受附加之申請範圍之限定。
本申請案對應於2009年9月11日向日本專利廳提出之專利申請案第2009-210776號，與2009年9月16日向日本專利廳提出之專利申請案第2009-214925號，該等申請案之全部揭示內容以引用的方式併入本文中。
1．．．半導體裝置
2．．．導線架
3．．．半導體晶片
5．．．島狀物
6．．．引腳
14．．．焊墊
15．．．導線
16．．．球部
17．．．針腳部
107．．．凹部
108．．．薄膜
109．．．焊錫接合劑
110．．．固化助焊劑
113．．．支撐體
114．．．助焊劑
121．．．島狀物
122．．．凹部
123．．．薄膜
124．．．支撐體
131．．．島狀物
132．．．薄膜
133．．．支撐體
圖1A係本發明之第1實施形態之半導體裝置之平面圖；
圖1B係於圖1A適用變形例之圖；
圖2A係顯示從圖1A所示之半導體裝置省略半導體晶片、導線及焊錫接合劑之狀態之模式平面圖；
圖2B係於圖2A適用變形例之圖；
圖3係以切斷線III-III切斷圖1A所示之半導體裝置時之模式剖面圖；
圖4係圖1A所示之切斷線IV-IV之半導體裝置之模式剖面圖；
圖5A係顯示圖1A所示之半導體裝置之製造步驟之模式剖面圖；
圖5B係顯示圖5A之下一個步驟之模式剖面圖；
圖5C係顯示圖5B之下一個步驟之模式剖面圖；
圖5D係顯示圖5C之下一個步驟之模式剖面圖；
圖5E係顯示圖5D之下一個步驟之模式剖面圖；
圖6係顯示島狀物及支撐體之其他構成之立體圖；
圖7係顯示島狀物及支撐體之進而其他之構成之立體圖；
圖8係顯示實施例1所使用之焊針之前端形狀之圖解剖面圖；
圖9係在實施例1中所獲得之針腳部之附近之SEM圖像(其1)；
圖10係在實施例1中所獲得之針腳部之附近之SEM圖像(其2)；
圖11係在實施例1中所獲得之針腳部之附近之SEM圖像(其3)；
圖12係顯示實施例2所使用之焊針之前端形狀之圖解剖面圖；
圖13係在實施例2中所獲得之針腳部之附近之SEM圖像(其1)；
圖14係在實施例2中所獲得之針腳部之附近之SEM圖像(其2)；
圖15係顯示比較例所使用之焊針之前端形狀之圖解剖面圖；
圖16係在比較例中所獲得之針腳部之附近之SEM圖像；
圖17係本發明之第2實施形態之半導體裝置之平面圖；
圖18係圖17所示之切斷線A-A之半導體裝置之模式剖面圖；
圖19係顯示實施例1所使用之焊針之前端形狀之圖解剖面圖；
圖20係在實施例1中所獲得之針腳部之附近之SEM圖像(其1)；
圖21係在實施例1中所獲得之針腳部之附近之SEM圖像(其2)；
圖22係在實施例1中所獲得之針腳部之附近之SEM圖像(其3)；
圖23係顯示實施例2所使用之焊針之前端形狀之圖解剖面圖；
圖24係在實施例2中所獲得之針腳部之附近之SEM圖像(其1)；
圖25係在實施例2中所獲得之針腳部之附近之SEM圖像(其2)；
圖26係顯示比較例所使用之焊針之前端形狀之圖解剖面圖；
圖27係在比較例中所獲得之針腳部之附近之SEM圖像；
圖28係本發明之第3實施形態之半導體裝置之模式平面圖；
圖29係顯示從圖28所示之半導體裝置省略半導體晶片、導線及焊錫接合劑之狀態之模式平面圖；
圖30係以切斷線B-B切斷圖28所示之半導體裝置時之模式剖面圖；
圖31A係顯示圖28所示之半導體裝置之製造步驟之模式剖面圖；
圖31B係顯示圖31A之下一個步驟之模式剖面圖；
圖31C係顯示圖31B之下一個步驟之模式剖面圖；
圖31D係顯示圖31C之下一個步驟之模式剖面圖；
圖31E係顯示圖31D之下一個步驟之模式剖面圖；
圖32係顯示島狀物及支撐體之其他之構成之立體圖；
圖33係顯示島狀物及支撐體之進而其他之構成之立體圖；及
圖34係藉由逆向接合架設導線之半導體裝置之模式側視圖。
2．．．導線架
3．．．半導體晶片
5．．．島狀物
6．．．引腳
14．．．焊墊
15．．．導線
16．．．球部
17．．．針腳部

Claims (25)

  1. 一種半導體裝置，其包含：半導體晶片；配置於上述半導體晶片之側方之複數的引腳(lead)；導線，其一端及另一端分別接合於上述半導體晶片及上述引腳；於上面接合上述半導體晶片之島狀物；晶片接合物質，其介存於上述半導體晶片與上述島狀物之間，使上述半導體晶片與上述島狀物接合；及樹脂封裝，其形成為俯視之四角形狀，而封裝上述島狀物及上述引腳；俯視時，上述島狀物係形成為具有相對於上述樹脂封裝之各邊而傾斜之4邊的四角形狀；俯視時，上述引腳係於上述樹脂封裝之四個角落之各者各配置一個，各上述引腳具有與上述島狀物之4邊中最接近該引腳之一者相對向之第1邊。
  2. 如請求項1之半導體裝置，其中上述島狀物包含：於俯視時，自上述島狀物之4個角部之各個朝向上述樹脂封裝之各邊之中央延伸之垂吊部。
  3. 如請求項1之半導體裝置，其中上述引腳中，於上述樹脂封裝之背面所配置之下面係於俯視時，由上述第1邊、於上述樹脂封裝之一邊的內側而與該邊平行地設置之第2邊、與上述樹脂封裝之另 一致而設置之第3邊、與上述第1邊及上述第2邊相連之第4邊、及與上述第1邊及上述第3邊相連之第5邊所構成之五角形狀。
  4. 如請求項1之半導體裝置，其中上述導線係於上述半導體晶片及上述引腳上分別具有球部及側視為楔狀之針腳部。
  5. 如請求項1之半導體裝置，其中上述導線對上述引腳之進入角度為50°以上。
  6. 如請求項5之半導體裝置，其中上述針腳部之長度為33μm以上。
  7. 如請求項5之半導體裝置，其中上述針腳部之上面與上述引腳之上面所成之角度為15°以上。
  8. 如請求項7之半導體裝置，其中上述針腳部之長度為33μm以上。
  9. 一種半導體裝置，其包含：半導體晶片；配置於上述半導體晶片之側方之引腳；及導線，其一端及另一端分別接合於上述半導體晶片及上述引腳，且於上述半導體晶片及上述引腳上分別具有球部及側視楔狀之針腳部；且上述導線之長度為400μm以下，上述半導體晶片之上述球部之接合部分與上述引腳之上述針腳部之接合部分的高低差為200μm以上， 上述針腳部之長度為33μm以上。
  10. 一種半導體裝置，其包含：半導體晶片；配置於上述半導體晶片之側方之引腳；及導線，其一端及另一端分別接合於上述半導體晶片及上述引腳，且於上述半導體晶片及上述引腳上分別具有球部及側視楔狀之針腳部；且上述導線之長度為400μm以下，上述半導體晶片之上述球部之接合部分與上述引腳之上述針腳部之接合部分的高低差為200μm以上，上述針腳部之上面與上述引腳之上面所成之角度為15°以上。
  11. 如請求項10之半導體裝置，其中上述針腳部之長度為33μm以上。
  12. 如請求項1至8中任一項之半導體裝置，其中於上述晶片接合物質附著有助焊劑(flux)。
  13. 如請求項12之半導體裝置，其於上述島狀物形成有從其上面往下挖之凹部。
  14. 如請求項12之半導體裝置，其中上述島狀物為俯視四角形狀，且於上述島狀物之上面，以分別沿著四角形狀之上述島狀物所對向之2邊延伸的方式，形成有往下挖之1對槽狀凹部。
  15. 如請求項13之半導體裝置，其中上述凹部為剖面半圓形 狀。
  16. 如請求項13之半導體裝置，其中上述凹部為半球狀。
  17. 一種半導體裝置之製造方法，其包含：支撐體配置步驟，於島狀物上配置包含固體之焊錫(solder)之支撐體；晶片支撐步驟，在上述支撐體配置步驟後，於上述支撐體上載置半導體晶片，使上述支撐體支撐上述半導體晶片；及接合步驟，在上述晶片載置步驟後，藉由熱處理，使上述支撐體熔融而接合上述島狀物與上述半導體晶片。
  18. 如請求項17之半導體裝置之製造方法，其於上述支撐體配置步驟之前，進而包含於上述島狀物上形成包含銀之薄膜之步驟，且在上述支撐體配置步驟中，於上述薄膜上配置上述支撐體。
  19. 如請求項17或18之半導體裝置之製造方法，其中於上述島狀物形成有從其上面往下挖之凹部，且在上述支撐體配置步驟中，上述支撐體配置於上述凹部內。
  20. 如請求項17之半導體裝置，其於上述支撐體配置步驟後、上述晶片支撐步驟之前，進而包含於上述支撐體塗布助焊劑之助焊劑塗布步驟。
  21. 一種半導體裝置，其包含：半導體晶片； 於上面接合上述半導體晶片之島狀物；及焊錫接合劑，其包含焊錫，且介存於上述半導體晶片與上述島狀物之間，使上述半導體晶片與上述島狀物接合；且於上述焊錫接合劑上附著有助焊劑。
  22. 如請求項21之半導體裝置，其於上述島狀物形成有從其上面往下挖之凹部。
  23. 如請求項21之半導體裝置，其中上述島狀物為俯視四角形狀，且於上述島狀物之上面，以分別沿著四角形狀之上述島狀物所對向之2邊延伸的方式，形成有往下挖之一對槽狀凹部。
  24. 如請求項22或23之半導體裝置，其中上述凹部為剖面半圓形狀。
  25. 如請求項22之半導體裝置，其中上述凹部為半球狀。
TW099130820A 2009-09-11 2010-09-10 半導體裝置及其製造方法 TWI573235B (zh)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5464825B2 (ja) * 2008-07-23 2014-04-09 ローム株式会社 Ｌｅｄモジュール
JP6002461B2 (ja) * 2011-08-26 2016-10-05 ローム株式会社 半導体装置および電子デバイス
US20130093072A1 (en) * 2011-10-13 2013-04-18 Stmicroelectronics Pte Ltd. Leadframe pad design with enhanced robustness to die crack failure
KR101884234B1 (ko) * 2011-10-24 2018-08-30 엘지이노텍 주식회사 스테핑 모터의 피드백 루프제어 구조
JP6825660B2 (ja) * 2013-07-31 2021-02-03 日亜化学工業株式会社 リードフレーム、樹脂付きリードフレーム、樹脂パッケージ、発光装置及び樹脂パッケージの製造方法
US9269690B2 (en) * 2013-12-06 2016-02-23 Nxp B.V. Packaged semiconductor device with interior polygonal pads
JP6986385B2 (ja) * 2016-08-22 2021-12-22 ローム株式会社 半導体装置、半導体装置の実装構造

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6131799A (en) * 1998-01-15 2000-10-17 Esec Sa Method of making wire connections of predetermined shape

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5521106A (en) * 1978-07-31 1980-02-15 Nec Home Electronics Ltd Method of forming ohmic electrode
JPS5596666A (en) * 1979-01-18 1980-07-23 Mitsubishi Electric Corp Method of fabricating semiconductor device substrate
JPS5615074U (zh) * 1979-07-13 1981-02-09
JPS5615074A (en) 1979-07-19 1981-02-13 Pioneer Electronic Corp Semiconductor device
US4415115A (en) * 1981-06-08 1983-11-15 Motorola, Inc. Bonding means and method
JPS61168927A (ja) * 1985-01-22 1986-07-30 Toshiba Corp ハイブリツド集積回路装置
JPH0372641A (ja) * 1989-05-09 1991-03-27 Citizen Watch Co Ltd Ｉｃ実装構造及びその実装方法
JPH0364033A (ja) * 1989-08-02 1991-03-19 Hitachi Ltd 半導体装置およびその製造に用いるリードフレーム
JPH04155854A (ja) * 1990-10-19 1992-05-28 Hitachi Ltd 半導体集積回路装置およびそれに用いるリードフレーム
CH686325A5 (de) * 1992-11-27 1996-02-29 Esec Sempac Sa Elektronikmodul und Chip-Karte.
JP2823454B2 (ja) * 1992-12-03 1998-11-11 株式会社東芝 ワイヤボンディング装置
JP2536431B2 (ja) 1993-09-30 1996-09-18 日本電気株式会社 半導体装置
US5421503A (en) * 1994-08-24 1995-06-06 Kulicke And Soffa Investments, Inc. Fine pitch capillary bonding tool
JPH0992776A (ja) * 1995-09-28 1997-04-04 Mitsubishi Electric Corp リードフレームおよび半導体装置
TW335526B (en) * 1996-07-15 1998-07-01 Matsushita Electron Co Ltd A semiconductor and the manufacturing method
US5907769A (en) * 1996-12-30 1999-05-25 Micron Technology, Inc. Leads under chip in conventional IC package
JPH1167809A (ja) * 1997-08-26 1999-03-09 Sanyo Electric Co Ltd 半導体装置
JPH11111750A (ja) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd 半導体装置
JP2000091372A (ja) * 1998-09-11 2000-03-31 Matsushita Electronics Industry Corp 電子部品及びそのワイヤボンディングに使用するキャピラリ
JP2001230360A (ja) * 2000-02-18 2001-08-24 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3802821B2 (ja) 2002-02-22 2006-07-26 新日本無線株式会社 電子部品のリード切断方法
JP2004207292A (ja) 2002-12-24 2004-07-22 Seiko Epson Corp ワイヤボンディング方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP4186055B2 (ja) 2003-04-17 2008-11-26 ソニー株式会社 電子部品装置及び電子部品の製造方法
JP2007073763A (ja) * 2005-09-07 2007-03-22 Renesas Technology Corp 半導体装置およびその製造方法
JP4980600B2 (ja) * 2005-09-27 2012-07-18 旭化成エレクトロニクス株式会社 磁気センサ
JP4738983B2 (ja) * 2005-11-08 2011-08-03 ローム株式会社 半導体装置
JP2008041999A (ja) 2006-08-08 2008-02-21 Nec Electronics Corp 半導体装置およびその製造方法
KR100888885B1 (ko) * 2007-04-19 2009-03-17 삼성전자주식회사 리드프레임 및 이를 갖는 반도체 장치
JP2008294172A (ja) * 2007-05-24 2008-12-04 Panasonic Corp リードフレームおよび半導体装置ならびに半導体装置の製造方法
TWI506710B (zh) * 2009-09-09 2015-11-01 Renesas Electronics Corp 半導體裝置之製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6131799A (en) * 1998-01-15 2000-10-17 Esec Sa Method of making wire connections of predetermined shape

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