TWI506710B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TWI506710B
TWI506710B TW099122044A TW99122044A TWI506710B TW I506710 B TWI506710 B TW I506710B TW 099122044 A TW099122044 A TW 099122044A TW 99122044 A TW99122044 A TW 99122044A TW I506710 B TWI506710 B TW I506710B
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Taiwan
Prior art keywords
wire
capillary
bonding
height
semiconductor device
Prior art date
Application number
TW099122044A
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English (en)
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TW201130062A (en
Inventor
Yasuki Takata
Kaori Sumitomo
Hiroshi Horibe
Hideyuki Arakawa
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Renesas Electronics Corp
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Priority claimed from JP2009207952A external-priority patent/JP5586901B2/ja
Priority claimed from JP2010124207A external-priority patent/JP5444125B2/ja
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW201130062A publication Critical patent/TW201130062A/zh
Application granted granted Critical
Publication of TWI506710B publication Critical patent/TWI506710B/zh

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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/002Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
    • B23K20/004Wire welding
    • B23K20/005Capillary welding
    • B23K20/007Ball bonding
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Description

半導體裝置之製造方法
本發明係關於一種半導體裝置之製造技術及半導體裝置,特別是關於一種對打線接合步驟中導線之接合強度的提高適用而且有效的技術。
於例如日本特開2000-91372號公報(專利文獻1)中記載有於打線接合中,將導線楔接於引線的表面時,於前端的端緣周圍使用具有曲面狀第1壓下面與以環狀形成於其周圍之第2壓下面之毛細管,進而增大壓下量而於毛細管上形成扁平部而增強對引線表面的接合力之技術。
[先前技術文獻] [專利文獻]
專利文獻1:日本特開2000-91372號公報
於利用金屬製的導線,電性連接半導體晶片的電極墊與引線框架的內引線之打線接合中,作為其導線的材料主要使用金。但,因近年來金的價格高漲,而謀求一種代替金的材料,作為較金價格低的導線材料,銅已為人所知。
關於打線接合中之銅線的應用,不只是成本的降低化,其較金線導電率高,在電氣特性面亦較佳才是其理由。
在打線接合的引線側(2nd側)的接合之針腳式接合中,係利用溫度、荷重、超音波進行接合,但此時如圖16的比較例所示,與接合併用的是賦予機械性振幅動作S以補針腳式接合之不足。
本發明之發明人就前述針腳式接合進行了研討。
於針腳式接合中,在導線到達引腳之後,於此一位置僅進行對導線的荷重賦予(以下亦將該動作稱為「荷重控制」)。即,於針腳式接合中,藉由毛細管的引導,導線到達引腳之後,毛細管止於其位置,並對於導線賦予預先設定的特定荷重與超音波而進行接合。
從而,在導線是金等柔軟材料之情形下,雖可較大地採取針腳式接合之接合餘裕,而可充分確保接合強度,但會有金的成本較高之問題。
另一方面,在使用銅線之情形下,因銅線較金線容易氧化,而必須破壞其表面的氧化被覆膜,故需要對銅線賦予比較大的荷重或超音波。再者,相較於金線為較硬材質的銅線相較於金線其接合力弱,且原本接合餘裕較少。從而,若為獲得充分的接合強度,而賦予較大的荷重或超音波與前述機械性振幅動作S,則如圖16所示,針腳部20的厚度會變得過薄而發生斷線之問題。
另,在前述專利文獻1(日本特開2000-91372號公報)中,並無關於針腳式接合時的導線接合部之導線高度控制(厚壁控制)的記載,即使使用於前述專利文獻1所記載的打線接合技術,亦無法進行針腳式接合時的導線接合部之導線高度控制(厚壁控制)。
本發明係鑒於上述課題而完成者,其目的在於提供一種可確保針腳式接合的接合強度而謀求其接合可靠性提高之技術。
又,本發明之其他目的在於提供一種可謀求打線接合的成本降低化之技術。
本發明之前述及其他目的及新穎特徵,可由本說明書之敘述及附圖獲得深一層之瞭解。
本發明所揭示之發明中,代表性者之概要的簡單說明係如下所示。
根據代表性實施形態之半導體裝置之製造方法包含:(a)準備具備搭載半導體晶片之晶片搭載部與配置於前述晶片搭載部周圍之複數個引線的引線框架之步驟;(b)於前述引線框架的前述晶片搭載部搭載前述半導體晶片之步驟;及(c)藉由毛細管的引導以導線連接前述半導體晶片的電極墊與對應於前述電極墊之前述引線之步驟;且,前述(c)步驟包含在將前述導線連接於前述引線時,於自前述導線接觸前述引線之第1地點至前述毛細管接觸前述引線之第2地點之間,控制前述毛細管的高度,以使前述毛細管階段性押壓前述導線之高度控制步驟。
又,根據代表性的實施形態之其他半導體裝置之製造方法包含:(a)準備具備搭載半導體晶片之晶片搭載部與配置於前述晶片搭載部周圍之複數個接合引線的配線基板之步驟;(b)於前述配線基板的前述晶片搭載部搭載前述半導體晶片之步驟;及(c)藉由毛細管的引導以導線連接前述半導 體晶片的電極墊與對應於前述電極墊之前述引線之步驟;且,前述(c)步驟包含在將前述導線連接於前述接合引線時,於自前述導線接觸前述接合引線之第1地點至前述毛細管接觸前述接合引線之第2地點之間,控制前述毛細管的高度,以使前述毛細管階段性押壓前述導線之高度控制步驟。
再者,根據代表性實施形態之其他半導體裝置之製造方法包含:(a)準備具備搭載半導體晶片之晶片搭載部與配置於前述晶片搭載部周圍之複數個引線的引線框架之步驟;(b)於前述引線框架的前述晶片搭載部搭載前述半導體晶片之步驟;及(c)藉由毛細管的引導以導線連接前述半導體晶片的電極墊與對應於前述電極墊之前述引線之步驟;且,前述(c)步驟包含:在將前述導線連接於前述引線時,於自前述導線接觸前述引線之第1地點至前述毛細管接觸前述引線之第2地點之間,控制前述毛細管的高度,以使前述毛細管階段性押壓前述導線之高度控制步驟;及在前述高度控制步驟之後,自前述毛細管對前述導線賦予荷重之荷重控制步驟;於前述高度控制步驟中對於前述導線施加第1超音波,於前述荷重控制步驟中對於前述導線施加較前述第1超音波大的第2超音波者。
又,根據代表性實施形態之半導體裝置係為使用毛細管經打線接合組裝而成,其包含:搭載有半導體晶片之晶片搭載部;配置於前述晶片搭載部的周圍之複數個引線;及將形成於前述半導體晶片上之複數個電極墊與分別對應於 前述複數個電極墊之前述複數個引線電性連接的複數個導線;且於前述複數個導線的與前述複數個引線各自之導線接合部具有較前述毛細管的表面與頸側面各自之延長線的交點之垂直方向的高度厚度更厚的厚壁部分;於前述厚壁部分的下部形成有前述導線與前述引線的接合區域者。
再者,根據代表性實施形態之其他半導體裝置係為使用毛細管經打線接合組裝而成,其包含:搭載有半導體晶片之晶片搭載部;配置於前述晶片搭載部的周圍之複數個引線;及與分別對應形成於前述半導體晶片上之複數個電極墊與前述複數個電極墊之前述複數個引線電性連接之複數個導線;且於前述複數個導線的前述複數個引線之各自的導線接合部具有經施加第1尺寸的第1超音波而形成的第1接合區域,與經施加較前述第1尺寸大的第2尺寸之第2超音波而形成的第2接合區域者。
於本發明所揭示之發明中,由代表性者所獲得之效果簡單說明之,係如下所示。
可在打線接合的針腳式接合中確保充分的接合強度,而謀求針腳式接合的接合可靠性的提高。
因可在打線接合中採用銅線,故可謀求打線接合的成本之降低。
於以下實施形態中,除了特別必要時以外,原則上不重複同一或相同部分的說明。
再者,於以下實施形態中,為方便起見必要時乃分割成複數個部分或實施形態進行說明,但除特別明示之情形以外,其等並非是互無關係者,而是一者與其他者的一部分或全部變形例、詳細內容、補充說明等有關係。
又,於以下實施形態中,在提及要件之數量等(包含個數、數值、量、範圍等)之情形下,除特別明示之情形及原理上顯然限定於特定的數量之情形等以外,不應受特定數量之限制,可為特定之數量以上或以下。
又,於以下之實施形態中,其構成要件(亦包含要件步驟等)除特別明示之情形及原理上考量顯然是必須之情形以外,當然亦未必是一定必須者。
又,於以下實施形態中,針對構成要件提及「自A構成」、「由A構成」、「具有A」及「包含A」時,除特別明示只有該要件之意旨之情形等以外,亦不應排除其以外之要件。同樣,以下實施形態中,在提及構成要件等的形狀、位置關係等時,除特別明示之情形及原理上考量顯然並非如此之情形等以外,實質上應包含與其形狀等等近似或類似者等,該情況針對上述數值及範圍亦同。
以下,基於圖面詳細說明本發明之實施形態。另,於用以說明實施形態之全圖中,對具有同一機能之構件標注以同一符號,而省略其重複說明。
(實施形態1)
圖1係顯示本發明實施形態1之半導體裝置的構造之一例的平面圖,圖2係顯示沿著圖1所示之A-A線切斷之構造的 剖面圖。
本實施形態1的半導體裝置係為使用引線框架組裝的多引線,且係為樹脂密封型的半導體封裝體,於本實施形態1中作為前述半導體裝置的一例,係例舉如圖1所示之多引線QFP(Quad Flat Package,四側引線扁平封裝體)1進行說明。
就圖1、圖2所示之QFP 1之構成進行說明,其具有:形成有半導體積體電路之半導體晶片4;以放射狀配置於半導體晶片4的周圍之複數個內引線(引線)2a;與內引線2a形成為一體之複數個外引線2b;及將形成於半導體晶片4的主面4a上之作為表面電極之電極墊4c及對應其之內引線2a電性連接之導線5。
再者,QFP 1具有:介以銀膠等之晶粒接合材固定有半導體晶片4之作為晶片搭載部之接頭(亦稱為「晶粒墊」)2c;及藉由樹脂成形由密封用樹脂等形成,且密封半導體晶片4、接頭2c、複數個導線5及複數個內引線2a之密封體3。因係QFP 1,故與複數個內引線2a分別形成為一體之複數個外引線2b係自密封體3的4邊分別朝外部突出,各外引線2b係以鷗翼狀彎曲成形
此處,搭載於QFP 1上之半導體晶片4以窄墊節距設置有形成於其主面4a上之複數個電極墊4c,藉此,謀求多接腳化。
又,與半導體晶片4的複數個電極墊4c及分別對應之複數個內引線2a分別電性連接之複數個導線5,係由銅形成 之銅線。即,本實施形態1之QFP 1係於導線5中採用銅線而謀求低成本化。
再者,於QFP 1中在其組裝的打線接合之針腳式接合時(2nd接合時),係進行導線5的接合部之高度控制(針腳部5a(參照圖15)的厚壁控制)而組裝者。
即,在與內引線2a打線接合之時,如圖15所示進行導線5的針腳部5a之厚度控制而充分確保銅線(導線5)的接合強度者。
另,內引線2a、外引線2b及接頭2c係由例如銅合金等之薄板狀的構件形成,再者,密封體3係由例如熱硬化性的環氧樹脂系樹脂等形成,且係由樹脂成形所形成者。
接著,依圖3所示之流程圖說明本實施形態1之半導體裝置(QFP 1)之製造方法。
圖3係顯示圖1所示之半導體裝置的組裝程序順序之一例的製造流程圖,圖4係顯示於圖1所示之半導體裝置的組裝中所使用的引線框架的構造之一例的放大部分平面圖,圖5係顯示在圖1所示之半導體裝置的組裝之晶粒接合後的構造之一例的部分剖面圖,圖6係顯示在圖1所示之半導體裝置的組裝之打線接合後的構造之一例的部分剖面圖。又,圖7係顯示於圖1所示之半導體裝置的組裝之打線接合步驟中使用的打線機之主要部的構造之一例的構成方塊圖,圖8係顯示至使用圖7所示之打線機之打線接合之形成線弧的程序之一例的立體圖,圖9係顯示在使用圖7所示之打線機之打線接合之針腳式接合以後的程序之一例的立體圖。再 者,圖10係顯示自使用圖7所示之打線機之打線接合之1st接合至2nd接合之毛細管的軌跡之一例的動作圖,圖11係顯示利用圖7所示之打線機之打線接合之毛細管的高度位置、荷重及超音波的控制狀況之一例的控制圖,圖12係顯示在利用圖7所示之打線機之針腳式接合時的到達檢測時與高度控制時的構造之一例的放大部分剖面圖,圖13係顯示在利用圖7所示之打線機之針腳式接合時的荷重控制開始時與結束時的構造之一例的放大部分剖面圖。又,圖14係顯示在利用圖7所示之打線機之針腳式接合時的理想的毛細管之移動量的一例之放大部分剖面圖,圖15係顯示在利用圖7所示之打線機進行針腳式接合之時的針腳形狀的一例之放大部分剖面圖,圖16係顯示比較例的針腳形狀之放大部分剖面圖。再者,圖17係顯示在以圖15所示之實施形態1的針腳式接合形狀與圖16所示之比較例的針腳式接合形狀進行拉伸斷裂強度評價時的評價結果之一例的結果圖,圖18係顯示圖17的拉伸斷裂強度之評價結果的數值例之結果圖,圖19係顯示在圖1所示之半導體裝置的組裝之樹脂成形後的構造之一例的剖面圖,圖20係顯示在圖1所示之半導體裝置的組裝之切斷.成形後的構造之一例的部分剖面圖。
首先,進行圖3之步驟S1所示之引線框架準備。此處,準備作為圖4所示之引線框架的一例之矩陣框架2。於矩陣框架2上並排形成有複數個搭載半導體晶片4之器件區域2d,且於各自的器件區域2d中設置有複數個內引線(引 線)2a或外引線2b。
於本實施形態1中使用的圖4所示之矩陣框架2上,以複數行×複數列(例如,圖4中2行×2列)之矩陣配置形成有複數個用以形成1個QFP 1的區域之器件區域2d,於各器件區域2d中形成有1個接頭(晶粒墊)2c、複數個內引線2a及複數個外引線2b等。
又,矩陣框架2係為由例如銅合金等所形成的長方形的薄板材,接頭2c、複數個內引線2a及外引線2b形成為一體。於圖4所示之矩陣框架2中,X方向係為長方形的長度方向,Y方向係為長方形的寬度方向。
又,於矩陣框架2的寬度方向之兩端部的框部2e上,設置有複數個處理時定位用的長孔2g或引導用的鏈輪孔2f。
另,雖圖4所示之矩陣框架2的1個器件區域2d之內引線2a的支數與圖1所示之QFP 1之外引線2b的支數不同,但這是為了易於了解矩陣框架2的引線部分之形狀而顯示者,用以組裝QFP 1而使用的矩陣框架2的1個器件區域2d的內引線2a的支數當然與QFP 1的外引線2b的支數相同。
其後,進行圖3之步驟S2所示之晶粒接合。此處,於矩陣框架2的複數個器件區域2d的接頭(晶片搭載部)2c上,如圖5所示介以晶粒接合材搭載半導體晶片4。即,藉由前述晶粒接合材接合半導體晶片4的內面4b與接頭2c。
其後,進行圖3之步驟S3所示之打線接合。即,如圖6所示,藉由圖7所示之接合工具即毛細管6e的引導,以導線5電性連接半導體晶片4的主面4a之電極墊4c與對應其之內 引線2a。另,導線5係為銅線。
此處,茲就於步驟S3的打線接合步驟所使用的圖7所示之打線機6進行說明。
打線機6於其主要部具備有:進行打線接合之接合頭部6b;支撐接合頭部6b,且使接合頭部6b在XY方向移動之XY平台6a;及進行接合頭部6b的高度控制之高度控制部6c。
再者,於接合頭部6b設置有在打線接合時引導導線5之毛細管6e;與高度控制部6c連動,且組裝有毛細管6e之機臂6d;對導線5施加拉力之張緊器6h;及在切斷導線5時夾固導線5之夾持器6g等。
此處,使用圖8及圖9茲就本實施形態1之QFP 1的組裝中之打線接合的程序進行說明。另,於本實施形態1說明之打線接合係為球型接合。
首先,進行圖8之步驟S3-1所示之球形成。此處,將矩陣框架2配置於加熱臺6j上之後,以噴燈6i將由毛細管6e所引導之導線5的前端放電而形成球狀。
其後,於晶片側進行步驟S3-2所示之球型接合。於此處,賦予超音波或熱等而實施將球狀導線5的前端接合於半導體晶片4的電極墊4c上之1st接合。
其後,進行步驟S3-3所示之形成線弧。於此處,在藉由毛細管6e的引導形成導線5的弧形之後,將導線5配置於內引線2a上。
其後,於內引線側進行圖9的步驟S3-4所示之針腳式接 合。於此處,賦予超音波或熱等而實施利用毛細管6e的引導而將導線5接合於內引線2a上之2nd接合。
其後,進行步驟S3-5所示之末端切斷。於此處,在藉由夾持器6g夾固導線5之狀態下,藉由毛細管6e牽拉導線5而將導線5扯下。
其後,對於其他電極墊4c亦同樣進行步驟S3-1~步驟S3-5之動作,而結束步驟S3-6之步驟。
接著,茲就本實施形態1之打線接合之針腳式接合進行說明。
本實施形態1之針腳式接合係關於對於半導體晶片4的電極墊4c進行1st接合之後的朝內引線2a的2nd接合者。圖10係顯示自1st接合至2nd接合的毛細管6e之前端軌跡者,由此圖可知於針腳部、即2nd接合的部位,在導線5接觸於內引線2a之後,毛細管6e徐徐下降而接觸於內引線2a。
再者,圖11係顯示對於自1st接合至2nd接合之時間(t)之毛細管6e的高度位置、導線接合荷重及導線接合超音波的各自關係者。即,其為可知針腳部(2nd接合部)之相對時間(t)之毛細管6e的高度位置、荷重及超音波的關係之圖。
如圖11所示,本實施形態1之針腳式接合包含有在將導線5連接於內引線2a上之時,於自導線5接觸於內引線2a之第1地點V至毛細管6e接觸於內引線2a之第2地點W之間,控制毛細管6e的高度以使毛細管6e階段性押壓導線5之高度控制步驟。
即,其為在1st接合結束後,進行形成線弧,而後利用 毛細管6e的引導使導線5下降,在對於內引線2a進行2nd接合之時,進行毛細管6e的高度控制者。
此時,於2nd接合之針腳式接合中,將導線5接觸於內引線2a之地點作為第1地點V,進而使毛細管6e下降,將毛細管6e接觸於內引線2a之地點作為第2地點W,於自該第1地點V至第2地點W之間進行毛細管6e的高度控制。
於毛細管6e的高度控制中,係為一面監控毛細管6e的高度方向位置,一面自毛細管6e對於導線5施加荷重或超音波而押壓導線5,控制毛細管6e下降途中之毛細管6e的高度方向位置者。
另,作為毛細管6e的高度控制之具體的一例,係監控毛細管6e的前端部之高度,在毛細管6e的下降速度較預先所設定之設定值大之時,減小自毛細管6e賦予導線5之荷重的大小,在毛細管6e的下降速度較前述設定值小之時,增大自毛細管6e賦予導線5之荷重的大小。
即,於毛細管6e的高度控制步驟中,利用預先評價或模擬等預算出毛細管6e的下降速度(圖11之高度控制中的曲線之斜率)之設定值,並以此設定值為基準檢測毛細管6e的下降速度是較前述設定值大或小,一面予以反饋一面以儘量接近前述設定值之方式進行針腳式接合。
另,於毛細管6e的高度控制中,如圖11所示,與對於導線5賦予荷重之同時亦施加超音波,並於自第1地點V至第2地點W之間,控制毛細管6e的高度,以使毛細管6e階段性押壓導線5。或,控制毛細管6e的高度位置,以使導線5之 2nd接合部的導線接合部(圖15所示之導線5的針腳部5a)之厚度成為期望之厚度。
又,如圖11所示在高度控制後(到達第2地點W後)進行荷重控制。此處,在到達第2地點W後,自毛細管6e對導線5賦予荷重,且施加超音波。此時,於荷重控制步驟中,毛細管6e無須在水平方向上移動,於第2地點W對導線5賦予荷重與超音波而提高導線5與內引線2a的接合強度。
此處,茲使用圖12及圖13就高度控制與荷重控制中的毛細管6e之詳細動作進行說明。此時,作為一例,例舉導線5的直徑為30μm之情形進行說明。
如圖12的高度控制開始所示,自導線5接觸於內引線2a而檢測到達之時點(第1地點V)開始毛細管6e的高度控制。於此處,如前所述,將預先所算出之毛細管6e的下降速度之設定值作為基準,檢測毛細管6e的下降速度較前述設定值大或小,一面予以反饋一面以儘量接近前述設定值方式一面進行針腳式接合。
即,如圖12的高度控制途中所示,一面予以反饋一面進行毛細管6e的高度控制,而階段性(一點一點)地將毛細管6e壓入於導線5中。此時,藉由高度控制部6c進行機臂6d的高度方向及XY方向(水平方向)的驅動。
此處,高度控制之毛細管6e的高度方向之下降量(移動量)以與導線5的直徑相同為佳,且毛細管6e的XY方向(水平方向)之移動量亦與導線5的直徑相同為佳。
其後,進行圖13的高度控制結束/荷重控制開始。即, 當下降之毛細管6e的前端接觸內引線2a之時點(第2地點W)結束高度控制,且接下來開始荷重控制。另,在高度控制結束時點(荷重控制開始時點)之導線5的針腳部5a之厚壁大致係為0(零)。
而後,於荷重控制中,如前述不使毛細管6e移動,在止於第2地點W之狀態下自毛細管6e對導線5施加荷重與超音波。即,於毛細管6e的端緣部6f對導線5施加荷重與超音波。
其後,如圖13的荷重控制結束所示,以特定時間自毛細管6e對導線5施加荷重與超音波後結束接合。
此處,圖14係顯示毛細管6e的理想的高度控制之狀態的一例者,例如在導線5的直徑(E)為30μm之情形下,高度控制之毛細管6e的前端之水平方向的移動量(F)係為30μm,且,高度控制之毛細管6e的前端之高度方向的移動量(G)亦為30μm。此時。於高度控制中的毛細管6e的前述移動時間約為0.1秒。
另,在毛細管6e的高度控制之後所進行荷重控制之時間約為0.02秒。
接著,圖17及圖18係利用本實施形態1之毛細管6e的高度控制所形成的針腳部5a(圖15中,針腳部的厚壁較厚)與比較例之針腳部20(圖16中,針腳部的厚壁較薄)比較拉伸斷裂強度,並對於複數條銅線之導線5進行評價之結果者。根據圖17及圖18,顯示為不管是MAX(最大)、AVE(平均)、MIN(最小)之所有項中,以圖15所示之本實施形態1 之針腳部5a之拉伸斷裂強度之值較高,於針腳式接合中亦以其接合強度較高。
如上所示,依序進行打線接合,完成圖3之步驟S3所示之打線接合步驟。
在打線接合步驟完成後,進行圖3之步驟S4所示之樹脂成形。於此處,使用未圖示之樹脂成形模具將矩陣框架2的器件區域2d之圖19所示之接頭2c、半導體晶片4、複數個內引線2a及導線5利用密封用樹脂進行樹脂密封,而形成密封體3。另,前述密封用樹脂係為例如熱硬化性的環氧樹脂樹脂等。
其後,進行圖3之步驟S5所示之切斷.成形。此處,切斷矩陣框架2而個別片化成各封裝體單位。此時,如圖20所示,將自密封體3突出之複數個外引線2b的各者以彎曲成形成鷗翼狀而完成QFP1的組裝。
根據本實施形態1之半導體裝置之製造方法,於打線接合的2nd接合之針腳式接合中,藉由控制毛細管6e的前端高度,而可進行導線接合部的高度控制(針腳部5a的厚壁控制),可充分確保針腳部5a的厚度,且可於針腳部5a上形成無應力集中點之圓滑的形狀。
其結果,可於導線接合部(針腳部5a)確保充分的接合強度而謀求針腳式接合的導線5之接合可靠性的提高。
再者,因於針腳式接合中可確保針腳部5a的厚度,故於打線接合中可採用銅線,而可謀求打線接合的成本降低化。又,因可採用銅線,故可提高導線5的導電率。
又,因可進行針腳部5a的厚壁控制,故可令導線接合部(針腳部5a)的厚度成為期望之厚度。即,可令針腳部5a的厚度更厚,或亦可更薄。
又,因可進行打線接合的2nd接合之針腳部5a的厚壁控制,故作為導線5,在採用例如金線之時,即使在金線變為更細之情形下,亦可提高其導線接合部之接合強度。
接著,茲就本實施形態1之變形例進行說明。
圖21係顯示本發明之變形例之半導體裝置(BGA)之構造的一例之剖面圖,圖22係顯示於圖21所示之半導體裝置之組裝中使用的配線基板之構造的一例之平面圖。
圖21所示之半導體裝置之BGA(Ball Grid Array,球柵陣列)7,係為於BGA基板(配線基板)8的主面8a上具有介以樹脂接著劑材10等之晶粒接合材而搭載的半導體晶片4者,半導體晶片4的表面電極與BGA基板8的主面8a之接合引線8c係由複數個導線5電性連接。再者,半導體晶片4與複數個導線5於BGA基板8的主面8a上係利用由密封用樹脂形成的密封體3由樹脂所密封。
又,於BGA基板8的內面8b側以格柵狀並排設置有成為外部連接端子之複數個焊錫球11。
圖22係顯示於此種構造之BGA 7的組裝中使用的多片式基板(配線基板)9之構造者,並於其主面9d上以複數個矩陣排列形成有供組裝1個BGA 7之區域之器件區域9a。各自的器件區域9a係由切割線9b區劃,並於各器件區域9a形成有搭載半導體晶片4之區域之晶片搭載部9e。另,於多片式 基板9的主面9d之外周部形成有在基板的搬送等之際作為定位或引導用使用之複數個貫通孔9c。
於使用此種多片式基板9,且經打線接合而組裝之BGA 7中亦可藉由於打線接合的2nd接合之針腳式接合中控制毛細管6e的前端高度,而進行導線接合部之高度控制(針腳部5a的厚壁控制),可充分確保針腳部5a的厚度,且可於針腳部5a上形成無應力集中點之圓滑的形狀。
其結果,可於導線接合部(針腳部5a)確保充分的接合強度而謀求針腳式接合之導線5之接合可靠性的提高。
另,關於圖21所示之BGA 7的其他製造方法因與圖1所示之QFP 1的製造方法相同,故省略其重複說明。
又,關於利用圖21所示之BGA 7之製造方法所獲得之其他效果,因與利用圖1所示之QFP1之製造方法所獲得之其他效果相同,故省略其重複說明。
(實施形態2)
圖23係為顯示本發明實施形態2之半導體裝置之構造的一例之剖面圖,圖24係顯示自圖23所示之半導體裝置的組裝之A部的打線接合之1st接合後至2nd接合的毛細管軌跡之一例的動作圖,圖25係顯示圖24所示之打線接合之毛細管的高度、接合荷重及超音波的一例之時序圖。又,圖26係顯示於圖23所示之半導體裝置的組裝之打線接合中使用的毛細管的前端部之構造的一例之剖面圖,圖27係顯示圖26所示之A部的構造之一例的放大部分剖面圖,圖28係顯示在利用圖26所示之毛細管接合時的導線之狀態的一例之 部分剖面圖,圖29係顯示在圖28所示之導線接合時的針腳式接合形狀之一例的部分剖面圖,圖30係顯示圖29所示之導線接合部的針腳式接合形狀之一例的部分平面圖。再者,圖31係顯示在比較例的導線接合時之針腳式接合形狀的部分剖面圖,圖32係顯示圖31所示之針腳式接合形狀的部分平面圖。
本實施形態2將進一步詳細說明於實施形態1所說明之打線接合方法之毛細管6e的控制(高度控制+荷重控制),且係針對採用該毛細管6e的控制經打線接合所組裝之半導體裝置(QFP 1)的構造之一例進行說明者。
首先,圖23所示之本實施形態2的QFP 1係為與圖1及圖2所示之實施形態1的QFP 1完全相同之構造,並具有:形成有半導體積體電路之半導體晶片4;以放射狀配置於半導體晶片4的周圍之複數個內引線2a;與內引線2a形成為一體之複數個外引線2b;及電性連接形成於半導體晶片4的主面4a上之電極墊4c與對應其之內引線2a之複數個導線5。
再者,半導體晶片4、複數個內引線2a及複數個導線5係由密封體3被樹脂密封。又,自密封體3露出之複數個外引線2b各者係彎曲成形成鷗翼狀。
另,導線5雖例如為銅線,但亦可使用金線等。
接著,茲就本實施形態2之半導體裝置的組裝之打線接合之毛細管6e的動作與控制進行說明。
圖24顯示於圖23所示之QFP 1之A部的打線接合時之毛 細管6e的移動軌跡,主要顯示有自其1st接合(晶片側接合)結束後至2nd接合(引線側接合)地點的軌跡。圖24中,毛細管軌跡21係為本實施形態2的軌跡,毛細管軌跡22係為本發明人作為比較例所研討之一般性毛細管6e之軌跡。
又,圖24中,TP(Tip)係顯示毛細管6e自毛細管6e的環軌跡之頂點以高速下降而切換為定速之時點的毛細管6e的高度者,CA(Contact Angle,接觸角)顯示自2nd接合之前述TP到達內引線2a的接合面2h之時的毛細管6e的下降角度,再者,CO(Contact Offset,接觸偏移)顯示在毛細管6e到達內引線2a之接合面2h之後,使其原狀滑行之距離。
於比較例之毛細管軌跡22中,作為於2nd接合中之毛細管6e的下降角度之CA係為0°(度)。即,在2nd接合時,毛細管6e相對於內引線2a的接合面2h之到達點,係自略正上方下降而到達2nd接合地點。
相對於此,於本實施形態2之毛細管軌跡21中,CA係為例如為9°(度),此時之TP係為0.127mm(5mils)、CO係為0.0381mm(1.5mils)。即,於本實施形態2之毛細管軌跡21中,在2nd接合時,毛細管6e相對於內引線2a的接合面2h具有9°的下降角度並以定速斜向下降而到達2nd接合地點,其後,以0.0381mm原狀滑動。其係因在2nd接合之時,如於實施形態1所說明之於到達內引線2a之前進行毛細管6e的高度控制,且為進行該高度控制,在導線5即將要接觸內引線2a之前使毛細管6e以定速斜向下降,而自導線5接觸內引線2a之時點開始毛細管6e的高度控制。另, 關於毛細管6e的高度控制之控制方法係與於實施形態1所說明之控制方法相同。
再者,前述之CA、TP及CO的數值係為一例,並非限定於此等數值。
又,於本實施形態2之打線接合中亦在2nd接合時進行與於實施形態1所說明之毛細管6e的荷重控制相同的荷重控制。
即,如圖25之時序圖所示,於時間T1開始毛細管6e的斜向下降,且開始到達前超音波,且為第1大小的超音波之第1超音波的施加。此時,令前述第1超音波的振幅為第1振幅23,則在用以形成第1振幅23的打線機中的輸入值為例如60mA。
其後,將導線5接觸於內引線2a之時點設為T1A,則於時間T1A開始於實施形態1所說明之毛細管6e的高度控制。毛細管6e的高度控制係為控制毛細管6e的高度以使毛細管6e階段性押壓導線5者。
其後,將毛細管6e接觸於內引線2a的接合面2h之時點設為到達點T2,於該時間T2結束毛細管6e的高度控制。
即,進行毛細管6e的高度控制之時,對導線5施加第1振幅23的第1超音波。
其後,於時間T3開始毛細管6e的荷重控制。另,於荷重控制中亦施加超音波。於荷重控制中施加的超音波係為較第1超音波大的第2大小之第2超音波。令前述第2超音波的振幅為第2振幅24,則於用以形成第2振幅24的打線機中的 輸入值係為例如75mA。即,成為(第1振幅23的第1超音波)<(第2振幅24的第2超音波)之關係。
從而,於毛細管6e的高度控制步驟中,對於導線5施加第1振幅23的第1超音波,而於高度控制步驟後的前述荷重控制步驟中,對於導線5施加較第1振幅23(第1超音波)大的第2振幅24之第2超音波。
換言之,於毛細管6e的高度控制步驟中,施加較於荷重控制步驟施加之第2超音波為小的能量之第1超音波。
這是因為於本實施形態2之高度控制步驟中未對導線5賦予荷重,故若在未對導線5賦予荷重之狀態下施加較大的超音波,則因導線自身未被束縛而對導線自身有過度的超音波能量傳遞而容易引起斷線,故為避免發生其斷線,乃施加較小的能量(振幅)之超音波者。
另,本實施形態2之前述第1超音波的大小(第1大小)以例如為前述第2超音波大小(第2大小)的30~80%之程度為佳。此處,超音波的能量大小主要由振幅大小與其施加時間決定。
其後,於時間T4結束荷重控制,完成導線5與內引線2a的接合之2nd接合。
接著,茲就採用前述本實施形態2之打線接合的毛細管6e之控制方法所組裝之QFP 1之構造的特徵部分進行說明。
首先,茲使用圖26~圖28就毛細管6e的前端部之形狀進行說明。圖26及圖28所示之CD(Chamfer Diameter,倒角直徑)係為毛細管6e的最前端之開口孔的直徑,FA(Face Angle,面角)係為水平面Z與毛細管6e的表面6k形成的角度。又,OR(Outside Radius,外側半徑)係為形成連接毛細管6e的表面6k與頸側面6n之曲線部6q之圓的半徑,TD(Tip Diameter,尖端直徑)係為自圖28所示之水平面Z與毛細管6e的頸側面6n的延長線6p的交點Q所形成的毛細管外周方向的虛擬圓的直徑。
再者,圖27所示之高度H係顯示毛細管6e的表面6k與頸側面6n的各自延長線6m、6p的交點P之垂直方向Y的高度。
此處,在2nd接合中,於圖29與圖30顯示使用圖26~圖28所示形狀的毛細管6e並採用本實施形態2之毛細管6e的控制(圖24及圖25所示之毛細管6e的動作)進行打線接合時的針腳部(導線接合部)5a的構造。再者,於圖31與圖32顯示由本發明人所比較研討的根據圖24之比較例的毛細管軌跡22之動作進行2nd接合之時的針腳部20的構造。
圖31及圖32之比較例的針腳部20之長度t1係顯示到達2nd接合地點時的毛細管6e的下降角度之CA(Contact Angle,接觸角)為CA=0°(度)之情形的針腳部20的接合區域20a之導線環方向25的長度。又,將此時的針腳部20的厚度(MAX)設為t2。
此處,針腳部20的長度t1基於圖28所示之毛細管6e的形狀,係由t1=(TD-CD)/2-OR表示,再者針腳部20的厚度t2係由t2=t1×tan(FA)=t1(TD-CD)/2-t1×OR表示。
又,針腳部20的厚度t2與圖27所示之交點P的垂直方向Y 的高度H相同。
另,於圖31之比較例的針腳部20中,雖其粗實線部顯示有接合區域20a,但因於針腳部20由毛細管6e自上方押壓,故外觀上雖看似接合,但實際存在有未接合之非接合區域20b。
另一方面,採用本實施形態2之毛細管6e的控制進行打線接合時的圖29之針腳部(導線接合部)5a的接合區域5b(粗實線部)的長度可以CO(Contact Offset,接觸偏移)+t1+α表示。即,針腳部5a係為包含(CO+t1+α)與厚壁部分5e之導線接合部分。此處,由前述α所示之區域係為在毛細管6e到達前藉由超音波(第1大小的第1超音波)接合之區域。換言之,由前述α所示之區域係為在毛細管6e到達前經高度控制並在水平方向接合增加之區域。
又,針腳部5a的厚度(MAX)可以β+t2表示。此處,由前述β所示之區域係為在毛細管6e到達前利用超音波(第1大小的第1超音波)於厚度方向上厚度增加之區域。換言之,由前述β所示之區域係為在毛細管6e到達前進行高度控制並於厚度方向增大接合之區域,係為圖29之針腳部5a的斜線部所示之厚壁部分5e。
從而,採用本實施形態2之毛細管6e的控制而進行打線接合所組裝的圖23所示的QFP 1之導線5的2nd接合部(圖29的針腳部5a)具有較圖28的毛細管6e之表面6k與頸側面6n各自之延長線6m、6p的交點P之垂直方向Y的高度H厚度更厚之圖29所示之厚壁部分5e,且於厚壁部分5e的下部形成 有導線5與內引線2a的接合區域5b的一部分(α部)。
又,於圖29所示之針腳部5a中,若將於毛細管6e的高度控制步驟施加第1大小的第1超音波而接合之區域設為圖30所示之第1接合區域5c,將於荷重控制步驟施加較第1大小為大的第2大小之第2超音波而接合之區域設為第2接合區域5d,則針腳部5a具有經施加第1超音波而形成的第1接合區域5c,及經施加第2超音波而形成的第2接合區域5d。
藉此,於圖29及圖30所示之本實施形態2的針腳部5a與圖31及圖32所示之比較例的針腳部20中,針腳部5a的接合區域5b較針腳部20的接合區域20a(粗實線部)接合面積大,且厚度(MAX)亦是針腳部5a較針腳部20厚。
即,於本實施形態2的QFP 1中,於導線5的2nd接合部之針腳部(導線接合部)5a具有厚壁部分5e,且於該厚壁部分5e的下部形成有導線5與內引線2a的接合區域5b的一部分(α部),藉此可充分確保針腳部5a的厚度,且可增加針腳部5a的接合區域5b的面積。
藉此,可於針腳部5a確保充分的接合強度而降低斷線,其結果,可謀求針腳式接合之導線5的接合可靠性的提高。
又,於本實施形態2之打線接合的2nd接合之毛細管6e的高度控制步驟中,施加較於荷重控制步驟所施加的第2超音波小的能量之第1超音波。
藉此,可減少超音波對導線自身之過度能量傳遞而導致斷線發生之情形。
即,因於毛細管6e的高度控制步驟中未對導線5賦予荷重,故若在未對導線5賦予荷重之狀態下施加較大的超音波,則因導線自身未受拘束因而會對導線自身傳遞超音波的過度能量而容易引起斷線。
因此,於本實施形態2中,於毛細管6e的高度控制步驟中,藉由施加較於荷重控制步驟所施加之第2超音波小的能量(振幅)之超音波(第1超音波),可降低斷線的發生。
其結果,可謀求針腳式接合之導線5的接合可靠性的提高。
又,因於針腳式接合可確保針腳部5a的厚度,故可於打線接合中採用銅線,而可謀求打線接合之成本降低化。又,因可採用銅線,故可提高導線5的導電率。
另,關於本實施形態2之半導體裝置的其他構造與其他製造方法,因與於實施形態1所說明之半導體裝置之構造及製造方法相同,故省略其重複說明。
又,關於根據本實施形態2之半導體裝置之製造方法及半導體裝置獲得之其他效果,因與於實施形態1所說明之效果亦相同,故省略其重複說明。
以上,雖基於發明的實施形態具體說明了由本發明人完成之發明,但本發明並非限定於前述發明之實施形態,在未脫離其主旨之範圍內當然可做各種變更。
例如,於前述實施形態1之QFP 1的製造方法中,雖就引線框架為矩陣框架2之情形進行了說明,但前述引線框架亦可為可形成複數個QFP 1的單列引線框架。又,於BGA 7 的製造方法中亦可採用單列的多片式基板9。
再者,只要前述半導體裝置是經打線接合而組裝的半導體封裝體,則亦可為QFP 1或BGA 7以外的QFN(Quad Flat Non-leaded Package,四方形扁平無引線封裝)或SOP(Small Outline Package,小尺寸封裝)、或LGA(Land Grid Array,平面柵格陣列)等,可適用於經打線接合而組裝的所有半導體封裝體。
又,於實施形態2中,雖針對於毛細管6e的高度控制步驟中未對毛細管6e賦予荷重之情形說明,但如於實施形態1所說明之於高度控制步驟中亦可對毛細管6e賦予荷重。
又,關於實施形態1與實施形態2,亦可為各自單獨之技術,或亦可為將兩者組合之技術。
又,於實施形態1及2的引線(內引線2a或接合引線8c)與導線5的接合部之針腳部5a中,於其接合區域5b形成有導線5與引線上的鍍敷物之接合層。
例如,在導線5為銅線,引線上的鍍敷物為Pd鍍敷物之情形下,前述接合層係為Pd-Cu,在銅線與銀鍍敷物之組合之情形下係為Ag-Cu,在金線與銀鍍敷物之組合之情形下係為Ag-Au,再者,於使用基板之半導體封裝體之情形下亦是於金線與金鍍敷物之組合之情形等形成Au-Au。
[產業上之可利用性]
本發明適用於經施行打線接合之電子裝置的組裝。
1‧‧‧QFP(半導體裝置)
2‧‧‧矩陣框架(引線框架)
2a‧‧‧內引線(引線)
2b‧‧‧外引線
2c‧‧‧接頭(晶片搭載部)
2d‧‧‧器件區域
2e‧‧‧框部
2f‧‧‧鏈輪孔
2g‧‧‧長孔
2h‧‧‧接合面
3‧‧‧密封體
4‧‧‧半導體晶片
4a‧‧‧主面
4b‧‧‧內面
4c‧‧‧電極墊
5‧‧‧導線
5a‧‧‧針腳部(導線接合部)
5b‧‧‧接合區域
5c‧‧‧第1接合區域
5d‧‧‧第2接合區域
5e‧‧‧厚壁部分
6‧‧‧打線機
6a‧‧‧XY平台
6b‧‧‧接合頭部
6c‧‧‧高度控制部
6d‧‧‧機臂
6e‧‧‧毛細管
6f‧‧‧端緣部
6g‧‧‧夾持器
6h‧‧‧張緊器
6i‧‧‧噴燈
6j‧‧‧加熱臺
6k‧‧‧表面
6m‧‧‧延長線
6n‧‧‧頸側面
6p‧‧‧延長線
6q‧‧‧曲線部
7‧‧‧BGA(半導體裝置)
8‧‧‧BGA基板(配線基板)
8a‧‧‧主面
8b‧‧‧內面
8c‧‧‧接合引線
9‧‧‧多片式基板(配線基板)
9a‧‧‧器件區域
9b‧‧‧切割線
9c‧‧‧貫通孔
9d‧‧‧主面
9e‧‧‧晶片搭載部
10‧‧‧樹脂接著劑材
11‧‧‧焊錫球
20‧‧‧針腳部
20a‧‧‧接合區域
20b‧‧‧非接合區域
21、22‧‧‧毛細管軌跡
23‧‧‧第1振幅
24‧‧‧第2振幅
25‧‧‧導線環方向
圖1係顯示本發明實施形態1的半導體裝置之構造的一例 之平面圖。
圖2係顯示沿著圖1所示之A-A線切斷之構造的剖面圖。
圖3係顯示圖1所示之半導體裝置的組裝程序的一例之製造流程圖。
圖4係顯示於圖1所示之半導體裝置的組裝中所使用的引線框架的構造之一例的放大部分平面圖。
圖5係顯示在圖1所示之半導體裝置的組裝之晶粒接合後的構造之一例的部分剖面圖。
圖6係顯示在圖1所示之半導體裝置的組裝之打線接合後的構造之一例的部分剖面圖。
圖7係顯示於圖1所示之半導體裝置的組裝之打線接合步驟中使用的打線機之主要部的構造之一例的構成方塊圖。
圖8係顯示至使用圖7所示之打線機之打線接合之形成線弧的程序之一例的立體圖。
圖9係顯示在使用圖7所示之打線機之打線接合之針腳式接合以後的程序之一例的立體圖。
圖10係顯示使用圖7所示之打線機之打線接合之自1st接合至2nd接合的毛細管的軌跡之一例的動作圖。
圖11係顯示利用圖7所示之打線機之打線接合之毛細管的高度位置與荷重及超音波的控制狀況之一例的控制圖。
圖12係顯示在利用圖7所示之打線機之針腳式接合時的到達檢測時與高度控制時的構造之一例的放大部分剖面圖。
圖13係顯示在利用圖7所示之打線機之針腳式接合時的 荷重控制開始時與結束時的構造之一例的放大部分剖面圖。
圖14係顯示在利用圖7所示之打線機之針腳式接合時的理想的毛細管之移動量的一例之放大部分剖面圖。
圖15係顯示在利用圖7所示之打線機進行針腳式接合之時的針腳式接合形狀的一例之放大部分剖面圖。
圖16係顯示比較例的針腳式接合形狀之放大部分剖面圖。
圖17係顯示在以圖15所示之實施形態1的針腳式接合形狀與圖16所示之比較例的針腳式接合形狀,進行拉伸斷裂強度評價時的評價結果之一例的結果圖。
圖18係顯示圖17的拉伸斷裂強度之評價結果的數值例之結果圖。
圖19係顯示在圖1所示之半導體裝置的組裝之樹脂成形後的構造之一例的剖面圖。
圖20係顯示在圖1所示之半導體裝置的組裝之切斷.成形後的構造之一例的部分剖面圖。
圖21係顯示本發明之變形例之半導體裝置(BGA)的構造之一例的剖面圖。
圖22係顯示於圖21所示之半導體裝置的組裝中使用的配線基板的構造之一例的平面圖。
圖23係顯示本發明實施形態2之半導體裝置的構造之一例的剖面圖。
圖24係顯示自圖23所示之半導體裝置的組裝之A部的打 線接合之1st接合後至2nd接合的毛細管軌跡之一例的動作圖。
圖25係顯示圖24所示之打線接合之毛細管的高度、接合荷重及超音波的一例之時序圖。
圖26係顯示於圖23所示之半導體裝置的組裝之打線接合中使用的毛細管的前端部之構造的一例之剖面圖。
圖27係顯示圖26所示之A部的構造之一例的放大部分剖面圖。
圖28係顯示在利用圖26所示之毛細管接合時的導線之狀態的一例之部分剖面圖。
圖29係顯示在圖28所示之導線接合時的針腳式接合形狀之一例的部分剖面圖。
圖30係顯示圖29所示之導線接合部的針腳式接合形狀之一例的部分平面圖。
圖31係顯示在比較例的導線接合時之針腳式接合形狀的部分剖面圖。
圖32係顯示圖31所示之針腳式接合形狀的部分平面圖。
2a‧‧‧內引腳
2h‧‧‧接合面
5‧‧‧導線
5a‧‧‧針腳部
5b‧‧‧接合區域
5e‧‧‧厚壁部分
6e‧‧‧毛細管
6k‧‧‧表面
6n‧‧‧頸側面
25‧‧‧導線環方向
t1‧‧‧時間
t2‧‧‧厚度
α‧‧‧接合區域的一部分
β‧‧‧接合增加之區域
CO‧‧‧接觸偏移

Claims (13)

  1. 一種半導體裝置之製造方法,其特徵為包含:(a)準備具備搭載半導體晶片之晶片搭載部與配置於前述晶片搭載部周圍之複數個引線(lead)的引線框架之步驟;(b)於前述引線框架的前述晶片搭載部搭載前述半導體晶片之步驟;及(c)藉由毛細管之引導,以導線連接前述半導體晶片的電極墊與對應於前述電極墊之前述引線之步驟;前述(c)步驟包含在將前述導線連接於前述引線時,於自前述導線接觸於前述引線之第1地點至前述毛細管經由前述導線之薄膜而接觸於前述引線之第2地點之間,以使前述毛細管一邊與自前述第1地點朝向前述第2地點之方向錯開一邊接近前述引線而押壓前述導線之方式控制前述毛細管之高度的高度控制步驟;且前述(c)步驟之前述高度控制步驟中監控前述毛細管的前端部之高度,並在前述毛細管的下降速度較設定值大之時,減小自前述毛細管賦予前述導線之荷重的大小,在前述毛細管的下降速度較前述設定值小之時,增大自前述毛細管賦予前述導線之荷重的大小。
  2. 如請求項1之半導體裝置之製造方法,其中前述導線係為銅線。
  3. 如請求項1之半導體裝置之製造方法,其中前述(c)步驟包含在前述高度控制步驟之後,自前述毛細管對前述導 線賦予荷重之荷重控制步驟。
  4. 如請求項2之半導體裝置之製造方法,其中於前述(c)步驟中對於前述導線施加超音波。
  5. 如請求項4之半導體裝置之製造方法,其中於前述高度控制步驟中的前述毛細管之高度方向的移動量與前述導線的直徑相同。
  6. 如請求項5之半導體裝置之製造方法,其中於前述高度控制步驟中的前述毛細管之水平方向的移動量與前述導線的直徑相同。
  7. 如請求項3之半導體裝置之製造方法,其中於前述荷重控制步驟中,前述毛細管未在水平方向移動而對前述導線賦予荷重。
  8. 一種半導體裝置之製造方法,其特徵為包含:(a)準備具備搭載半導體晶片之晶片搭載部與配置於前述晶片搭載部周圍之複數個接合引線的配線基板之步驟;(b)於前述配線基板之前述晶片搭載部搭載前述半導體晶片之步驟;及(c)藉由毛細管之引導,以導線連接前述半導體晶片的電極墊與對應於前述電極墊之前述接合引線之步驟;前述(c)步驟包含在將前述導線連接於前述接合引線時,於自前述導線接觸於前述接合引線之第1地點至前述毛細管經由前述導線之薄膜而接觸於前述接合引線之第2地點之間,以使前述毛細管一邊與自前述第1地點朝 向前述第2地點之方向錯開一邊接近前述接合引線而押壓前述導線之方式,控制前述毛細管之高度的高度控制步驟;且前述(c)步驟之前述高度控制步驟中,監控前述毛細管的前端部之高度,並在前述毛細管的下降速度較設定值大之時,減小自前述毛細管賦予前述導線之荷重的大小,在前述毛細管的下降速度較前述設定值小之時,增大自前述毛細管賦予前述導線之荷重的大小。
  9. 如請求項8之半導體裝置之製造方法,其中前述導線係為銅線。
  10. 如請求項8之半導體裝置之製造方法,其中前述(c)步驟包含在前述高度控制步驟之後,自前述毛細管對前述導線賦予荷重之荷重控制步驟。
  11. 一種半導體裝置之製造方法,其特徵為包含:(a)準備具備搭載半導體晶片之晶片搭載部與配置於前述晶片搭載部周圍之複數個引線的引線框架之步驟;(b)於前述引線框架的前述晶片搭載部搭載前述半導體晶片之步驟;及(c)藉由毛細管之引導以導線連接前述半導體晶片的電極墊與對應於前述電極墊之前述引線之步驟;且前述(c)步驟包含:(c1)在將前述導線連接於前述引線時,於自前述導線接觸於前述引線之第1地點至前述毛細管經由前述導線之薄膜而接觸於前述引線之第2地點之間,以使 前述毛細管一邊與自前述第1地點朝向前述第2地點之方向錯開一邊接近前述引線而押壓前述導線之方式,控制前述毛細管之高度的高度控制步驟;及(c2)在前述高度控制步驟之後,自前述毛細管對前述導線賦予荷重之荷重控制步驟;於前述高度控制步驟中對於前述導線施加第1超音波,於前述荷重控制步驟中對於前述導線施加較前述第1超音波大的第2超音波;前述高度控制步驟中,監控前述毛細管的前端部之高度,並在前述毛細管的下降速度較設定值大之時,減小自前述毛細管賦予前述導線之荷重的大小,在前述毛細管的下降速度較前述設定值小之時,增大自前述毛細管賦予前述導線之荷重的大小。
  12. 如請求項11之半導體裝置之製造方法,其中前述導線係為銅線。
  13. 如請求項12之半導體裝置之製造方法,其中前述第1超音波的大小係為前述第2超音波的大小之30~80%。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI573235B (zh) * 2009-09-11 2017-03-01 羅姆股份有限公司 半導體裝置及其製造方法
JP5618873B2 (ja) * 2011-03-15 2014-11-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5893266B2 (ja) * 2011-05-13 2016-03-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6002461B2 (ja) * 2011-08-26 2016-10-05 ローム株式会社 半導体装置および電子デバイス
JP5734217B2 (ja) * 2012-02-03 2015-06-17 ルネサスエレクトロニクス株式会社 半導体装置
US8643159B2 (en) 2012-04-09 2014-02-04 Freescale Semiconductor, Inc. Lead frame with grooved lead finger
JP6121692B2 (ja) * 2012-11-05 2017-04-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6279339B2 (ja) * 2014-02-07 2018-02-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TWI543284B (zh) * 2014-02-10 2016-07-21 新川股份有限公司 半導體裝置的製造方法以及打線裝置
US9881870B2 (en) 2015-12-30 2018-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
WO2018147164A1 (ja) * 2017-02-09 2018-08-16 株式会社新川 ワイヤボンディング装置
DE102017114771B4 (de) * 2017-06-29 2022-01-27 Pac Tech - Packaging Technologies Gmbh Verfahren und Vorrichtung zur Herstellung einer Drahtverbindung sowie Bauelementanordnung mit Drahtverbindung
JP7168780B2 (ja) * 2018-12-12 2022-11-09 ヘレウス マテリアルズ シンガポール ピーティーイー. リミテッド 電子部品の接触面を電気的に接続するプロセス
US11515284B2 (en) * 2020-07-14 2022-11-29 Semiconductor Components Industries, Llc Multi-segment wire-bond
US11597031B2 (en) * 2020-11-05 2023-03-07 Kulicke And Soffa Industries, Inc. Methods of operating a wire bonding machine, including methods of monitoring an accuracy of bond force on a wire bonding machine, and related methods
US20220199571A1 (en) * 2020-12-23 2022-06-23 Skyworks Solutions, Inc. Apparatus and methods for tool mark free stitch bonding

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091372A (ja) * 1998-09-11 2000-03-31 Matsushita Electronics Industry Corp 電子部品及びそのワイヤボンディングに使用するキャピラリ
TW200910490A (en) * 2007-08-31 2009-03-01 Shinkawa Kk Bonding device and bonding method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2770542B2 (ja) * 1990-03-14 1998-07-02 松下電器産業株式会社 ワイヤボンダーにおけるトランスデューサのus発振装置
JP2980447B2 (ja) * 1992-03-09 1999-11-22 三菱電機株式会社 半導体装置および半導体装置製造用キャピラリー
JP3230691B2 (ja) * 1992-03-31 2001-11-19 芝浦メカトロニクス株式会社 ワイヤボンディング方法
JPH07221141A (ja) * 1994-02-03 1995-08-18 Matsushita Electric Ind Co Ltd 超音波ワイヤボンディング装置
US7170149B2 (en) * 2001-04-13 2007-01-30 Yamaha Corporation Semiconductor device and package, and method of manufacture therefor
US7229906B2 (en) * 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
JP2005159267A (ja) * 2003-10-30 2005-06-16 Shinkawa Ltd 半導体装置及びワイヤボンディング方法
US20060011710A1 (en) * 2004-07-13 2006-01-19 Asm Technology Singapore Pte Ltd Formation of a wire bond with enhanced pull
CN101192588A (zh) * 2006-11-17 2008-06-04 飞思卡尔半导体公司 引线接合及其形成方法
KR100932680B1 (ko) * 2007-02-21 2009-12-21 가부시키가이샤 신가와 반도체 장치 및 와이어 본딩 방법
JP4361593B1 (ja) * 2008-10-21 2009-11-11 株式会社新川 ワイヤボンディング方法
JP4787374B2 (ja) * 2010-01-27 2011-10-05 株式会社新川 半導体装置の製造方法並びにワイヤボンディング装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091372A (ja) * 1998-09-11 2000-03-31 Matsushita Electronics Industry Corp 電子部品及びそのワイヤボンディングに使用するキャピラリ
TW200910490A (en) * 2007-08-31 2009-03-01 Shinkawa Kk Bonding device and bonding method

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