KR101119708B1 - 집적 회로 다이를 패키징하는 방법 - Google Patents

집적 회로 다이를 패키징하는 방법 Download PDF

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KR101119708B1
KR101119708B1 KR1020067011382A KR20067011382A KR101119708B1 KR 101119708 B1 KR101119708 B1 KR 101119708B1 KR 1020067011382 A KR1020067011382 A KR 1020067011382A KR 20067011382 A KR20067011382 A KR 20067011382A KR 101119708 B1 KR101119708 B1 KR 101119708B1
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balls
die
fixture
integrated circuit
masking tape
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KR1020067011382A
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KR20060126645A (ko
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헤이 밍 시우
와이 옹 초우
난 수
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프리스케일 세미컨덕터, 인크.
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Publication of KR20060126645A publication Critical patent/KR20060126645A/ko
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Abstract

본 발명은 집적 회로 다이(12)를 패키징하는 방법으로서, 픽스처(30) 내에 연질의 전도성 볼들(14)의 어레이를 형성하는 단계, 및 볼들의 대향면들을 평평하게 하는 단계를 포함한다. 평평하게 된 볼들은 픽스처에서 몰드 마스킹 테이프(mold masking tape)로 옮겨진다. IC 다이의 제1 면은 다이 부착 접착제(16)로 볼들에 부착되고, 다이 상의 와이어 본딩 패드(20)는 와이어(22)로 각각의 볼들에 직접 전기적으로 연결된다. 다이, 전기적 연결, 및 형성된 볼들의 상단부 상에 밀봉제(22)가 형성된다. 테이프는 제거되고, 인접한 밀봉된 다이들은 쏘 싱귤레이션(saw singulation)을 통해 분리된다. 결과는, 하단면에 볼들이 노출되어 있는 캡슐화된 IC이다.
집적 회로 다이, 몰드 마스킹 테이프, 밀봉제, 쏘 싱귤레이션

Description

집적 회로 다이를 패키징하는 방법{LAND GRID ARRAY PACKAGED DEVICE AND METHOD OF FORMING SAME}
본 발명은 집적 회로 패키징(intergrated circuit packaging)에 관한 것으로서, 더 상세하게는, LGA(Land Grid Array) 패키징된 장치를 제작하기 위한 향상된 공정에 관한 것이다.
집적 회로(IC) 다이(die)는 실리콘 웨이퍼와 같은 반도체 웨이퍼 상에 형성된 작은 장치이다. 리드프레임(leadframe)은 보통 웨이퍼에서 잘려진 IC 다이를 지지하는 패들(paddle)을 포함하는 금속 프레임이다. 리드프레임은 또한, 외부의 전기적 연결을 제공하는 리드 핑거(lead finger)를 갖는다. 즉, 다이는 다이 패들에 부착되고, 다이의 본딩 패드는 와이어 본드 또는 플립 칩 범프를 통해 리드 핑거에 연결되어 외부의 전기적 연결을 제공한다. 다이 및 와이어 본드 또는 플립 칩 범프를 보호 재료와 함께 캡슐화하면 패키지가 형성된다. 패키지 유형에 따라, 외부의 전기적 연결은 TSOP(Thin Small Outline Package)에서와 같이 있는 그대로 사용될 수도 있고, 추가적으로, BGA(Ball Grid Array)에 대해서는 구형의 땜납 볼(ball)들을 부착하는 등으로써 처리될 수도 있다. 이러한 단자점은 다이가 인쇄 회로 보드 상의 회로와 같은 다른 회로와 전기적으로 연결되게 해준다. 그러나, 화학 에칭 및 에칭백과 같은 단계가 요구되는 경우 리드프레임을 형성하고 장치를 패키징하는 것은 비용이 많이 들고 시간소모적일 수 있다.
사실상, 모든 전자 장치는 패키징된 IC를 사용하며, 더 작지만 더 강력한 장치에 대한 현재의 요구에 대해서, 패키지 크기를 줄이는 것이 매우 바람직하다. LGA 패키지는 BGA 패키지의 일부분인 땜납 볼들을 제거함으로써 높이를 줄인다. 패키징된 장치를 땜납 볼들로 인쇄 회로 보드(PCB)에 부착하는 것 대신에, LGA 패키지는 소켓을 통해 PCB에 부착된다. 최근, LGA 패키지는 인쇄 회로 보드에 도포되었던 납땜을 이용하여 리플로우-실장되었다. 신뢰도가 떨어지지 않고서 패키지 높이를 줄이는 것은, 셀룰러 폰, 디지털 카메라, PDA 등과 같은 다수의 전자 장치들에 있어서 LGA 패키지가 인기있게 만든다. 또한, LGA 패키지는 더 작은 패키지로 더 높은 핀 카운트(pin count)를 달성할 수 있다. 동시에, IC에서 패키지 패드로의 전기 경로는 짧아진다.
따라서, 패키징된 IC의 크기를 줄이는 방법을 갖는 것이 바람직하다. 또한, IC를 패키징하는 저비용의 방법을 제공하는 것이 바람직하다.
본 발명의 바람직한 실시예에 대한 다음의 상세한 설명은 첨부된 도면과 함께 읽을 때 가장 잘 이해될 것이다. 본 발명은 예로서 도시된 것이며, 유사한 참조번호들이 유사한 구성요소들을 가리키는 첨부 도면에 의해 제한되지 않는다.
도 1은 본 발명의 일 실시예에 따른 패키징된 집적 회로의 확대된 횡단면도.
도 2a는 본 발명의 일 실시예에 따른 전도성 볼들을 형성하기 위한 픽스처의 투시도.
도 2b는 도 2a의 픽스처 내에 배치된 전도성 볼들의 크게 확대된 도면.
도 3a는 도 2a의 픽스처 내의 전도성 볼들 상의 기계적 코이닝 공정을 도시하는 투시도.
도 3b는 기계적 코이닝 공정 이후의 도 2a의 픽스처 내의 전도성 볼들의 더 확대된 투시도.
도 4는 전도성 볼들을 도 2a의 픽스처로부터 접착 테이프로 옮기는 단계를 도시하는 투시도.
도 5a는 본 발명의 일 실시예에 따른 다이 부착 공정의 투시도.
도 5b 내지 도 5d는 대안적인 다이 부착 공정들을 도시하는 확대된 횡단면도.
도 6a는 복수의 전도성 볼들에 와이어 본딩된 도 5의 다이들 중 하나를 도시하는 크게 확대된 투시도.
도 6b는 도 6a의 와이어 본드들 중 하나의 크게 확대된 횡단면도.
도 7은 캡슐화 공정 이후의 전도성 볼들에 와이어 본딩된 다이들을 갖는 접착 테이프의 상단면의 투시도.
도 8은 본 발명의 일 실시예에 따른 테이프 탈착 단계 이후의 캡슐화된 장치의 하단면을 도시하는 투시도.
도 9는 본 발명에 따른 싱귤레이션(singulation) 공정 이후의 패키징된 장치의 하단의 투시도.
도 10은 본 발명에 따른 전도성 볼의 대안적인 실시예의 투시도.
첨부 도면과 관련하여 이하에 개시된 상세한 설명은 본 발명의 바람직한 실시예에 대한 설명으로서 의도되며, 본 발명이 실시될 수 있는 유일한 형태를 나타내는 것으로서 의도되지 않는다. 본 발명의 범주 및 취지에 포함되는 것으로 의도되는 다른 실시예들에 의해 동일하거나 동등한 기능이 수행될 수 있음을 이해해야 한다.
본 발명은 집적 회로 다이(die)를 패키징하는 방법으로서,
픽스처 내에 복수의 연질의 전도성 볼들을 형성하는 단계(볼들의 대향면들은 적어도 부분적으로 평평하게 되어 있음);
형성된 볼들을 픽스처로부터 몰드 마스킹 테이프(mold masking tape)로 옮기는 단계;
집적 회로 다이의 제1 면을 몰드 마스킹 테이블에 부착하는 단계(다이의 제2 면은 복수의 다이 본딩 패드들을 갖고, 다이는 형성된 볼들에 의해 둘러싸임);
다이를 둘러싸고 있는 형성된 볼들 하나 하나에 다이 본딩 패드들을 전기적으로 연결시키는 단계;
다이, 전기적 연결, 및 형성된 볼들의 상단부를 몰드 합성물로 캡슐화하는 단계; 및
볼들의 하단부가 노출되도록 몰드 마스킹 테이프를 제거하는 단계
를 포함하는 방법을 제공한다. 둘 이상의 장치가 동시에 형성되면, 인접한 장치들을 분리시키기 위해 싱귤레이션 단계가 수행된다.
이제, 도 1을 참조하면, 본 발명의 일 실시예에 따라 형성된 패키징된 반도체 장치(10)의 확대된 횡단면도가 도시되어 있다. 패키징된 장치(10)는 다이 부착 재료(16)로 하나 이상의 연질의 볼들(14)에 부착된, 실리콘 웨이퍼로부터 잘려진 것과 같은 집적 회로 다이(12)를 포함한다. 집적 회로 다이(12)는 복수의 와이어 본딩 패드(20)를 갖는 상단 또는 제1 표면(18)을 갖는다. 와이어 본딩 패드(20)는 연질의 볼들(14) 중 다른 것들에 전기적으로 연결된다. 바람직하게, 와이어 본딩 패드(20)는 와이어 본딩을 통해 와이어(22)를 이용하여 연질의 볼들(14)에 연결된다. 다이(12), 전기적 연결, 와이어(22) 및 적어도 연질의 볼들(14)의 상단부는 몰드 합성물(24)로 덮혀지거나 캡슐화된다. 볼들(14)의 하단면은 노출되고, 집적 회로 다이(12)가 인쇄 회로 보드에 연결되게 해준다. 와이어(22)가 연결되는 볼들(14)은 본 기술분야에 숙련된 자들이 알고 있는 바와 같이, 데이터, 전력 또는 접지 신호를 다이(12) 및 기판 또는 인쇄 회로 보드에/로부터 전달하는 데 사용되는 한편, 다이(12)가 부착되는 다른 볼들(14)은 다이(12)로부터 열을 전달하고(즉, 열 관리) 보드 레벨의 납땜 접합 강도를 강화시킬 수 있다. 즉, 다이(12) 아래의 볼들(14)은 보드 레벨의 납땜 강도를 강화시키는 납땜가능한 표면을 제공한다. 또한, 코너에 있고 패키지 가장자리를 따라 있는 볼들(14)은 패키지의 기계적 강도를 강화시키는 연결을 제공할 수 있음을 유념한다.
집적 회로 다이(12)는 디지털 신호 프로세서, 특수 목적 회로 등과 같은 임의의 유형의 회로일 수 있다. 그러한 회로는 본 기술분야에 숙련된 자들에게 잘 알려져 있다. 연질의 볼들(14)은 바람직하게, 전기 신호가 통과될 수 있도록 전기 적 전도성 재료로 만들어진다. 전도성 재료는 구리 또는 금, 또는 그것의 합금, 또는 63/37 재료(63% 주석, 37% 납) 또는 90/10 재료(90% 납, 10% 주석)과 같은 연질의 땜납과 같은 금속일 수 있다. 대안적으로, 연질의 볼들(14)은 금속 표면 마무리를 갖는 폴리머 주성분의 재료로 형성될 수 있다. 무연 패키지는 무연 금속 볼을 이용함으로써 성취될 수 있다. 볼들(14)은 와이어(22)가 쉽게 와이어본딩될 수 있도록 연질의 재료로 이루어 진다. 바람직하게, 와이어(22)는 와이어 본딩 동안, 와이어(22)가 연질의 볼들(14)을 관통하거나 거기에 매립되도록, 구리 또는 경금합금과 같은 더 딱딱하고 단단한 재료로 이루어진다. 이하에 더 상세히 설명되는 바와 같이, 와이어(22)에 대해서 더 단단한 재료를 사용하면, 와이어(22)는 연질의 볼들(14)을 관통하게 되고, 따라서, 단단한 와이어(22)가 더 연질의 볼들(14)에 매립됨으로써 연결을 형성하게 된다.
다이(12)는 다이 부착 재료(16)로 복수의 볼들(14)에 부착된다. 다이 부착 재료(16)은 다이들을 기판에 부착하는 데 사용되는 임의의 잘 알려진 에폭시 수지와 같은 접착제일 수 있다. 이 실시예에서는 다이(12)가 볼들(14)에 부착되어 있는 것으로 도시되고 있지만, 다이(12)는 구리와 같은 금속으로 형성된 다이 패들의 한 면에 부착될 수 있고, 이러한 경우, 다이 패들의 다른 면이 노출된다. 다른 대안으로는, 다이(12)의 하단(또는, 제2 면)이 노출되게 하는 것인데, 이러한 경우, 다이(12)는 볼들(14) 중 어느 것에도 부착되지 않고, 다이 패들에도 부착되지 않는다. 밀봉제(24, encapsulant)는 집적 회로를 패키징하는 데 흔히 사용되는 본 분야에 숙련된 자들에게 알려진 유형이다.
이제, 도 2a 내지 도 9를 참조하여, 본 발명에 따라 IC 다이를 패키징하기 위한 방법이 설명될 것이다. 도 2a 및 2b는 본 발명의 일 실시예에 따른 연질의 전도성 볼들(14)을 형성하기 위한 픽스처(30)를 도시한다. 도 2a는 픽스처(30)의 투시도이고, 도 2b는 픽스처(30) 내에 배치된 전도성 볼들의 확대도이다. 집적 회로 다이(12)를 패키징하는 공정의 초기 단계는 연질의 볼들(14)을 형성하기 위한 것이다. 픽스처(30)는 볼들(14)이 형성되는 복수의 캐비티를 갖는 넓은 평평한 표면을 갖는 금속 블럭이다. 캐비티는 픽스처(30)의 표면 상에서 그리드 또는 어레이로 레이아웃된다. 낮은 제조 비용은 본 발명에 있어서 중요한 고려사항들 중 하나이다. 본 바람직한 실시예에서, 볼들(14)은 회전판 상에 녹은 금속을 부음으로써 형성된다. 이것은 작은 금속 볼들이 비용상 매우 효율적인 방법으로 매우 엄격한 크기 조절로 형성되게 해준다. 픽스처(30) 내의 캐비티들은 일반적으로 둥글다. 바람직하게, 캐비티는 평평하거나 부분적으로 평평한 하단면을 가져서, 캐비티 내에 형성된 볼의 일부분이 평평하거나 부분적으로 평평한 표면을 갖도록 한다. 구형의 볼들, 또는 평평한 하단면을 가진 구형의 볼들을 형성하는 것에 대한 대안으로서, 직사각형의 볼들을 사용하는 것이 가능하다. 도 10은 직사각형의 볼(15)의 일례를 도시한다.
상술된 바와 같이, 볼들(14)은 연질의 금속과 같은, 변형될 수 있는 연질의 도전성 재료로 형성된다. 예시적인 금속으로는 땜납 또는 금이 있다. 본 기술분야에 숙련된 기술을 가진 자가 알고 있는 바와 같이, 대부분의 BGA 볼들은 매우 연질인 63/67 재료(63% 주석, 37% 납)로 이루어져 있다. 90/10 재료(90% 납, 10% 주 석)이 사용될 때에도, 볼 형상은 변형될 수 있다. 이제, 도 3a 및 3b를 참조하면, 픽스처(30) 내에 볼들(14)이 배치된 후에, 볼들(14)의 상단면(32)은 기계적 코이닝 공정(mechanical coining process)을 통해 프레스(34)에 의해 평평하게 된다. 즉, 프레스(34)는 픽스처(30)의 캐비티 내의 볼들(14)의 상단면을 누르는 데 사용되는데, 이것은 볼들(14)의 상단면(32)을 평평하게 한다. 캐비티는 바람직하게 평평하거나 부분적으로 평평한 하단면을 갖기 때문에, 볼들(14)의 하단면은 상단면(32)과 동일한 방식으로 평평하게 된다. 따라서, 볼들(14)의 적어도 2개의 대향면은 평평하거나 부분적으로 평평하다.
이제 도 4를 참조하면, 기계적 코이닝 공정 이후, 볼들(14)은 픽스처(30)로부터 한쪽 면 상에 접착제를 갖는 몰드 마스킹 테이프(36)로 옮겨진다. 보다 구체적으로, 테이프(36)가 볼들(14) 위에 놓인다. 볼들(14)을 테이프(36)의 접착면에 붙인 후, 테이프(36)를 픽스처(30)로부터 떼어낸다. 이와 달리, 픽스처(30)를 테이프(36)에 대향하여 배치하고, 볼들(14)이 테이프(36)의 접착면에 붙으면, 그 후 픽스처(30)를 제거한다. 도 5에 나타낸 바와 같이, 볼들(14)이 테이프(36)로 옮겨지기 전에 또는 옮겨진 이후에, 몰드 마스킹 테이프(36)가 금속 프레임(38)에 부착될 수 있다.
볼들(14)이 몰드 마스킹 테이프(36)로 옮겨진 후, 다이 부착 단계가 행해진다. 도 5a를 참조하면, 집적 회로 다이(12)들이 미리 정해진 위치에서 복수의 볼들(14)에 부착된다. 다이(12)는 복수의 와이어 본딩 패드(20)를 포함하는 상단면 및 하단면을 갖는다. 본 바람직한 실시예에서, 다이(12)의 하단면은 다이 부착 접 착제(16)에 의해 볼들(14)에 직접 부착되어 있다(도 1). 다이(12)는 복수의 볼들(14)에 의해 둘러싸이는 위치에 부착된다. I/O의 개수를 사용하여, 각각의 다이(12)를 둘러싸는 볼들(14)의 개수를 결정한다. 복수의 볼들(14)의 상단에 다이(12)를 부착하는 것은, 픽스처가 크기가 균일하고 단일 볼 매트릭스 패턴을 갖는 볼들을 형성하기 위해 사용되는 것을 허용한다. 단일 볼 매트릭스 패턴은 픽스처(30) 크기를 변경시킬 필요없이 상이한 크기의 다이 및 상이한 패키지 크기가 형성되게 해준다. 또한, 전술된 바와 같이, 다이(12)가 부착된 볼들(14)은 IC(12)로의 열 경로 역할을 하고, 보드 레벨 납땜 접합 강도를 강화시키는 납땜가능한 면을 제공한다. 즉, 볼들(14)은 납땜가능한 면을 제공한다.
다이 부착에 대한 다른 옵션도 존재한다. 하나의 옵션은 도 5b에 도시된 바와 같이, 볼들(14)이 없는 위치에서 다이(12)를 테이프(36)에 직접 부착시키는 것이다. 즉, 픽스처(30) 내에 볼들의 배열을 형성할 때, 각각의 다이(12)를 수용하기 위한 볼이 없는 일부 공간들을 남겨둔다. 이러한 방식으로, 다이(12)는 캡슐화 및 테이프 탈착 이후 노출된 면을 갖게 된다. 두 번째 옵션은 도 5c에 나타낸 바와 같이 다이(12)를 비전도성 에폭시 수지(40)로 테이프(36)에 부착시키는 것이다. 이 두 번째 옵션을 사용하여 형성된 패키지에서는, 다이(12)가 노출되지 않으며, 다이(12)와 최종 패키지의 외부 간에 전도성 경로가 존재하지 않는다. 이 두 번째 옵션은 패키지 밑에서의 PCB 라우팅을 허용한다. 도 5d를 참조하여, 또 다른 옵션은 에폭시 수지 또는 땜납(44)으로 다이(12)를 열발산판(42)(예를 들어, 고체 금속판)에 부착시키는 것이다. 열발살판(42)은 볼들(14)이 테이프(36)에 부착된 이후 에 테이프(36)에 부착될 수 있다. 열발살판(42)은 또한, 패키지의 열 효율을 향상시키고, 패키지의 납땜가능한 영역을 증가시킬 수 있다.
이제 도 1, 도 6a 및 도 6b를 참조하여, 전술된 바와 같이 다이(12)가 테이프(36)나 볼들(14)에 부착된 후에, 다이(12)를 둘러싸고 있는 형성된 볼들(14) 하나 하나에 와이어 본딩 패드(20)가 전기적으로 연결된다. 보다 구체적으로, 본딩 와이어(22)가 IC 와이어 본딩 패드(20)로부터 형성된 볼들(14) 하나 하나에 연결된다. 형성된 볼들(14)이 오직 몰드 마스킹 테이프(36)의 접착제에 의해서만 홀딩(holding)되어 있으면, 볼은 전형적인 저온열압착 와이어 본딩 공정에서 사용되는 초음파 힘을 적용하기에 충분히 튼튼하게 홀딩되지 못할 수 있다. 따라서, 전형적인 저온열압착 본딩을 적용하는 대신, 연질의 볼들(14)에 침투하기 위해 구리 또는 경금합금으로 만들어진 단단한 와이어를 사용하는데, 이것은 단단한 와이어(22)를 연질의 볼들(14)에 매립시킴으로써 연결을 형성한다. 도 6b에 도시된 바와 같이, 와이어(22)의 끝(33)은 볼들(14)에 매립된다. 끝(33)은 일반적으로 둥근 형상이며, 와이어 본딩 기계에 의해 와이어(22)의 EFO(electric flame off)에 의해 형성된다.
와이어본딩 공정이 수행된 후, 집적 회로 패키징 기술에 알려진 바와 같이, 바람직하게 플라스틱 재료에 의해 다이(12), 전기적 연결, 와이어(22) 및 볼의 일부가 캡슐화된다. 도 7은 밀봉제(24)로 덥여진 테이프(36)를 홀딩하고 있는 금속 프레임(38)을 도시하고 있다. 이 단계에서, 밀봉제는 테이프(36)의 한쪽 면 전체를 덮는다. 볼의 부분적으로 평평한 면은 밀봉제(24) 내에 볼들(14)을 안전하게 지키는 것을 돕는 잠금 특징을 제공한다.
캡슐화 공정 이후, 손이나 상업적으로 사용가능한 디필링(de-peeling) 기계 등으로 인해 몰드 마스킹 테이프(36)가 제거되고, 이에 따라 도 8에 도시된 바와 같이 볼들(14) 배열의 하단부가 노출된다. 신뢰성 있는 LGA 상호연결 성능을 보장하기 위해, 볼의 노출된 하단부는 부식을 방지하고 낮은 접촉 저항을 제공하는 값비싼 표면 마무리(예를 들어, Ni/Au)로 코팅 또는 도금될 수 있다. 볼들(14)의 노출부는 전해 Ni/Au 도금의 선택적인 퇴적을 통해 코팅될 수 있다. 마지막으로, 개별적인 패키징된 장치(10)를 형성하기 위해, 바람직하게 잘 알려진 쏘 싱귤레이션 공정(saw singulation process)를 사용하여 캡슐화된 매트릭스가 싱귤레이팅된다.
쏘 싱귤레이션 공정 이전에, 선택적인 전기 기능 테스트가 행해질 수 있다. 캡슐화된 장치의 I/O 단자들 모두가 패키징 공정을 통해 분리되기 때문에, 스트립 포맷(strip format)의 전기적 테스트가 가능하며, 따라서 테스트기 효율이 향상되고, 추가적인 공정 또는 비용 없이 병렬 테스트가 가능해 진다.
패키징된 장치는 IC(12)로부터 보드로의 신호 경로가 짧아짐으로 인해 고주파수 전기 성능을 향상시켰다. 또한, 시스템 보드의 편향에 의해 발생된 스트레스 장애에 대한 납땜 접합 저항을 증가시킴으로써 시스템 신뢰도가 향상된다. 향상된 RF 성능 및 기기 스트레스 장애에 대한 저항은 셀룰러 전화 핸드셋 제조업자에게 중요한 쟁점이 된다.
본 발명은 용이하고 값싼 집적 회로 패키징 방법을 제공한다. 기판도 종단(외부 핀 또는 볼)도 요구되지 않기 때문에, 장치 비용이 낮다. 금속 리드프레임 이 없기 때문에, 싱귤레이션 단계에서 사용되는 톱날은 금속을 자를 필요가 없으므로 수명이 길어진다. 또한, 리드프레임이 요구되지 않기 때문에, 기판 추적 라우팅이 수행될 필요가 없다. 패키징 공정은 값비쌀 수 있는 화학적인 에칭백을 요구하지 않는다. 패키징 공정은 현재 사용가능한 장치를 사용하여 수행될 수 있다. 패키지는 또한 0.4mm 이하의 매우 짧은 프로파일을 갖는다. LGA 패키지가 설명되어 있지만, 전술된 방법을 사용하여 QFN(Quad Flat No lead)과 같은 다른 패키지 유형도 형성될 수 있다. 스태킹된 다이 장치도 또한 이 방법으로 패키징될 수 있다. LGA는 높은 상호연결 밀도를 제공하며, 예를 들어, 200+I/O가 가능하다.
본 발명의 바람직한 실시예들이 도시 및 설명되어 있지만, 본 발명이 이러한 실시예들에만 제한되는 것은 아니라는 것이 명백해질 것이다. 청구항에 설명된 바와 같은 본 발명의 취지 및 영역으로부터 벗어나지 않는 수많은 수정물, 변경물, 변형물, 대체물 및 등가물이 당업자에 의해 자명해질 것이다.

Claims (9)

  1. 집적 회로 다이(die)를 패키징하는 방법으로서,
    픽스처(fixture) 내에 복수의 연질의 전도성 볼들(soft conductive balls)을 형성하는 단계- 상기 볼들의 대향면들은 적어도 부분적으로 평평하게 되어 있음 -;
    상기 형성된 볼들을 상기 픽스처로부터 몰드 마스킹 테이프(mold masking tape)로 옮기는 단계;
    집적 회로 다이의 제1 면을 상기 몰드 마스킹 테이프에 부착시키는 단계- 상기 다이의 제2 면은 복수의 다이 본딩 패드들(die bonding pads)을 가지며, 상기 다이는 상기 형성된 볼들에 의해 둘러싸임 -;
    상기 다이를 둘러싸고 있는 상기 형성된 볼들 하나 하나에 상기 다이 본딩 패드들을 전기적으로 연결시키는 단계;
    상기 다이, 상기 전기적 연결 및 상기 형성된 볼들의 상단부를 몰드 합성물로 캡슐화하는 단계; 및
    상기 볼들의 하단부가 노출되도록 상기 몰드 마스킹 테이프를 제거하는 단계
    를 포함하는 집적 회로 다이 패키징 방법.
  2. 제1항에 있어서, 상기 픽스처 내에 형성된 상기 볼들은 부분적으로 구형(spherical)인 방법.
  3. 제1항에 있어서, 상기 픽스처 내에 형성된 상기 볼들은 단면이 사각형인 방법.
  4. 제1항에 있어서, 상기 볼들을 형성하는 단계는 상기 볼들의 적어도 2개의 대향면들이 적어도 부분적으로 평평하게 되는 기계적 코이닝(mechanical coining) 단계를 포함하는 방법.
  5. 제1항에 있어서, 상기 몰드 마스킹 테이프를 프레임에 부착시키는 단계를 더 포함하는 방법.
  6. 제1항에 있어서, 상기 다이를 부착시키는 단계는 상기 다이의 제1 면을 다이 부착 접착제로 상기 복수의 볼들에 부착시키는 단계를 포함하는 방법.
  7. 제1항에 있어서, 상기 전기적으로 연결시키는 단계는, 상기 다이 본딩 패드들을 대응하는 복수의 와이어들로 상기 볼들 하나 하나에 와이어본딩시키는 단계를 포함하는 방법.
  8. 제7항에 있어서, 상기 와이어본딩시키는 단계에서, 상기 와이어들은 상기 볼들 내에 침투하여 거기에 매립되는 방법.
  9. 제1항에 있어서, 상기 캡슐화된 다이를 인접한 캡슐화된 다이들로부터 쏘 싱귤레이팅(saw singulating)하는 단계를 더 포함하는 방법.
KR1020067011382A 2003-12-09 2004-11-04 집적 회로 다이를 패키징하는 방법 KR101119708B1 (ko)

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