CN107919331A - 无引线框架的表面安装半导体器件 - Google Patents

无引线框架的表面安装半导体器件 Download PDF

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Publication number
CN107919331A
CN107919331A CN201710912158.XA CN201710912158A CN107919331A CN 107919331 A CN107919331 A CN 107919331A CN 201710912158 A CN201710912158 A CN 201710912158A CN 107919331 A CN107919331 A CN 107919331A
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China
Prior art keywords
electrical connecting
top surface
packaging body
semiconductor devices
semiconductor
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Pending
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CN201710912158.XA
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English (en)
Inventor
波姆皮奥·V·乌马里
尤金·普马内斯·桑托斯
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Yasuyo Co Ltd
Nexperia BV
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Yasuyo Co Ltd
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Publication of CN107919331A publication Critical patent/CN107919331A/zh
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种半导体器件，包括：具有顶表面的半导体裸片，接合焊盘形成在所述顶表面上；电连接元件，每个电连接元件具有位于第一平面且电连接至接合焊盘中的一个接合焊盘的第一端以及位于与第一平面不同的第二平面的相对的第二端；以及成型材料，其封装半导体裸片和电连接元件，其中，成型材料限定具有顶表面和一个或多个侧表面的封装体，其中，每个电连接元件的第二端暴露在封装体的顶表面处并暴露在封装体的一个或多个侧表面中的至少一个处。

Description

无引线框架的表面安装半导体器件
技术领域
本发明涉及集成电路(IC)器件装配，更具体地，涉及无引线框架(leadframe-less)的表面安装半导体器件。
背景技术
用平面铜引线框架制造的方形扁平无引脚(QFN)封装是广泛使用的表面安装技术。典型的QFN装配流程包括前段(FOL)工艺和后段(EOL)工艺。FOL工艺包括贴片、互连接合和检查，而EOL工艺包括成型、顶部标记、镀锡、封装分离和最终检查，这是昂贵的封装处理。因此，用无引线框架的封装结构来改善装配过程并降低总封装成本将是有利的。
发明内容
在一个实施例中，本发明提供一种半导体器件，包括：具有顶表面的半导体裸片，一个或多个接合焊盘形成在顶表面上；以及一个或多个电连接元件，每个电连接元件具有位于第一平面处并且电连接至这些接合焊盘中的一个接合焊盘的第一端以及位于与第一平面不同的第二平面的相对的第二端。成型材料封装半导体裸片和电连接元件。成型材料限定具有顶表面和一个或多个侧表面的封装体。每个电连接元件的第二端暴露在封装体的顶表面和至少一个侧表面处。
在另一实施例中，本发明提供一种用于装配半导体器件的方法。所述方法包括：提供晶片，该晶片具有：顶表面和相对的底表面；以沿第一方向和第二方向延伸的阵列的形式布置的多个半导体裸片；以及锯道，其位于半导体裸片中相邻的半导体裸片之间。每个半导体裸片具有形成在顶表面上的一个或多个接合焊盘。所述方法还包括：将一个或多个电连接元件接合至半导体裸片的接合焊盘，其中，每个电连接元件沿第一方向和第二方向中的至少一个方向桥接相邻的半导体裸片；以及用成型材料对半导体裸片和电连接元件进行封装以形成半导体器件的阵列的组件。每个半导体器件包括由成型材料形成的封装体，并且一个或多个电连接元件中的每个具有暴露在组件的顶表面处的桥部。所述方法还包括：通过沿锯道切割组件来分离半导体器件，其中，每个半导体器件的每个电连接元件的剩余部分具有暴露在封装体的顶表面和至少一个侧表面处的端部。
附图说明
可以参照以下对优选实施例的描述与附图一起来最佳地理解本发明及其目标和优点，附图中：
图1A是根据本发明的第一实施例的无引线框架的表面安装半导体器件的部分分解等距示图，而图1B和图1C是图1A的器件的A侧和B侧的截面侧示图；
图2是根据本发明的第二实施例的无引线框架的表面安装半导体器件的部分分解等距示图；
图3是根据本发明的第三实施例的无引线框架的表面安装半导体器件的部分分解等距示图；
图4A-图4B、图5A-图5B、图6A-图6B、图7-图8、图9A-图9B、图10、图11A-图11B以及图12-图13是示出根据本发明实施例的装配无引线的框架表面安装半导体时的步骤的一系列示图。
具体实施方式
以下结合附图阐述的详细描述旨在作为对本发明的当前优选实施例的描述，并不旨在表示可以实践本发明的唯一形式。要理解的是，相同或等同的功能可以通过旨在被包含在本发明的精神和范围内的不同实施例来实现。在附图中，相同的数字自始至终都用于表示相同的元件。还应当注意的是，附图提供放大示图而不是按比例绘制，使得可以更好地理解本发明的特定特征。术语“包括”、“包括有”或其任意变形旨在涵盖非排他性包含，使得包括一系列元件或步骤的模块、电路、设备部件、结构和方法步骤不仅包括这些元件，还可以包括未明确列出的或者这些模块、电路、设备组件或步骤固有的其他元件或步骤。在没有更多约束的情况下，由“包括...一个”进行的元件或步骤不排除包含该元件或步骤的额外的相同元件或步骤的存在。
现在参照图1A-图1C，示出无引线框架的表面安装半导体器件100的示例。具体地，图1A示出无引线框架的表面安装半导体器件100的部分分解等距示图，而图1B和图1C是图1A的无引线框架的表面安装半导体器件的A侧和B侧的截面侧示图。半导体器件100包括：具有顶表面的半导体裸片102，一个或多个接合焊盘104形成在顶表面上；以及一个或多个电连接元件106，每个电连接元件106具有位于第一平面处并且电连接至一个或多个接合焊盘104中的一个接合焊盘的第一端108以及位于与第一平面不同的第二平面的相对的第二端110。
在优选实施例中，电连接元件106的第一端108直接与接合焊盘104接合。在另一优选实施例中，半导体器件100包括可选的再分布层112，所述再分布层112位于接合焊盘104与电连接元件106的第一端108之间。
半导体器件100还包括成型材料114，所述成型材料114覆盖或封入半导体裸片102和一个或多个电连接元件104。成型材料114限定具有顶表面和一个或多个侧表面的封装体116。每个电连接元件106的第二端110暴露在封装体116的顶表面处以及暴露在封装体116的一个或多个侧表面中的至少一个处。在优选实施例中，电连接元件106是由铜形成的电镀的或未电镀的导电夹。每个电连接元件106的第二端110暴露在封装体116的顶表面和两个相邻的侧表面处。
在优选实施例中，半导体器件100包括金属层118，所述金属层118形成在封装体116的顶表面之上并且电连接至每个电连接元件106的第二端110。在优选实施例中，金属层118包括铜或其他导电金属。在另一优选实施例中，使用导电电镀工艺，用可湿性材料120(诸如锡)来涂覆金属层118。
在优选实施例中，半导体器件100还包括裸片载体122，其中，半导体裸片102的底表面用粘性材料附接至裸片载体122。在优选实施例中，裸片载体122是衬底。在另一优选实施例中，裸片载体122是胶带。
图2是根据本发明的第二实施例的无引线框架的表面安装半导体器件200的部分分解等距示图。除了电连接元件202是带形导电金属夹以外，半导体器件200与半导体器件100实质上相同，所述带形导电金属夹具有暴露在封装体116的顶表面和封装体116的一个侧表面处的第二端206。
图3是根据本发明的第三实施例的无引线框架的表面安装半导体器件300的部分分解等距示图。除了电连接元件302包括一个或多个接合线以外，半导体器件300与半导体器件200实质上相同，所述接合线具有暴露在封装体116的顶表面和封装体116的一个侧表面处的第二端306。
图4A-图4B、图5A-图5B、图6A-图6B、图7-图8、图9A-图9B、图10、图11A-图11B以及图12-图13是示出根据本发明的另一实施例的装配无引线框架的表面安装半导体器件时的步骤的一系列示图。
从图4A和图4B开始，提供具有顶表面402和相对的底表面404的晶片400。图4A是晶片400的等距示图，而图4B是晶片400沿图4A的线A-A的截面侧示图。晶片400包括多个半导体裸片406并且具有位于这些裸片406中的相邻裸片之间的锯道(saw street)408。每个裸片406具有形成在顶表面402上的一个或多个接合焊盘410。在优选实施例中，每个裸片400包括诸如晶体管或二极管的一个或多个有源部件(即，内部电路，未示出)，并且优选地，通过在顶表面402上沉积图案化金属层来形成接合焊盘410。接合焊盘410提供与裸片406内的有源部件的电连接。在优选实施例中，用粘性材料414将晶片400的底表面404安装在载体412的顶表面上。在优选实施例中，载体412是半导体衬底。
在图5A和图5B所示的下一步骤中，沿着锯道408来切割晶片400，以在这些裸片406中的相邻裸片之间形成多个沟槽418。图5A是切割之后的晶片400的俯示图，而图5B是晶片400的部分500沿图5A的线B-B的截面侧示图。如图5A中所示，半导体裸片406以沿X方向和Y方向二者延伸的阵列的形式布置。在优选实施例中，沟槽418向下延伸至粘性材料414。在另一优选实施例种，沟槽418延伸超过粘性材料414并且进入载体412中。
在图6A和图6B所示的下一步骤中，将多个电连接元件502附接或电连接至半导体裸片406的接合焊盘410。电连接元件502包括脚508，并且每个电连接元件502沿X方向和Y方向中的至少一个方向桥接相邻的半导体裸片406。图6A是具有与其接合的电连接元件502的晶片400的俯示图，而图6B是半导体裸片406和电连接元件502的部分504的放大的等距示图，该部分504包括与正交的两个沟槽418的交叉部分相邻的四个半导体裸片406。
在优选实施例中，将再分布层506附接至接合焊盘410，并且将电连接元件502接合至再分布层506并且通过再分布层506电连接至接合焊盘410。如果接合焊盘410不具有足够面积来容纳电连接元件502的脚508，则可选地设置再分布层506。在优选实施例中，再分布层506是分别位于接合焊盘410与电连接元件502的脚508之间的单独件。在另一优选实施例中，单个再分布层506位于半导体裸片406的顶表面之上。
在如图6A和图6B中所示的优选实施例中，电连接元件502包括金属组合夹(metalgang clip)，所述金属组合夹具有：四个脚508，其分别接合至与正交的两个沟槽418的交叉部分相邻的四个半导体裸片406的接合焊盘410；以及桥部510，其连接四个脚508，使得电连接元件502沿X方向和Y方向二者桥接相邻的半导体裸片406。
在如图7中所示的另一优选实施例中，电连接元件502是带形金属夹，所述带形金属夹具有：两个脚508，其接合至与两个相邻半导体裸片406的接合焊盘；以及桥部510，其连接两个脚508，使得电连接元件502沿Y方向桥接两个相邻的半导体裸片406。
在如图8所示的又一实施例中，电连接元件502包括接合线，所述接合线沿Y方向桥接相邻的半导体裸片406。
在图9A和图9B中所示的下一步骤中，用成型材料512对半导体裸片406和电连接元件502进行封装，以形成由锯道518分隔开的半导体器件516的阵列的组件514。图9A和图9B分别是组件514的截面侧示图和俯示图。成型材料512填充多个沟槽418，并且覆盖半导体裸片406的侧表面。每个半导体器件516包括由成型材料512形成的封装体520，其中，电连接元件502的桥部510暴露在组件514的顶表面处。
在图10中所示的下一步骤中，在组件514的顶表面之上形成金属层522。在优选实施例中，通过溅射或电镀来形成金属层522。在优选实施例中，金属层522包括铜。
如图11A和图11B所示，通过化学刻蚀或机械半切来在金属层522内选择性地形成开口524，以使每个半导体裸片406的接合焊盘410彼此电隔离。图11A和图11B分别示出已经在金属层522中形成开口524之后的组件514的截面侧示图和俯示图。成型材料512在开口524处暴露。在优选实施例中，开口524平行于一个方向上的锯道518。在另一优选实施例中，开口524不延伸至金属层522的边缘，使得金属层522仍然为一片金属而不被任意一个开口524分开。在优选实施例中，如图12中所示，用可湿性材料526诸如通过电镀来涂覆金属层522。如本领域已知的，可湿性材料526可以包括锡或锡合金。在可替换实施例中，在开口524形成之前执行电镀。
在图13中所示的下一步骤中，沿锯道518执行分离来使半导体器件516彼此分开。在分离之后，电连接元件502的剩余的桥部510暴露在封装体520的顶表面和至少一个侧表面处。
已经出于说明和描述的目的提出了对本发明的优选实施例的描述，但是并非意在穷举或将本发明限制于所公开的形式。本领域技术人员将理解，在不脱离其宽泛的发明构思的情况下，可以对上述实施例进行修改。因此理解的是，本发明不限于所公开的特定实施例，而是涵盖了如所附权利要求限定的本发明的精神和范围内的变形。

Claims (20)

1.一种半导体器件，包括：
半导体裸片，其具有顶表面以及相对的底表面，一个或多个接合焊盘形成在所述顶表面上；
一个或多个电连接元件，每个电连接元件具有位于第一平面且电连接至所述一个或多个接合焊盘中的一个接合焊盘的第一端以及位于与所述第一平面不同的第二平面的相对的第二端；以及
成型材料，其封装所述半导体裸片和所述一个或多个电连接元件，其中，所述成型材料限定具有顶表面和一个或多个侧表面的封装体，其中，每个电连接元件的所述第二端暴露在所述封装体的所述顶表面处并暴露在所述封装体的所述一个或多个侧表面中的至少一个处。
2.如权利要求1所述的半导体器件，其中，所述一个或多个电连接元件中的每个的所述第二端暴露在所述封装体的所述顶表面和两个相邻的侧表面处。
3.如权利要求1所述的半导体器件，还包括：
金属层，其形成在所述封装体的所述顶表面之上并且电连接至所述一个或多个电连接元件的至少一个。
4.如权利要求3所述的半导体器件，其中，通过导电电镀用可湿性材料来涂覆所述金属层。
5.如权利要求1所述的半导体器件，还包括：
裸片载体，其中，所述半导体裸片的所述底表面附接至所述裸片载体。
6.如权利要求1所述的半导体器件，还包括：
再分布层，其位于所述一个或多个接合焊盘与所述一个或多个电连接元件之间。
7.如权利要求1所述的半导体器件，其中，所述一个或多个电连接元件是金属夹。
8.如权利要求1所述的半导体器件，其中，所述一个或多个电连接元件是接合线。
9.一种半导体器件，包括：
裸片，其顶表面上具有至少两个接合焊盘；
至少两个导电的夹，其具有分别连接至所述接合焊盘的第一端；
成型材料，其覆盖所述裸片和所述夹，其中，所述成型材料形成封装体，并且所述夹的相对的第二端暴露在所述封装体的顶表面和所述封装体的至少一个侧表面处；以及
至少两个金属层，其形成在所述夹各自的暴露的第二端和所述封装体的所述顶表面之上。
10.如权利要求9所述的半导体器件，其中，所述夹的所述第二端暴露在所述封装体的所述顶表面和所述封装体的两个相邻的侧表面处。
11.一种装配半导体器件的方法，所述方法包括：
提供具有顶表面和相对的底表面的晶片，其中，所述晶片包括以沿第一方向和第二方向延伸的阵列的形式布置的多个半导体裸片以及位于所述多个半导体裸片中的相邻半导体裸片之间的锯道，其中，每个半导体裸片具有形成在所述顶表面上的一个或多个接合焊盘；
将一个或多个电连接元件接合至所述多个半导体裸片的所述接合焊盘，其中，每个电连接元件沿所述第一方向和所述第二方向中的至少一个方向桥接相邻的半导体裸片；
用成型材料对所述半导体裸片和所述一个或多个电连接元件进行封装以形成半导体器件阵列的组件，其中，每个半导体器件包括由所述成型材料形成的封装体，并且所述一个或多个电连接元件中的每个具有暴露在所述组件的顶表面处的桥部；以及
通过沿所述锯道切割所述组件来分离所述半导体器件，其中，每个半导体器件的每个电连接元件的剩余部分具有暴露在所述封装体的顶表面和至少一个侧表面处的端部。
12.如权利要求11所述的方法，其中，每个电连接元件沿所述第一方向和所述第二方向二者桥接相邻的半导体裸片，使得每个半导体器件的每个电连接元件的所述剩余部分具有暴露在所述封装体的所述顶表面和两个相邻的侧表面处的端部。
13.如权利要求11所述的方法，还包括：
在所述封装步骤之前，沿所述锯道切割所述晶片以在裸片中的相邻裸片之间形成多个沟槽，使得在所述封装步骤之后，所述成型材料填充所述多个沟槽并且覆盖所述半导体裸片的侧表面。
14.如权利要求11所述的方法，还包括：
在所述组件的所述顶表面之上形成金属层；以及
选择性地切割所述金属层来使每个半导体器件的电连接元件彼此电隔离。
15.如权利要求14所述的方法，其中，通过溅射或电镀来形成所述金属层。
16.如权利要求14所述的方法，还包括：
用可湿性材料来电镀所述金属层。
17.如权利要求11所述的方法，还包括：
将所述晶片的所述底表面安装至载体的顶表面。
18.如权利要求11所述的方法，还包括：
在将所述一个或多个电连接元件接合至所述半导体裸片的所述接合焊盘之前，在所述晶片的所述顶表面之上形成再分布层。
19.如权利要求11所述的方法，其中，所述一个或多个电连接元件是金属夹，其中，每个金属夹具有四个脚和将所述四个脚连接的桥部，所述四个脚分别电连接至位于两个锯道的交叉部分的四个角处的半导体裸片的接合焊盘。
20.如权利要求11所述的方法，其中，所述一个或多个电连接元件是接合线。
CN201710912158.XA 2016-10-06 2017-09-29 无引线框架的表面安装半导体器件 Pending CN107919331A (zh)

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