CN101032021A - 低矮外形、芯片级封装及制作方法 - Google Patents

低矮外形、芯片级封装及制作方法 Download PDF

Info

Publication number
CN101032021A
CN101032021A CNA2005800332631A CN200580033263A CN101032021A CN 101032021 A CN101032021 A CN 101032021A CN A2005800332631 A CNA2005800332631 A CN A2005800332631A CN 200580033263 A CN200580033263 A CN 200580033263A CN 101032021 A CN101032021 A CN 101032021A
Authority
CN
China
Prior art keywords
chip
substrate
gap
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005800332631A
Other languages
English (en)
Inventor
纳温钱德拉·卡利达斯
耶雷米亚斯·P·利布雷斯
迈克尔·P·皮尔斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN101032021A publication Critical patent/CN101032021A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/4851—Morphology of the connecting portion, e.g. grain size distribution
    • H01L2224/48511—Heat affected zone [HAZ]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明揭示一种具有电绝缘衬底(301)的半导体装置，电绝缘衬底(301)具有第一及第二表面、至少一个开口及给定的厚度。导电路由条带连接第一衬底表面上的接触焊垫(330)。厚度等于或小于所述衬底的半导体芯片(102)定位于衬底开口内，其中边缘间隙(311)将朝外的芯片侧面(703)与朝内的衬底侧面(702)隔开。结合元件(501)跨越所述间隙将衬底路由条带与位于芯片有源表面(102a)上的芯片结合焊垫相连。芯片(102)具有与第二衬底表面(301b)基本共面的无源表面(102b)。囊封材料(701)填充边缘间隙(311)并覆盖有源芯片表面(102a)及结合元件(501)。支撑带(101)－其在组装之后被移除－用于提供与第二衬底表面(301b)及无源芯片表面(102b)基本共面的囊封材料(701)的间隙填充表面(701a)。

Description

低矮外形、芯片级封装及制作方法
技术领域
本发明大体而言涉及半导体装置领域，且更具体而言，涉及低矮外形、芯片级多芯片封装及制作方法。
背景技术
例如移动电话及其他便携式、手持式及可佩带式产品等消费产品的强烈市场趋势要求使用在安装于电路板上时仅占用非常小的面积及高度的积木形式的半导体装置。其中一种用于得到细长、小尺寸半导体装置的最成功的方法是开发所谓的“芯片级封装”。这些封装具有使芯片面积增加不到20％的外形轮廓；然而，其高度尚未达到所需的薄的外形。
一种广泛实施的组装及封闭半导体芯片的方法是首先提供“空腔区朝下”式封装并将芯片组装于空腔区中。该组装过程包括使用粘著材料来粘固芯片的步骤，随后是进行丝焊以使芯片接触焊垫与封装端子相连的步骤。然而，在金属丝球焊工艺中，金属丝的机械上脆弱的受热影响区域使得金属丝必须在球上面处于垂直位置，从而导致丝焊的特别高的回绕。空腔区朝下的封装自身的特点常常是具有几个内置的导电线层，以便能够将焊料球连接至外部部件。金属丝回绕所需的高度及多层式封装的设计阻碍人们获得薄的装置外形；此外，其不易于降低制作成本。
便携式产品进一步要求半导体装置具有改良的热特性，且常常要求具有改良的电性能，尤其是更高的速度。在现有的空腔区朝下的封装中，难以使导热金属件接触半导体芯片。在丝焊及多层式封装配置存在这些技术约束的情况下，也难以在多层式封装中布置短的、高速线或屏蔽线。
发明内容
本发明提供一种半导体装置及一种制作此种装置的方法，所述半导体装置具有装配于装置封装内的半导体芯片，而无需用于现有低矮外形、芯片级多芯片封装装置中的类型的空腔。本发明各实施例的优点是会减小互连线长度、腾出用于直接附连散热器的芯片表面、减小装置外形、及减小封装部件以及整个组装过程的成本。其实施方案非常灵活，足以应用于不同的半导体产品系列及各种各样的设计和组装变化形式，并会实现朝提高工艺良率及装置可靠性的目标进行的改良。
本发明的一个实施例是一种半导体装置，其包含电绝缘衬底，所述电绝缘衬底具有第一及第二表面、至少一个穿过所述第一及第二表面的开口、及给定的厚度。在所述第一表面上是导电元件，其可呈多个导电路由条带及多个接触焊垫的形式。所述接触焊垫中的至少一者电连接所述路由条带中的至少一者，并可附连有焊料体。半导体芯片定位于所述衬底开口内，与所述衬底相隔一边缘间隙。所述芯片具有包含至少一个结合焊垫的第一表面、及第二表面。芯片厚度小于或基本等于衬底厚度。结合元件跨越所述间隙，以对结合焊垫与路由条带进行电连接。囊封材料覆盖有源芯片表面及结合元件，并填充所述间隙以提供一填料表面。所述衬底及芯片可配置有平整的表面，以使所述填料表面形成为与所述芯片第一或第二表面及所述第二衬底表面基本共面。此外，一散热器可附连至共面的无源芯片表面及第二衬底表面。
本发明的另一实施例是一种具有衬底的多芯片模块，所述衬底在其第一及第二表面二者上具有一开口及多个导电路由条带。第一芯片处于所述衬底开口中，与所述衬底之间留有第一间隙，所述衬底的有源表面基本与所述第一衬底表面共面，且结合元件桥接所述第一间隙，以将所述第一芯片结合焊垫连接至所述第一衬底表面的路由条带。第二芯片处于所述衬底开口中，与所述衬底之间留有第二间隙，所述衬底的有源表面基本与所述第二衬底表面共面，且结合元件桥接所述第二间隙，以将所述第二芯片结合焊垫连接至所述第二衬底表面的路由条带。所述第一及第二芯片的无源表面通过粘著层相互粘固。囊封材料保护所述有源芯片表面及结合元件，并填充第一及第二间隙。
本发明的另一实施例是一种用于组装半导体装置的方法，其包括：衬底，其具有第一及第二表面及开口；及定位于该开口中的芯片，其具有有源及无源表面。该方法采用具有粘著性上表面的可移除式支撑带，其用于使所述第二衬底表面与所述无源芯片表面基本共面地对齐，且其在装置组装完成之后被丢弃。所述方法可进一步包含如下步骤：将焊料球附连至所述第一衬底表面上并将散热器附连至所述无源芯片表面及共面的第二衬底表面上。
本发明的另一实施例是一种用于组装半导体多芯片装置的方法，所述半导体多芯片装置包含：衬底，其具有第一及第二表面及开口；及位于所述开口中的两个具有有源表面及无源表面的芯片，其在其无源表面上相互附连。所述方法采用具有粘著性表面的可移除式支撑带，其用于使所述第一衬底表面与所述第一芯片的有源表面基本共面地对齐。在将所述第二芯片附连至所述第一芯片上之后，将所述第二芯片的焊垫结合至所述第二衬底表面的路由条带上，且囊封所述第二芯片的有源表面及填充所述芯片-衬底间隙，丢弃所述支撑带。所述方法在如下步骤中结束：将所述第一芯片的焊垫结合至所述第一衬底表面的路由条带上，并囊封所述第一芯片的有源表面。
附图说明
下文将参照附图来说明本发明的实施例。
图1-12示意性地图解说明在根据本发明实施例制作低矮外形芯片级装置的工艺流程中的所选步骤；
图1A为支撑带及薄于衬底的芯片的示意性剖面图；
图1B为支撑带及与衬底一样厚的芯片的示意性剖面图；
图2为所要组装的支撑带及芯片的示意性俯视图；
图3A为带有所附连芯片的支撑带及(较厚)衬底的示意性剖面图；
图3B为带有所附连芯片的支撑带及(相等厚度)衬底的示意性剖面图；
图4为带有所附连芯片的支撑带及所要组装的衬底的示意性俯视图；
图5A为所附连衬底及(较薄)芯片的示意性剖面图，其图解说明互连丝焊点；
图5B为所附连衬底及(相等厚度)芯片的示意性剖面图，其图解说明互连楔形焊点；
图6为经组装及互连的衬底与芯片的示意性俯视图；
图7A为经囊封及丝焊的芯片与衬底组合件的示意性剖面图；
图7B为经囊封、楔焊的芯片与衬底组合件的示意性剖面图；
图8为经囊封及互连的芯片与衬底组合件的示意性俯视图；
图9A显示附连有焊料体的经丝焊组装的芯片与衬底的示意性剖面图；
图9B显示附连有焊料体的经楔焊组装的芯片与衬底的示意性剖面图；
图10显示附连有焊料体的芯片与衬底组合件的示意性俯视图；
图11A示意性地图解说明从图9A中的所封装装置中移除支撑带的过程步骤；
图11B示意性地图解说明从图9B中的所封装装置中移除支撑带的过程步骤；
图12示意性地图解说明在移除支撑带之后所封装装置的俯视图；
图13A显示附连有散热片的图11A所示装置的示意性剖面图；
图13B显示附连有散热片的图11B所示装置的示意性剖面图；
图14为根据本发明另一实施例组装于支撑带上的多芯片装置的示意性俯视图；
图15为在丢弃支撑带之后图14所示多芯片装置的示意性俯视图；
图16至22示意性地图解说明在根据本发明另一实施例制作低矮外形、芯片级、多芯片装置的工艺流程中的所选步骤；
图16为支撑带、第一芯片及衬底的示意性剖面图；
图17示意性地图解说明将第二芯片附连至第一芯片上的工艺步骤；
图18示意性地图解说明将第二芯片互连至衬底上的工艺步骤；
图19示意性地图解说明囊封第二芯片并填充这两个芯片与衬底之间的间隙的工艺步骤；
图20为在丢弃支撑带、翻转所述组合件、并将第一芯片互连至衬底之后所述装置的示意性剖面图；
图21为在囊封第一芯片之后已组装装置的示意性剖面图；
图22为附连有焊料体的经囊封多芯片装置的示意性剖面图；
图23为附连有焊料体的经囊封多芯片装置的示意性剖面图，所述多芯片包含多于两个芯片；
图24为在衬底的两个表面上均附连有焊料体的经囊封多芯片装置的示意性剖面图。
具体实施方式
下文将根据本发明的实例性实施例、参照一系列工艺步骤来说明本发明的半导体装置及制作方法。图1A、1B及2图解说明具有粘著性表面101a(较佳具有低的强度以易于移除)的支撑带101。在组装工艺流程中，该表面101a朝上。较佳地，带101是厚度介于约25至100μm范围内的电绝缘聚酰亚胺箔。
半导体芯片(图1A中的102及图1B中的120)放置于带101的粘性表面101a上。芯片102/120具有带有至少一个焊垫103/130的有源表面102a/120a、及无源表面102b/120a。无源表面102b/120b粘附至带表面101a上。半导体芯片可为硅集成电路芯片、离散硅装置芯片、或由硅、锗化硅、砷化镓或任何其他用于装置制造的半导体材料制成的任何其他半导体芯片。芯片厚度较佳等于或小于衬底厚度(参见图3A及3B)。图1A中的厚度104小于图3A中的衬底厚度302(例如，厚度104可约为100μm或以下)，而图1B中的厚度105约等于图3B中的衬底厚度302(例如，厚度105可介于225与275μm之间)。
图2示意性地图解说明将芯片102/120放置于支撑带102的粘著性表面102a上的工艺步骤。通过预先印刷的参考标记或记号(“基准”)201来支持所述放置，所述参考标记或记号(“基准”)用作对芯片102/120及随后对衬底进行定位的对齐标记。芯片102/120具有多个结合焊垫103/130。
图3A及3B示意性地图解说明将衬底301放置于支撑带101的粘著性表面101a上的工艺步骤。衬底301是较佳为薄片状的电绝缘材料，其选自由FR-4、FR-5、玻璃纤维、聚酰亚胺及相关聚合物所组成的群组。衬底301的厚度302可处于约50至300μm范围内。衬底301具有第一表面301a及第二表面301b；第二表面301b粘固至带表面101a。在第一表面301a上布置有多个导电路由条带340(显示于图4中)及多个接触焊垫330。接触焊垫330电连接至各个路由条带340(显示于图4中)。
在图3A及3B中，衬底301具有宽度为310的开口(在图14及15中，显示不止一个开口)。可使所述开口的形状为矩形、正方形、圆形或任意其他几何形状。开口宽度310的尺寸使其适合接纳放置于所述开口内的芯片102(图3A)或者芯片120(图3B)，同时在衬底上在芯片与衬底开口的面对的侧边缘之间留下边缘间隙311。
图4示意性地绘示将衬底301放置于支撑带102的粘著性表面102a上的工艺步骤。通过预先印刷的基准201来支持所述放置，基准201用作围绕芯片102/120对衬底301进行定位的对齐标记。图4显示所述多个接触焊垫330及导电路由条带340。
图5A及5B图解说明通过由结合元件将各芯片结合焊垫分别电连接至衬底路由条带来分别桥接芯片102或120与衬底301之间间隙311的工艺步骤。在图5A中，使用金属丝球焊点501将芯片结合焊垫103连接至衬底路由条带340(参见图6)的尖端340a。在图5B中，使用楔形焊点502来实现类似的连接。对于这两种类型的焊接技术而言，为支持制作低矮外形装置的目标，较佳使金属丝或条带的回绕保持较低。通过窄的间隙311来促进形成低的回绕。一种适用于进行低回绕丝焊的技术揭示于2004年9月30日颁予且名称为“Wire Bonding for Thin Semiconductor Package”的第6,815,836号美国专利中。
图6显示多个结合元件601，其用于将芯片102的各芯片结合焊垫103连接至其各自的衬底路由条带340的尖端340a上。对芯片120的各芯片结合焊垫130也进行类似的连接。
图7A及7B绘示填充间隙311及使用囊封材料701分别囊封有源芯片表面102a或120a和结合元件501或502的工艺步骤。对该囊封材料加以选择，以使其粘固至衬底侧面702上或者面对开口311的芯片侧面703上。因此，该工艺步骤会实现对装置部件的保护以及粘合性。由于使用囊封材料将间隙311向下填充至支撑带表面101a，因而101a处的囊封材料表面基本上分别与无源芯片表面102b或120b及第二衬底表面301b共面。
图8显示囊封材料701使衬底接触焊垫330仍保持外露，以便随后附连焊料体。图9A及9B图解说明使用丝焊(图9A)及楔焊(图9B)在所囊封的装置上进行焊料体901的此种附连。图10显示附连至每一衬底接触焊垫的焊料体901。
组装及封装工艺流程的最终步骤是从完工的装置中移除支撑带101。在图11A中针对丝焊装置及在图11B中针对楔焊装置示意性地图解说明所述带移除步骤。对于这两种装置类型而言，该步骤均会暴露出第二衬底表面301b、无源芯片表面102b/120b、及共面的装置囊封表面(在图11A及11B中标记为701a)。这三个表面的共面性是在制作工艺流程中使用支撑带101所特有的。
图12绘示在无支撑带时的已完工装置。在使装置翻转之后，该产品的共面的背面提供一平面，以用于附连散热器来改善装置的热性能。这些散热器可制作成各种各样的形状及尺寸，特定散热器设计1301的实例示意性地显示于图13A(丝焊装置)及13B(楔焊装置)中。通常使用导热性粘著剂1302(其可例如为填充银的环氧树脂)来实施所述附连。
在本发明的另一实施例中，将图1至12中所述的组装概念方法扩展至多芯片装置。所述衬底提供芯片互连线的一部分。双芯片装置的一实例示意性地图解说明于图14(仍附连有支撑带101)及图15(在移除支撑带之后)中。第一芯片1401及第二芯片1402可属于不同的装置系列(不同的面积大小)，或者其可来自同一系列(相同的面积大小)。在图14及15中显示联合衬底1403的第一表面、以及导电路由条带1440。联合衬底1403具有多个开口(在图14及15中为两个开口，其标记为1410及1411)，其中在每一开口中将一个半导体芯片定位成在每一芯片与各自衬底开口之间留有间隙。通过丝焊元件桥接这些间隙，并随后使用粘固至芯片及衬底开口侧面上的囊封剂来填充这些间隙。带101的上表面的共面性确保使所有芯片的无源表面均与衬底的第二表面共面。因此，可在共面的装置表面上附连散热器来改善热特性。
图16-22示意性地图解说明根据本发明另一实施例的低矮外形、芯片级多芯片装置的制作流程中的所选工艺步骤。在该装置中，通过在衬底的环绕多芯片堆叠的开口内叠置两个芯片来组装这两个芯片。在图23中显示具有三个芯片的实例性装置。所述组装及封装顺序同样是基于具有粘著性上表面的可移除式支撑带。
在图16中，将可移除式支撑带1601定向成使其粘著性表面1601a朝上。电绝缘衬底1602(较佳为薄片形状)具有第一表面1602a，第一表面1602a包含导电路由条带(在图16中未显示)及接触焊垫1603。各接触焊垫1603分别与各路由条带电连接。衬底1602进一步具有第二表面1602b，第二表面1602b具有与表面1602b成一体的导电路由条带。在图24所示的另一实施例中，第二表面1602b还具有接触焊垫，所述接触焊垫分别与表面1602b上的各路由条带电连接。如图16所示，将衬底1602定向成使其第一表面1602a面朝带1601，其中衬底表面1602粘附至所述带的粘性表面1601a上。
在图16中显示衬底1602具有一个宽度为1610的开口。在其他实施例中，也可使用具有不止一个开口的衬底。宽度1610经尺寸确定以将所述堆叠中具有最大尺寸的芯片定位于开口内，同时与所述开口的衬底侧面之间留有间隙。衬底1602进一步具有约等于所述堆叠中多层芯片的厚度之和的厚度1604。
在衬底1602已放置于支撑带1601上、使其第一表面1602面朝带1601的粘性侧之后，添加第一半导体芯片1620。芯片1620具有包含结合焊垫1630的有源表面1620a、无源表面1620b、及约为衬底厚度1604的一半的厚度。第一芯片1620的有源表面1620a在衬底开口1610中放置于粘著带表面1601a上，同时与衬底之间留有第一间隙1611。
接下来，提供第二半导体芯片1701(参见图17)，其具有包含结合焊垫1703的有源表面1701a、无源表面1701b、及约为衬底厚度1604的一半的厚度。通过粘著材料1710将第二芯片1701的无源表面1701b附连至第一芯片1620的无源表面1620b上，同时与衬底1602之间留有第二间隙1711。
如图18所示，通过丝焊元件1801桥接第二间隙1711，以将第二芯片1701的结合焊垫1703电连接至衬底路由条带1802。
接下来，如在图19中所示，使用囊封材料1901(例如环氧树脂)来填充第二间隙1711及第一间隙1611。间隙填充物界面1902与衬底的第一表面1602a及第一芯片1620的有源表面1620s共面。在同一工艺步骤中，材料1901囊封第二芯片1701的有源表面1701a及结合元件1801。在该阶段中，翻转所述组合件并移除支撑带1601。
在下一步骤中，通过结合元件2001来桥接第一间隙1611，以便将第一芯片1620的结合焊垫1630电连接至衬底路由条带2002，如在图20中所示。如图21所示，然后使用第二囊封步骤来囊封第一芯片1620的有源表面1620a及结合元件2001。该囊封步骤使衬底的接触焊垫1603仍保持外露。
作为最后的工艺步骤，图22图解说明在接触焊垫1603上附连焊料体2201。当各实施例(参见图24)使用在第二表面1602b上也具有接触焊垫2401的衬底1602时，也可将焊料体2402附连至这些接触焊垫2401上。焊料体方法可具有替代方法，例如当采用压力接点来实现与焊垫1603及2401中一者或二者的电接触时。
如前面所述，图23显示一其中由两个单独芯片2301及2302来取代图16中的第一芯片1602的实施例。类似于图16中所示的工艺步骤，将这两个芯片通过其有源表面附连至支撑带上，且类似于图20中所示的工艺步骤，在已移除支撑带之后，将这些芯片结合至衬底条带上。
尽管参照例示性实施例来说明本发明，然而本说明并非旨在视为具有限定意义。所属领域中的技术人员在阅读本说明后，将易知各例示性实施例的各种修改及组合形式、以及本发明的其他实施例。例如，可在将第一芯片放置于带上的步骤之后，对堆叠式多芯片实施例采用第一囊封步骤；该囊封步骤使用囊封材料填充第一间隙。打算使所请求的本发明囊括任何此种修改形式或实施例。

Claims (14)

1、一种半导体装置，其包含：
电绝缘衬底，其具有第一及第二表面以及至少一个穿过所述第一及第二表面的开口；
至少一个位于所述第一表面上的导电元件；
半导体芯片，其定位于所述至少一个开口内并通过边缘间隙与所述衬底隔开，所述芯片具有包含至少一个结合焊垫的第一表面及第二表面；
一个或多个结合元件，其跨越所述间隙将所述至少一个结合焊垫电连接至所述至少一个导电元件；及
囊封材料，其覆盖所述第一芯片表面及所述结合元件，并填充所述间隙。
2、如权利要求1所述的半导体装置，其中所述衬底与芯片相对地配置及放置，以便与所述衬底和芯片中每一者的第一及第二表面中的至少一者基本共面地形成所述囊封材料的间隙填充物表面。
3、如权利要求2所述的半导体装置，其进一步包含位于所述基本共面的表面上的散热器。
4、如权利要求1-3中任一权利要求所述的半导体装置，其中所述至少一个导电元件包含多个导电路由条带及多个分别电连接至所述路由条带的接触焊垫；所述芯片具有多个结合焊垫；且所述结合元件分别将所述芯片结合焊垫电连接至所述路由条带。
5、如权利要求4所述的半导体装置，其中所述囊封材料覆盖所述结合元件至所述路由条带的连接、但使所述接触焊垫暴露。
6、如权利要求4所述的半导体装置，其进一步包含设置于所述接触焊垫中至少一者上的焊料体。
7、如权利要求1所述的半导体装置，其中所述衬底具有厚度且所述芯片具有基本等于所述衬底厚度的厚度。
8、如权利要求1所述的半导体装置，其中所述至少一个开口包含多个开口，且所述装置包含多个分别定位于所述多个开口内并通过边缘间隙与所述衬底隔开的所述半导体芯片，结合元件将所述芯片的结合焊垫电连接至所述衬底上各自的导电元件，且所述囊封材料覆盖所述各自多个半导体芯片的第一芯片表面及所述结合元件并填充所述间隙。
9、如权利要求8所述的半导体装置，其中所述至少一个导电元件包含多个导电路由条带及多个分别电连接至所述路由条带的接触焊垫；且所述路由条带中的至少一者由所述结合元件共同地电连接至不同芯片的结合焊垫。
10、一种用于组装半导体装置的方法，其包含如下步骤：
提供具有一表面的支撑带；
提供电绝缘衬底，其具有第一及第二表面、至少一个穿过所述第一及第二表面的开口、及至少一个位于所述第一表面上的导电元件；
将所述衬底定位成所述第二衬底表面位于所述带表面上；
提供半导体芯片，所述半导体芯片具有包含至少一个结合焊垫的第一表面、及第二表面；
将所述半导体芯片定位于所述至少一个开口内、通过边缘间隙与所述衬底隔开，且使所述第二芯片表面位于所述带表面上；
使用一个或多个结合元件跨越所述间隙将所述至少一个结合焊垫电连接至所述至少一个导电元件；及
施加囊封材料，以覆盖所述第一芯片表面及所述结合元件并填充所述间隙。
11、如权利要求10所述的方法，其中所述衬底与芯片相对配置及定位，且所述囊封材料经施加以便与所述衬底和芯片的所述第二表面基本共面地形成所述囊封材料的间隙填充物表面。
12、如权利要求10或11所述的方法，其进一步包括在所述囊封材料施加步骤之后移除所述支撑带的步骤。
13、如权利要求10-12中任一权利要求所述的方法，其中选择性地实施所述施加步骤，以使所述多个接触焊垫保持暴露。
14、如权利要求10所述的方法，其中所述衬底设置有多个开口；所述半导体芯片提供及定位步骤包括提供多个分别定位于所述多个开口内、通过边缘间隙与所述衬底隔开的所述半导体芯片且使所述第二芯片表面位于所述带表面上；所述电连接步骤包括将所述芯片的结合焊垫电连接至所述衬底上各自的导电元件上；且所述施加步骤包括施加囊封材料来覆盖所述各自多个半导体芯片的所述第一芯片表面及所述结合元件并填充所述间隙。
CNA2005800332631A 2004-08-10 2005-08-02 低矮外形、芯片级封装及制作方法 Pending CN101032021A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/916,194 US7135781B2 (en) 2004-08-10 2004-08-10 Low profile, chip-scale package and method of fabrication
US10/916,194 2004-08-10

Publications (1)

Publication Number Publication Date
CN101032021A true CN101032021A (zh) 2007-09-05

Family

ID=35799237

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2005800332631A Pending CN101032021A (zh) 2004-08-10 2005-08-02 低矮外形、芯片级封装及制作方法

Country Status (4)

Country Link
US (2) US7135781B2 (zh)
CN (1) CN101032021A (zh)
TW (1) TWI270185B (zh)
WO (1) WO2006020452A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102651449A (zh) * 2011-02-23 2012-08-29 飞思卡尔半导体公司 Mram器件及其装配方法
CN102117877B (zh) * 2009-12-31 2012-12-05 钰桥半导体股份有限公司 半导体芯片组体
CN103560138A (zh) * 2013-11-19 2014-02-05 苏州晶方半导体科技股份有限公司 影像传感器封装结构及其封装方法
CN103560139A (zh) * 2013-11-19 2014-02-05 苏州晶方半导体科技股份有限公司 影像传感器封装结构及其封装方法
US9299735B2 (en) 2013-11-19 2016-03-29 China Wafer Level Csp Co., Ltd. Image sensor package structure and method
CN102651449B (zh) * 2011-02-23 2016-12-14 飞思卡尔半导体公司 Mram器件及其装配方法
CN106796879A (zh) * 2014-09-15 2017-05-31 美光科技公司 保护制造中半导体晶片的外围的方法以及相关制造中晶片及系统
WO2021227045A1 (zh) * 2020-05-15 2021-11-18 深圳市汇顶科技股份有限公司 半导体封装方法及其封装结构

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7453277B2 (en) * 2006-06-06 2008-11-18 Advanced Inquiry Systems, Inc. Apparatus for full-wafer test and burn-in mechanism
US20080197468A1 (en) * 2007-02-15 2008-08-21 Advanced Semiconductor Engineering, Inc. Package structure and manufacturing method thereof
JP4751351B2 (ja) * 2007-02-20 2011-08-17 株式会社東芝 半導体装置とそれを用いた半導体モジュール
WO2009001280A2 (en) * 2007-06-27 2008-12-31 Koninklijke Philips Electronics N.V. A method for the production of a microelectronic sensor device
KR100986829B1 (ko) * 2007-11-07 2010-10-12 삼성전기주식회사 반도체칩 및 이를 이용한 인쇄회로기판의 제조방법
TWI573201B (zh) 2008-07-18 2017-03-01 聯測總部私人有限公司 封裝結構性元件
US7847375B2 (en) * 2008-08-05 2010-12-07 Infineon Technologies Ag Electronic device and method of manufacturing same
KR20100059487A (ko) * 2008-11-26 2010-06-04 삼성전자주식회사 패키지 구조물
US10665475B2 (en) * 2014-06-11 2020-05-26 Texas Instruments Incorporated Quad flat no lead package and method of making
CN113491007A (zh) * 2019-03-11 2021-10-08 Hrl实验室有限责任公司 在金属嵌入式芯片组件(meca)处理期间保护晶粒的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072283A (en) * 1988-04-12 1991-12-10 Bolger Justin C Pre-formed chip carrier cavity package
TW258829B (zh) * 1994-01-28 1995-10-01 Ibm
WO1995026047A1 (en) * 1994-03-18 1995-09-28 Hitachi Chemical Company, Ltd. Semiconductor package manufacturing method and semiconductor package
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US6112972A (en) * 1996-12-19 2000-09-05 Texas Instruments Incorporated Wire bonding with capillary realignment
US5736785A (en) * 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
US5894108A (en) * 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US6585905B1 (en) * 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6294100B1 (en) * 1998-06-10 2001-09-25 Asat Ltd Exposed die leadless plastic chip carrier
US6057601A (en) * 1998-11-27 2000-05-02 Express Packaging Systems, Inc. Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
TW456013B (en) * 2000-07-04 2001-09-21 Advanced Semiconductor Eng Heat spreader substrate structure and the process thereof
US20050156322A1 (en) * 2001-08-31 2005-07-21 Smith Lee J. Thin semiconductor package including stacked dies
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US6723585B1 (en) * 2002-10-31 2004-04-20 National Semiconductor Corporation Leadless package
US6815836B2 (en) * 2003-03-24 2004-11-09 Texas Instruments Incorporated Wire bonding for thin semiconductor package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102117877B (zh) * 2009-12-31 2012-12-05 钰桥半导体股份有限公司 半导体芯片组体
CN102651449A (zh) * 2011-02-23 2012-08-29 飞思卡尔半导体公司 Mram器件及其装配方法
CN102651449B (zh) * 2011-02-23 2016-12-14 飞思卡尔半导体公司 Mram器件及其装配方法
CN103560138A (zh) * 2013-11-19 2014-02-05 苏州晶方半导体科技股份有限公司 影像传感器封装结构及其封装方法
CN103560139A (zh) * 2013-11-19 2014-02-05 苏州晶方半导体科技股份有限公司 影像传感器封装结构及其封装方法
CN103560138B (zh) * 2013-11-19 2016-01-20 苏州晶方半导体科技股份有限公司 影像传感器封装结构及其封装方法
US9299735B2 (en) 2013-11-19 2016-03-29 China Wafer Level Csp Co., Ltd. Image sensor package structure and method
CN103560139B (zh) * 2013-11-19 2016-04-13 苏州晶方半导体科技股份有限公司 影像传感器封装结构及其封装方法
CN106796879A (zh) * 2014-09-15 2017-05-31 美光科技公司 保护制造中半导体晶片的外围的方法以及相关制造中晶片及系统
WO2021227045A1 (zh) * 2020-05-15 2021-11-18 深圳市汇顶科技股份有限公司 半导体封装方法及其封装结构

Also Published As

Publication number Publication date
US20070020808A1 (en) 2007-01-25
US20060033219A1 (en) 2006-02-16
US7309648B2 (en) 2007-12-18
US7135781B2 (en) 2006-11-14
TW200620576A (en) 2006-06-16
TWI270185B (en) 2007-01-01
WO2006020452A1 (en) 2006-02-23

Similar Documents

Publication Publication Date Title
CN101032021A (zh) 低矮外形、芯片级封装及制作方法
TWI255020B (en) Stacked die semiconductor device
US7671451B2 (en) Semiconductor package having double layer leadframe
JP5227501B2 (ja) スタックダイパッケージ及びそれを製造する方法
US8786070B2 (en) Microelectronic package with stacked microelectronic elements and method for manufacture thereof
CN100479135C (zh) 半导体器件及其制造方法
TW201743420A (zh) 薄型扇出式多晶片堆疊封裝構造與製造方法
CN1455455A (zh) 中心焊点芯片的叠层球栅极阵列封装件及其制造方法
TW200919693A (en) Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same
CN1319890A (zh) 半导体器件和使用该半导体器件的半导体组件
CN107170769A (zh) 一种影像传感芯片的封装结构及其封装方法
CN106098717A (zh) 高可靠性芯片封装方法及结构
TW201123402A (en) Chip-stacked package structure and method for manufacturing the same
WO2022021799A1 (zh) 半导体封装方法及半导体封装结构
US7368322B2 (en) Method for mounting a chip on a base and arrangement produced by this method
TWI771901B (zh) 半導體裝置及半導體裝置之製造方法
TW200849503A (en) Package-on-package structure and method for making the same
CN108428690A (zh) 一种芯片的封装结构以及封装方法
CN104008982B (zh) 芯片封装工艺及芯片封装
US20130045572A1 (en) Flexible routing for high current module application
CN107919331A (zh) 无引线框架的表面安装半导体器件
TWI692042B (zh) 半導體封裝結構及其製作方法
CN101110369A (zh) 半导体封装件及其制法
CN1147931C (zh) 半导体器件及其制造方法
CN110634856A (zh) 一种倒装加打线混合型封装结构及其封装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication