CN1455455A - 中心焊点芯片的叠层球栅极阵列封装件及其制造方法 - Google Patents

中心焊点芯片的叠层球栅极阵列封装件及其制造方法 Download PDF

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CN1455455A
CN1455455A CN03100160A CN03100160A CN1455455A CN 1455455 A CN1455455 A CN 1455455A CN 03100160 A CN03100160 A CN 03100160A CN 03100160 A CN03100160 A CN 03100160A CN 1455455 A CN1455455 A CN 1455455A
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circuit substrate
chip
solder joint
grid array
ball grid
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CN100561737C (zh
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白亨吉
文起一
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SK Hynix Inc
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Abstract

一种中心焊点芯片的叠层球栅极阵列封装件及其制造方法。多个半导体芯片的芯片有效面彼此面对地各自粘着在上下部电路基板，多个芯片焊点用金属导线各自导电连接在上下部电路基板上，在上下部电路基板彼此结合的同时用形成在其间的凸块而进行导电连接，上部电路基板含于封装模内，下部电路基板其两侧端部分在封装模的下部侧露出。下部电路基板由具柔软性的绝缘薄膜构成，在下部电路基板的露出的两侧端部分形成锡球。在下部电路基板的两侧端部分结合有印刷电路基板，而在其下部面可形成多个锡球，下部电路基板形成导线架。该封装件可在单一封装件内将记忆容量增大为2倍以上，具有微细球栅极阵列封装件及中心焊点型半导体芯片的全部优点。

Description

中心焊点芯片的叠层球栅极阵列封装件及其制造方法
技术领域
本发明涉及半导体封装件，更具体地说，涉及将两个以上的中心焊点型半导体芯片予以叠层而实现微细球栅极阵列(fine ball grid array；FBGA)形态的叠层封装件的中心焊点芯片的叠层球栅极阵列封装件及其制造方法。
背景技术
在半导体产业中对集成电路芯片的封装(packaging)技术，为满足小型化的要求及封装可靠性而持续地发展着。同时，因电子制品的高性能化的推进，为在尺寸大小受限制的基板上封装更多的半导体而持续地努力着。作为此努力的一环提出有所谓的″叠层封装(stack package)″。
叠层封装为将相同大小及相同功能的记忆芯片予以叠层使记忆容量增大，或将大小及机能彼此不同的各种类型的半导体芯片组装成一个封装件，以使制品性能及效率达到最大化。叠层封装件因适用的制品，制造厂家等因素使得种类非常多样化。现有技术的叠层封装件的一例如图1所示。
图1表示叠层封装件10将单个封装件11、12予以叠层的封装叠层式，为TSOP(薄小外形封装)(thin small outline package)类型。在图1的叠层封装件10中，各自的单个封装件11、12为内藏有一个一个半导体芯片13使用LOC(lead-on-chip)(在芯片上的引脚)导线架(lead frame)。导线架的内部引脚14为靠粘着带15粘着在半导体芯片13的上部面且由金属导线16实现电气连接。叠层的单个封装件11、12使用另外的连接用引脚17而彼此电气连接。此时，连接用引脚17与各导线架的外部引脚18结合而成为叠层封装件10的外部连接端子。
但是，在此种类型的叠层封装件10中封装的组装面积宽且高度高，适用于要求小型化，薄型化的信息通信机器等系统有困难。且因使用导线架14、17、18，所以不适合于高速元件制品，由于自封装地点到上部封装件12的半导体芯片14的路径比封装地点至下部封装件11的半导体芯片13长，所以电气特性差。
因此，本发明以半导体封装件的表面封装面积最小化，且电气连接长度最小化以提高电气特性为目的提出在外部连接端子上使用锡球(solder ball)的球栅极阵列(ball grid array；BGA)封装件。基本上按照球栅极阵列封装的形态在封装件的内部叠层半导体芯片的所谓的″芯片的叠层球栅极阵列封装件″如图2所示。
如图2所示，芯片的叠层球栅极阵列封装件20为在封装模27的内部将单个半导体芯片23，24予以叠层的叠层式芯片，且利用印刷电路基板21和锡球28取代导线架。在形成有配线22的印刷电路基板21上，使用粘着剂25粘着下部半导体芯片23，且在下部半导体芯片23上粘着上部半导体芯片24。各半导体芯片23、24用金属导线26与印刷电路基板21的配线22形成电气连接，在印刷电路基板21的下部面形成多个锡球28而与配线22作电气连接，成为封装件20件的外部连接端子。
但是，此种类型的芯片的叠层球栅极阵列封装件20仅能使用所谓的″侧焊点(side pad)型半导体芯片″。在如DRAM的半导体芯片的有效面(activesurface)上，虽然形成多个充当与外部作输入输出的芯片焊点(chip pad)23a、24a，但是在芯片有效面的缘部形成有以芯片焊点(23a、24a)的侧焊点型半导体芯片23、24。
然而，为更有利实现近来高速元件普遍形成芯片焊点沿着芯片有效面中央所形成所谓的″中心焊点型半导体芯片″，但是在图2所示的现有的芯片的叠层球栅极阵列封装件20中，由于芯片的叠层困难及金属导线的长度变长的问题，所以具有不能使用此类型的中心焊点型半导体芯片的缺点。而且，此种封装件20的类型因热应力集中在封装件的上部，而产生封装件翘曲(warpage)现象。
因此，在现有技术中，实际上仅利用1个中心焊点型半导体芯片来实现球栅极阵列封装。有关中心焊点芯片的球栅极阵列封装件的实例如图3所示。
如图3所示，中心焊点芯片的球栅极阵列封装件30将形成有芯片焊点32a的半导体芯片32的有效面粘着在电路基板31后，用金属导线33将半导体芯片32和电路基板31作电气连接。半导体芯片32和金属导线33受封装模34保护，作成在电路基板31形成有作为外部连接端子的锡球35的球栅极阵列封装件的形态。
发明内容
如以上的说明，叠层封装件、球栅极阵列封装件和中心焊点型半导体芯片虽各自具有自身的优点，但是实现同时满足以上3个要求的封装件普遍认为从其构造方面或制造成本以工序安全性方面考虑是非常困难的。
因此，本发明的目的提供一种可全部具有叠层封装件的优点和微细球栅极阵列封装件的优点以及中心焊点型半导体芯片优点的新类型的中心焊点芯片的叠层球栅极阵列封装件及其制造方法。
为达到本目的，本发明提供一种叠层包括有沿各自芯片有效面中央所形成的多芯片焊点的两个中心焊点型半导体芯片，以实现微细球栅极阵列封装件。在本发明的中心焊点芯片的叠层球栅极阵列封装件中，多个半导体芯片以芯片有效面彼此相互面对地各自粘着在上下部电路基板，多个芯片焊点用金属导线各自导电连接在上下部电路基板上，上下部电路基板相互结合且用形成在其间的凸块进行导电连接，上部电路基板在封装模内，下部电路基板其两侧端部分在封装模的下部侧露出。
在本发明的中心焊点芯片的叠层球栅极阵列封装件中，下部电路基板由具柔软性的绝缘薄膜构成，在下部电路基板露出的两侧端部分可形成多个锡球。而且，在下部电路基板的两侧端部分结合印刷电路基板，在印刷电路基板的下部面上可形成多个锡球。下部电路基板可形成导线架。
本发明提供一种叠层包括有沿各自芯片有效面中央所形成的多芯片焊点的两个中心焊点型半导体芯片，以实现微细球栅极阵列封装件的制造方法。本发明的制造方法具有：以芯片有效面彼此相互面对方式将多个半导体芯片各自粘着在上下部电路基板的步骤；用金属导线将多个芯片焊点各自电气连接在上下部电路基板的步骤；用凸块使上下部电路基板彼此以可导电方式结合的步骤；以上部电路基板包括在封装模内，且下部电路基板在两侧端部分在封装模的下部侧露出的方式形成封装模的步骤。
本发明的制造方法包括：提供上下部电路基板带片的步骤，其中各个孔和窗形成一定间隔，基板焊点、配线、以及连接焊点形成一定的图案，且形成多个上下部电路基板，而该配线是延伸至该下部电路基板的孔内部，且形成球陆，且在该连接焊点形成有凸块；
半导体芯片粘着步骤，其多个芯片焊点穿过窗露出，在该电路基板带片的各电路基板进行粘着；
导电连接基板焊点步骤，其用金属导线将露出的多个芯片焊点用导电方式与该多个基板焊点连接；
导电连接上下部电路基板步骤，其使半导体芯片彼此相互面对使上下部电路基板彼此粘着，且由凸块将上下部电路基板用导电方式连接；
形成封装模步骤，其用孔按压下部电路基板的球陆，以使延伸至下部电路基板的孔内的配线朝下方弯曲的方式使球陆露出形成封装模；
在球陆形成多个锡球的步骤；由该电路基板带片将各自的单个封装件分离的步骤。
此时，形成封装模的步骤最好包括：以使各自的电路基板位在模制装置的铸孔内的方式，将该上下部电路基板带片提供于以上下部铸模所构成的模制装置内的步骤；以使该下部电路基板的球陆顶接该下部铸模的方式，使形成在该上部铸模的加压部、透过该电路基板带片的孔来按压该球陆的步骤；透过该模制装置的注入口，将液状模制树脂注入该铸孔内，使其硬化以形成该封装模等步骤。
以上的本发明的目的和其它特征以及优点等等可参考以下的本发明理想实施例的说明会更明确
附图说明
图1是现有技术的叠层封装件实例的剖面图；
图2是现有技术的芯片的叠层球栅极阵列封装件的剖面图；
图3是现有技术的中心焊点芯片的球栅极阵列封装件的剖面图；
图4是本发明第1实施例的中心焊点芯片的叠层球栅极阵列封装件的剖面图；
图5是图4所示的中心焊点芯片的叠层球栅极阵列封装件的制造方法的工序图，表示在上下部电路基板粘着各自半导体芯片的后，以导线连接状态的剖面图；
图6是图4所示的中心焊点芯片的叠层球栅极阵列封装件的制造方法的工序图，是在本实施例的制造方法所使用的上下部电路基板带片的示意平面图；
图7是图4所示的中心焊点芯片的叠层球栅极阵列封装件的制造方法的工序图，表示上下部电路基板彼此粘着状态的剖面图；
图8是图4所示的中心焊点芯片的叠层球栅极阵列封装件的制造方法的工序图，是表示在按压下部电路基板的同时进行模制工序的状态的示意剖面图；
图9为本发明第2实施例的中心焊点芯片的叠层球栅极阵列封装件的剖面图；
图10为本发明第3实施例的中心焊点芯片的叠层球栅极阵列封装件的剖面图。
具体实施方式
以下，参考附图详细说明本发明的理想实施例。在附图一部份的构成要素中，为了有助于明确理解，多少将图面夸张地示意性地图示，因此并未全部反映其实际尺寸大小。
(第1实施例)
图4是表示本发明第1实施例的中心焊点芯片的叠层球栅极阵列封装件的剖面图。参考图4，将两个中心焊点型半导体芯片102、104叠层以实现微细球栅极阵列封装件100。
半导体芯片102、104的芯片焊点106、108沿着芯片有效面中央形成，两个半导体芯片102、104的芯片有效面以彼此相互面对方式各自粘着在上下部电路基板112、122上。半导体芯片102、104的芯片焊点106、108用金属导线130各自导电连接在上下部电路基板112、122上。彼此结合的上下部电路基板112、122用形成在其间的凸块140形成导电连接。上部电路基板112具有几乎类似半导体芯片104的大小，且完全置于封装模150内，下部电路基板122其两侧端部分在封装模150的下部侧露出。在露出的下部电路基板122上形成多个锡球160作为封装件100的外部连接端子起作用。
本实施例的封装件100按如下方法制造。由以下说明的制造方法可使封装件的构造更加明确。图5至图8是表示图4中显示的中心焊点芯片的叠层球栅极阵列封装件的制造方法的工序图。
首先，如图5的剖面图所示，在上下部电路基板112、122上粘着各个半导体芯片104、102后，与金属导线130连接。如图6的平面图所示，上下部电路基板112、122各自以电路基板带片(strip)110、120的形态形成。
电路基板带片110、120是在卷筒(reel)形态的绝缘薄膜上以一定间隔形成孔(hole)111、121及窗(window)113、123；基板焊点114、124，配线115、125、128，连接焊点116、126，以及球陆(ballland)127以一定图案形成，形成多个电路基板112、122。与上部电路基板带片110不同，下部电路基板带片120的特征为配线128延伸至孔121的内部且形成球陆127。绝缘薄膜以具有柔软性的聚合物(polymer)材料构成，基板焊点114、124，配线115、125、128，连接焊点116、126，以及球陆127均由铜作成。
在电路基板带片110、120的各电路基板112、122上粘着半导体芯片104、102，各半导体芯片104、102的芯片焊点106、108是通过电路基板带片110、120的窗113、123而露在外部。露出的芯片焊点106、108用金属导线130与基板焊点114、124形成导电连接。此外，在图5及图6未图示的，在上下部电路基板112、122的任一方或两侧的连接焊点116、126上，形成有使上下部电路基板112、122导电连接的凸块(图7的140)。可在连接焊点116、126上镀锡以取代凸块。
然后，如图7的剖面图所示，半导体芯片102、104以彼此相互面对的方式使上下部电路基板112、122彼此粘着。上下部电路基板112、122由施加热及压力而彼此粘接且由凸块140形成导电连接。图7仅显示了一个上下部电路基板112、122，而在图6所图示的电路基板带片110、120的状态下进行粘接最为理想。
接着，一边按压下部电路基板一边进行模制工序。如图8所示，彼此粘着的上下部电路基板带片110、120置于由上下部制模220、210所构成的模制装置内，此时，粘着有半导体芯片102、104的各个电路基板112、122位于模制装置的铸孔(cavity)230内。另外，由于形成在上部制模220的加压部222通过电路基板带片110、120的孔111、121而按压下部电路基板122的球陆127，所以延伸至下部电路基板122的孔121内的配线128在朝下方弯曲的同时球陆127顶接下部制模210。
在此种状态下，通过注入口(未图示)将液状模制树脂注入铸孔230内的后使其硬化，则形成如图4所示的封装模150，且下部电路基板122的球陆127在封装模150的下部侧露出。接着，露在外部的球陆127上形成锡球160，且从电路基板带片110、120分别将多个单个封装件100分离。
(第2实施例)
图9是表示本发明第2实施例的中心焊点芯片的叠层球栅极阵列封装件300的剖面图。在图9中，与前述第1实施例相同的构成要素使用同一编号。参考图9，为使工艺性优越使用另外的印刷电路基板170，使下部电路基板122的两侧端部分与印刷电路基板170结合以形成封装模150。锡球160取代球陆在印刷电路基板170的下部面形成。
(第3实施例)
图10是表示本发明第3实施例的中心焊点芯片的叠层球栅极阵列封装件400的剖面图。在图10中，在与前述第1实施例相同的构成要素上是使用同一编号。依据图10，使用导线架180取代由绝缘薄膜构成的下部电路基板，在封装模150外面露出的导线架180的两侧端部分，用锡膏(solder paste)190来取代锡球直接结合于外部基板500上。外部基板500为组装有封装件100、300、400使用的系统基板。在第3实施例使用的导线架180中与半导体芯片102连接的部分进行往上成型(up-set)加工。
由以上说明可了解，本发明的中心焊点芯片的叠层球栅极阵列封装件可使用中心焊点型半导体芯片以具体实现芯片叠层球栅极阵列封装件。
本发明的封装件为在单一封装内可使记忆容量增大为2倍以上的叠层封装件，具备微细球栅极阵列封装件的优点及中心焊点型半导体芯片的全部优点。
因为封装件内部的半导体芯片形成上下对称构造，所以可使温度变化造成的封装件翘曲现象成为最小，特别是在第1实施例的封装件的情况下，尽管由封装件的中央到最外围的锡球为止的距离大但因在锡球的上侧不存在有半导体芯片，所以仍具有锡球结合可靠性高的优点。
而且，因在进行模制工序的同时弯曲下部电路基板，所以锡球的形成工序可容易实现。在把上下部电路基板进行导电连接时，通过以热压方式使其粘着形成在电路基板的凸块，所以可确保充分的可靠性。
在本说明书及附图上揭示了本发明的最佳实施例，即便使用了多个特定用语，其只是使用了容易说明本发明的技术内容且为有助益理解发明的一般意思，并非对本发明的范围进行限定。很明显，除在此所揭示的实施例以外，对具有属于本发明的技术领域的一般知识的技术人员，是可依据本发明的技术思想而实施其它变形例。

Claims (9)

1、一种中心焊点芯片的叠层球栅极阵列封装件，叠层包括有沿各自芯片有效面中央所形成的多芯片焊点的两个中心焊点型半导体芯片，以实现微细球栅极阵列封装件，其特征在于：
所述多个半导体芯片所述芯片有效面以彼此相互面对地各自粘着在上下部电路基板，所述多个芯片焊点用金属导线各自导电连接在所述上下部电路基板，所述上下部电路基板彼此相互结合，且用其间所形成的凸块而导电连接，所述上部电路基板在封装模内，所述下部电路基板其两侧端部分是在所述封装模的下部侧露出。
2、如权利要求1所述的中心焊点芯片的叠层球栅极阵列封装件，其中，所述下部电路基板由具柔软性的绝缘薄膜构成。
3、如权利要求2所述的中心焊点芯片的叠层球栅极阵列封装件，其中，在所述下部电路基板的露出的两侧端部分形成有多个锡球。
4、如权利要求2所述的中心焊点芯片的叠层球栅极阵列封装件，其中，所述下部电路基板的两侧端部分与印刷电路基板结合。
5、如权利要求4所述的中心焊点芯片的叠层球栅极阵列封装件，其中，在所述印刷电路基板的下部面上形成有多个锡球。
6、如权利要求2所述的中心焊点芯片的叠层球栅极阵列封装件，其中，所述下部电路基板形成导线架。
7、一种中心焊点芯片的叠层球栅极阵列封装件的制造方法，该方法叠层包括有沿各自芯片有效面中央所形成的芯片焊点的两个中心焊点型半导体芯片而制造微细球栅极阵列封装件，其特征在于，具有：以所述芯片有效面彼此相互面对方式将所述多个半导体芯片各自粘着在上下部电路基板的步骤；用金属导线将所述多个芯片焊点各自导电连接在所述上下部电路基板的步骤；用凸块以可导电方式将所述上下部电路基板彼此结合的步骤；以所述上部电路基板包括在封装模内，且所述下部电路基板是在两侧端的部分在所述封装模的下部侧露出方式形成所述封装模的步骤。
8、一种中心焊点芯片的叠层球栅极阵列封装件的制造方法，该方法叠层包括有沿各自芯片有效面中央所形成的多个芯片焊点的两个中心焊点型半导体芯片而制造微细球栅极阵列封装件，其特征在于，具有：
提供上下部电路基板带片的步骤，其中各个孔和窗形成一定间隔，基板焊点、配线、以及连接焊点形成一定的图案，且形成多个上下部电路基板，而所述配线是延伸至所述下部电路基板的孔内部，且形成球陆，且在所述连接焊点形成有凸块；
所述半导体芯片粘着步骤，其所述多个芯片焊点透过所述窗露出，在所述电路基板带片的各电路基板粘着；
导电连接所述多个基板焊点步骤，其用金属导线将露出的多个芯片焊点作电气连接；
导电连接上下部电路基板步骤，其使所述半导体芯片彼此相互面对使所述上下部电路基板彼此粘着，且由所述凸块将所述上下部电路基板作电气连接；
形成封装模步骤，其用所述孔按压所述下部电路基板的所述球陆，以使延伸至所述下部电路基板的孔内的配线朝下方弯曲的方式使所述球陆露出形成封装模；
在所述球陆形成多个锡球的步骤；
由所述电路基板带片将各自的单个封装件分离的步骤。
9、如权利要求8所述的中心焊点芯片的叠层球栅极阵列封装件的制造方法，其中，形成所述封装模的步骤包括：使所述各自的电路基板位在模制装置的铸孔内的方式，将所述上下部电路基板带片提供于以上下部铸模所构成的模制装置内的步骤；以使所述下部电路基板的球陆顶接所述下部铸模的方式，使形成在所述上部铸模的加压部透过所述电路基板带片的孔来按压所述球陆的步骤；透过所述模制装置的注入口，将液状模制树脂注入所述铸孔内，使其硬化以形成所述封装模的步骤。
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