CN110634856A - 一种倒装加打线混合型封装结构及其封装方法 - Google Patents

一种倒装加打线混合型封装结构及其封装方法 Download PDF

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CN110634856A
CN110634856A CN201910901464.2A CN201910901464A CN110634856A CN 110634856 A CN110634856 A CN 110634856A CN 201910901464 A CN201910901464 A CN 201910901464A CN 110634856 A CN110634856 A CN 110634856A
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郭海军
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Huatian Technology Xian Co Ltd
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Abstract

本发明公开了一种倒装加打线混合型封装结构及其封装方法，封装结构包括：基板，基板上开设窗口，第一倒装芯片设置在窗口内，第一倒装芯片上设置有若干第一铜柱；第二倒装芯片贴装在第一倒装芯片和基板上，第二倒装芯片上设置若干第二铜柱；第一倒装芯片的第一铜柱与第二倒装芯片电性连接，第二倒装芯片的第二铜柱与基板电性连接；打线芯片，两个打线芯片贴装在第二倒装芯片上；第一金属线分别电连接打线芯片和基板；塑封胶体包覆基板、第一倒装芯片、第二倒装芯片、打线芯片和第一金属线，塑封胶体下表面裸露第一倒装芯片的芯片硅面。该结构实现芯片在基板上的多层堆叠，确保封装之后结构平衡，避免封装结构导致的翘曲和内部芯片的异常。

Description

一种倒装加打线混合型封装结构及其封装方法
技术领域
本发明属于发明型技术领域，涉及一种半导体封装领域，尤其涉及一种倒装加打线混合型封装结构及其封装方法。
背景技术
随着科技的进步，当前半导体发展的趋势是越来越向多芯片模块堆叠方向发展。系统集成(SIP)封装将成为业界主流发展趋势。倒装(FC)芯片由于其I/OPad向下并直接与基板相连，从而基板上很难在封装体的高度方向上发展，只能将各个功能芯片平铺在基板表面上，再通过基板内部走线完成连接。
由于对封装外形尺寸的限制，在同一个封装体内平铺不同功能的芯片将变得及其困难，因此，芯片的堆叠成为一种发展的必然趋势。
发明内容
为解决现有技术存在的不能在同一个封装体内平铺不同功能的芯片的问题，本发明的第一个目的是提供一种倒装加打线混合型封装结构，该结构实现芯片在基板上的多层堆叠，确保封装之后结构平衡，避免封装结构导致的翘曲和内部芯片的异常。
本发明的第二个目的是提供一种倒装加打线混合型封装结构的封装方法，该方法可以实现倒装加打线混合型封装结构的快速封装，提高产品的可靠性。
为实现上述目的，本发明采用以下技术手段：
一种倒装加打线混合型封装结构，包括：
基板，所述基板上开设窗口，
第一倒装芯片，所述第一倒装芯片设置在所述窗口内，第一倒装芯片的上具有若干第一铜柱；
第二倒装芯片，所述第二倒装芯片贴装在基板上，第一倒装芯片贴装到第二倒装芯片上；第二倒装芯片的上具有若干第二铜柱；第一倒装芯片的第一铜柱与第二倒装芯片电性连接，第二倒装芯片的第二铜柱与基板电性连接；
打线芯片，两个所述打线芯片贴装在第二倒装芯片上；
第一金属线，所述第一金属线分别电连接打线芯片和基板；
及塑封胶体，所述塑封胶体包覆基板、第一倒装芯片、第二倒装芯片、打线芯片和第一金属线，所述塑封胶体下表面裸露第一倒装芯片的芯片硅面。
作为本发明的进一步改进，所述的第二倒装芯片的长度大于窗口的长度。
作为本发明的进一步改进，所述的第一铜柱端部设置有第一锡帽，第一锡帽与第二倒装芯片的焊盘连接。
作为本发明的进一步改进，所述的第二铜柱端部设置有第二锡帽，第二锡帽与基板的焊盘连接。
作为本发明的进一步改进，所述的打线芯片通过粘接胶贴装在第二倒装芯片上。
作为本发明的进一步改进，两个所述的打线芯片之间通过第二金属线互连。
作为本发明的进一步改进，所述的基板底部植有若干锡球。
作为本发明的进一步改进，所述的打线芯片的端部伸出第二倒装芯片的外部。
一种倒装加打线混合型封装结构的封装方法，包括以下步骤：
在第二倒装芯片和第一倒装芯片上制作铜柱；
在基板上挖出窗口；
将第二倒装芯片和基板进行贴装，使得第二倒装芯片的第二铜柱与基板电性连接；
将第一倒装芯片通过窗口和第二倒装芯片进行贴装，使得第一倒装芯片的第一铜柱与第二倒装芯片电性连接；
在第二倒装芯片上分别贴装两个打线芯片；
将打线芯片通过第一金属线与基板进行连接；
通过塑封胶体将芯片都密封在塑封料内，并使得第一倒装芯片的芯片硅面裸露。
与现有技术相比，本发明具有以下优点：
本发明采用在基板上开窗的方式，设置一个倒装芯片，再通过第二倒装芯片贴装在第一倒装芯片，第二倒装芯片上设置两个打线芯片，合理的空间布局，可以在有限的封装尺寸和高度范围内，堆叠四颗芯片，减小了产品的封装尺寸。整体封装结构相对对称，保证了封装后的结构平衡，避免封装产品的翘曲和内部芯片的碎裂，提高了产品可靠性，降低了生产成本。
本发明的封装方法可以实现倒装加打线混合型封装结构的快速封装，提高产品的可靠性,且有利于产品散热。
附图说明
图1是本发明的结构剖视图；
图2是上层和第一倒装芯片位置示意图；
图3是上层和第一倒装芯片制作铜柱示意图；
图4是基板加工过程挖出所需尺寸的窗口示意图；
图5是第二倒装芯片和基板进行贴装示意图；
图6是第一倒装芯片通过基板挖的窗口和第二倒装芯片进行贴装示意图；
图7是在第二倒装芯片硅面铺上粘接胶示意图；
图8是打线芯片通过金属线与基板进行连接示意图；
图9是整体塑封示意图；
图10是最后在基板面进行植球示意图；
其中，1、基板，2、第二铜柱，3、第二锡帽，4、第一铜柱，5、第一锡帽，6第二倒装芯片，7、第一倒装芯片，8、第一打线芯片，9、第一粘接胶，10、第二打线芯片，11、第二粘接胶，12、第二金属线，13、第一金属线，14、塑封料，15、锡球，16、窗口。
具体实施方式
实施例1
如图1所示，一种倒装加打线混合型封装结构，包括：
基板1，所述基板1上开设窗口16，
第一倒装芯片7，所述第一倒装芯片7设置在所述窗口16内，第一倒装芯片7上设置有若干第一铜柱4；
第二倒装芯片6，所述第二倒装芯片6贴装在第一倒装芯片7和基板1上，第二倒装芯片6上设置若干第二铜柱2；第一倒装芯片7的第一铜柱4与第二倒装芯片6电性连接，第二倒装芯片6的第二铜柱2与基板1电性连接；
打线芯片，两个所述打线芯片贴装在第二倒装芯片6上。具体地，第一打线芯片8和第二打线芯片10贴装在第二倒装芯片6上；
第一金属线13，所述第一金属线13分别电连接打线芯片和基板1；
塑封胶体14，所述塑封胶体14包覆基板1、第一倒装芯片7、第二倒装芯片6、打线芯片和第一金属线13，所述塑封胶体14下表面裸露第一倒装芯片7的芯片硅面。两个所述的打线芯片之间还可以通过第二金属线12互连。基板1底部植有若干锡球15。
作为优选地实施例，所述的第二倒装芯片6的长度大于窗口16的长度，第二倒装芯片6的宽度大于窗口16的宽度。
优选的，第一铜柱4端部设置有第一锡帽5，第一锡帽5与第二倒装芯片6的焊盘连接。第二铜柱2端部设置有第二锡帽3，第二锡帽3与基板1的焊盘连接。
优选的，所述的打线芯片通过粘接胶贴装在第二倒装芯片6上。粘接胶可以为Epoxy胶。
优选地，打线芯片的端部伸出第二倒装芯片6的外部。
具体地，第一倒装芯片7正面上设置有若干第一铜柱4；第一铜柱4与第一倒装芯片7正面(第一面指正面)的电路电连接；第二倒装芯片6的正面上设置若干第二铜柱2，第二铜柱2与第二倒装芯片6正面电路电连接；贴装时，第一倒装芯片7与第二倒装芯片6正面相对，通过回流方式进行连接。
实施例2
如图2至图10所示，本发明还提供一种倒装加打线混合型封装结构的封装方法，包括以下步骤：
在第二倒装芯片6和第一倒装芯片7上制作铜柱；
在基板1上挖出窗口16；
将第二倒装芯片6和基板1进行贴装，使得第二倒装芯片6的第二铜柱2与基板1电性连接；
将第一倒装芯片7通过窗口16和第二倒装芯片6进行贴装，使得第一倒装芯片7的第一铜柱4与第二倒装芯片6电性连接；
在第二倒装芯片6上分别贴装两个打线芯片；
将打线芯片通过第一金属线13与基板1进行连接；
通过塑封胶体14将芯片都密封在塑封料内，并使得第一倒装芯片7的芯片硅面裸露。
实施例3
如图1所示，一种倒装加打线混合型封装结构，包括基板1，基板1上挖出窗口16，基板1上封装两层芯片，倒装芯片与打线芯片间堆叠。两层芯片中的第二倒装芯片6的长度大于第一倒装芯片7的长度，第二倒装芯片6通过铜柱1与基板1上的PAD相连接，第一倒装芯片7通过基板1挖开的窗口16与第二倒装芯片6的焊盘通过铜柱2相连。
再在第二倒装芯片6铺上Epoxy胶9和Epoxy胶11，用于固定打线芯片8/10，打线芯片通过第一金属线13与基板1焊盘相连，第一打线芯片8、第二打线芯片10间也可以通过第二金属线12互连。这些芯片与基板1间再通过塑封胶体14填充，从而形成对芯片的密封。第一倒装芯片7采用open mold工艺，露出芯片硅面，以利于倒装芯片散热。
实施例4
本发明的一种倒装加打线混合型封装结构的封装方法，包括以下步骤：
1.第二倒装芯片6和第一倒装芯片7制作铜柱和锡帽，如图2至图3所示；
2.制作基板1结构，基板1加工过程挖出所需尺寸的窗口16，如图4所示；
3.第二倒装芯片6和基板1进行贴装，通过加热方式进行连接，如图5所示；
4.第一倒装芯片7通过基板挖的窗口16和第二倒装芯片6进行贴装，通过加热方式进行连接，如图6所示；
5.在第二倒装芯片6硅面铺上粘接胶，分别贴装两个打线芯片，如图7所示；
6.打线芯片通过金属线13与基板1进行连接，两个打线芯片间也可以通过金属线进行连接，如图8所示；
7.整体塑封，将芯片都密封在塑封料内，采用Open mold工艺，将第一倒装芯片7硅面露出，便于产品散热，如图9所示；
8.最后在基板面进行植有锡球15形成产品管脚，如图10所示。
本发明通过将基板挖窗口的方式，实现了上第一倒装芯片的连接。采用常规的芯片贴装工艺，实现了倒装芯片和打线芯片的堆叠，再使用open mold工艺，将第一倒装芯片的硅面露出，满足产品高散热的要求。整体封装结构相对对称，保证了封装后的结构平衡。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (9)

1.一种倒装加打线混合型封装结构，其特征在于，包括：
基板(1)，所述基板(1)上开设窗口(16)，
第一倒装芯片(7)，所述第一倒装芯片(7)设置在所述窗口(16)内，第一倒装芯片(7)的上具有若干第一铜柱(4)；
第二倒装芯片(6)，所述第二倒装芯片(6)贴装在基板(1)上，第一倒装芯片(7)贴装到第二倒装芯片(6)上；第二倒装芯片(6)的上具有若干第二铜柱(2)；第一倒装芯片(7)的第一铜柱(4)与第二倒装芯片(6)电性连接，第二倒装芯片(6)的第二铜柱(2)与基板(1)电性连接；
打线芯片，两个所述打线芯片贴装在第二倒装芯片(6)上；
第一金属线(13)，所述第一金属线(13)分别电连接打线芯片和基板(1)；
及塑封胶体(14)，所述塑封胶体(14)包覆基板(1)、第一倒装芯片(7)、第二倒装芯片(6)、打线芯片和第一金属线(13)，所述塑封胶体(14)下表面裸露第一倒装芯片(7)的芯片硅面。
2.根据权利要求1所述的一种倒装加打线混合型封装结构，其特征在于，所述的第二倒装芯片(6)的长度大于窗口(16)的长度。
3.根据权利要求1所述的一种倒装加打线混合型封装结构，其特征在于，所述的第一铜柱(4)端部设置有第一锡帽(5)，第一锡帽(5)与第二倒装芯片(6)的焊盘连接。
4.根据权利要求1所述的一种倒装加打线混合型封装结构，其特征在于，所述的第二铜柱(2)端部设置有第二锡帽(3)，第二锡帽(3)与基板(1)的焊盘连接。
5.根据权利要求1所述的一种倒装加打线混合型封装结构，其特征在于，所述的打线芯片通过粘接胶贴装在第二倒装芯片(6)上。
6.根据权利要求1所述的一种倒装加打线混合型封装结构，其特征在于，两个所述的打线芯片之间通过第二金属线(12)互连。
7.根据权利要求1所述的一种倒装加打线混合型封装结构，其特征在于，所述的基板(1)底部植有若干锡球(15)。
8.根据权利要求1所述的一种倒装加打线混合型封装结构，其特征在于，所述的打线芯片的端部伸出第二倒装芯片(6)的外部。
9.一种倒装加打线混合型封装结构的封装方法，其特征在于，包括以下步骤：
在第二倒装芯片(6)和第一倒装芯片(7)上制作铜柱；
在基板(1)上挖出窗口(14)；
将第二倒装芯片(6)和基板(1)进行贴装，使得第二倒装芯片(6)的第二铜柱(2)与基板(1)电性连接；
将第一倒装芯片(7)通过窗口(16)和第二倒装芯片(6)进行贴装，使得第一倒装芯片(7)的第一铜柱(4)与第二倒装芯片(6)电性连接；
在第二倒装芯片(6)上分别贴装两个打线芯片；
将打线芯片通过第一金属线(13)与基板(1)进行连接；
通过塑封胶体(14)将芯片都密封在塑封料内，并使得第一倒装芯片(7)的芯片硅面裸露。
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