TW201743420A - 薄型扇出式多晶片堆疊封裝構造與製造方法 - Google Patents

薄型扇出式多晶片堆疊封裝構造與製造方法 Download PDF

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TW201743420A
TW201743420A TW105117422A TW105117422A TW201743420A TW 201743420 A TW201743420 A TW 201743420A TW 105117422 A TW105117422 A TW 105117422A TW 105117422 A TW105117422 A TW 105117422A TW 201743420 A TW201743420 A TW 201743420A
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wafer
fan
protective layer
bonding wires
dummy spacer
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TW105117422A
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TWI567897B (zh
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莊詠程
張家維
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力成科技股份有限公司
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Priority to TW105117422A priority Critical patent/TWI567897B/zh
Priority to US15/361,073 priority patent/US9716080B1/en
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Publication of TW201743420A publication Critical patent/TW201743420A/zh

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Abstract

揭示一種薄型扇出式多晶片堆疊封裝構造，包含相互堆疊之複數個晶片，當晶片堆疊，該些晶片之電極與上晶片之主動面為顯露。虛置間隔片設置於主動面上。每一銲線各具有一接合至晶片電極之接合線頭與一體連接之垂直線段。封膠體密封晶片堆疊體與銲線並具有一平坦面，銲線之複數個研磨斷面與虛置間隔片之一表面顯露於平坦面。重配置線路結構形成於平坦面上，保護層覆蓋平坦面與虛置間隔片之表面但顯露出研磨斷面，扇出線路形成於保護層上並連接至研磨斷面。因此，可以改善垂直銲線模封沖線之問題。

Description

薄型扇出式多晶片堆疊封裝構造與製造方法
本發明係有關於半導體晶片封裝領域，特別係有關於一種薄型扇出式多晶片堆疊封裝構造與製造方法。
在習知的多晶片堆疊封裝構造中，複數個半導體晶片逐一往上堆疊在一基板上，並且該些晶片之主動面係朝上，並以打線形成之完整銲線電性連接該些晶片至該基板，通常銲線的接合線頭接合於晶片銲墊，銲線的線尾端接合於基板之接指，銲線的線段為弧形。然而，以此種方式形成的多晶片堆疊封裝構造之厚度包含了基板厚度與打線弧高而無法降低，並且特別在需要長銲線的場合，在形成封膠體時，容易發生沖線而產生短路等問題。
為了解決上述之問題，本發明之主要目的係在於提供一種薄型扇出式多晶片堆疊封裝構造與製造方法，可以改善特定封裝類型中的垂直銲線模封沖線之問題，而使得薄型扇出式多晶片堆疊封裝構造的製造有較佳的穩定度與良率。
本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種薄型扇出式多晶片堆疊封裝構造，包含一晶片堆疊體、一虛置間隔片、複數個不完整銲線、一封膠體以及一重配置線路結構。該晶片堆疊體係由複數個晶片堆疊所組成，每一晶片係具有一主動面以及至少一位於該主動面之電極，其中一第一晶片之至少一電極係不被一第二晶片覆蓋，並且該第二晶片之一主動面係亦不被堆疊覆蓋。該虛置間隔片係設置於該第二晶片之該主動面上，其中該第二晶片之至少一電極係不被該虛置間隔片覆蓋。每一不完整銲線係具有一接合線頭與一垂直線段，該些不完整銲線之該些接合線頭係接合至該些晶片之該些電極並一體連接對應之垂直線段。該封膠體係密封該晶片堆疊體與該些不完整銲線，該封膠體係具有一平坦面，並且該些不完整銲線之複數個研磨斷面與該虛置間隔片係共平面顯露於該平坦面。該重配置線路結構係形成於該平坦面上，該重配置線路結構係包含複數個扇出線路、一第一保護層以及一第二保護層，其中該第一保護層係覆蓋該平坦面與該虛置間隔片但顯露出該些研磨斷面，該些扇出線路係形成於該第一保護層上，並透過該第一保護層連接至該些不完整銲線之該些研磨斷面，該第二保護層係形成於該第一保護層上並覆蓋該些扇出線路。本發明另揭示上述薄型扇出式多晶片堆疊封裝構造之製造方法。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述薄型扇出式多晶片堆疊封裝構造中，可另包 含複數個外接端子，係可接合於該重配置線路結構上，以電性連接該些扇出線路。當該些外接端子為銲球時，可符合球格陣列封裝類型。
在前述薄型扇出式多晶片堆疊封裝構造中，該些外接端子與該些扇出線路之間係可設置有複數個端子承座，用以加強該些外接端子與該些扇出線路之結合。
在前述薄型扇出式多晶片堆疊封裝構造中，該些晶片係可為階梯式錯位堆疊，以顯露出該些電極，該些電極係可包含複數個銲墊。
在前述薄型扇出式多晶片堆疊封裝構造中，該虛置間隔片係可選自於虛晶片與金屬片之其中之一，可適用於晶片取放的作業，並具有良好散熱效果。
在前述薄型扇出式多晶片堆疊封裝構造中，該虛置間隔片顯露於該平坦面之面積係可等於或小於該第二晶片之該主動面，以使該虛置間隔片之周圍側面被該封膠體密封。藉此，該虛置間隔片被該封膠體與該第一保護層共同密封而不易剝離。
藉由上述的技術手段，本發明可以達成終極薄扇出出式晶圓級封裝製程(ultra thin fan out wafer level package process)之應用，即省略了基板厚度，總體封裝厚度極為接近晶片堆疊高度，可在不超過100微米之範圍內。除此之外，也可以運用於面板等級封裝製程。更可以結合為球格陣列封裝類型(BGA package type)。在晶圓級或面板級封裝製程中導入了晶片取放的堆疊、打 線與模封在RDL形成之前，以製作出終極薄的封裝構造。因此，除了載體不同與RDL形成之外，製程中的晶片設置、打線連接與模封步驟都可以使用到現有的封裝技術。
10‧‧‧暫時載板
11‧‧‧黏著層
30‧‧‧銲線
34‧‧‧曲折線段
35‧‧‧線尾端
40‧‧‧壓合桿
41‧‧‧切割膠膜
42‧‧‧定位環
50‧‧‧單離切割器
100‧‧‧薄型扇出式多晶片堆疊封裝構造
110‧‧‧晶片堆疊體
111‧‧‧第一晶片
111A‧‧‧第二晶片
112‧‧‧主動面
112A‧‧‧主動面
113‧‧‧電極
113A‧‧‧電極
114‧‧‧晶片貼附層
120‧‧‧虛置間隔片
121‧‧‧側面
130‧‧‧不完整銲線
131‧‧‧接合線頭
132‧‧‧垂直線段
133‧‧‧研磨斷面
140‧‧‧封膠體
141‧‧‧平坦面
150‧‧‧重配置線路結構
151‧‧‧扇出線路
152‧‧‧第一保護層
153‧‧‧第二保護層
160‧‧‧外接端子
170‧‧‧端子承座
200‧‧‧薄型扇出式多晶片堆疊封裝構造
280‧‧‧披覆層
第1圖：依據本發明之第一具體實施例，一種薄型扇出式多晶片堆疊封裝構造之截面示意圖。
第2A至2J圖：依據本發明之第一具體實施例，繪示在該薄型扇出 式多晶片堆疊封裝構造之製程中主要步驟之元件截面示意圖。
第3A與3B圖：依據本發明之第一具體實施例，繪示在該薄型扇出 式多晶片堆疊封裝構造之製程中單體化切割步驟之元件立體示意圖。
第4圖：依據本發明之第二具體實施例，另一種薄型扇出式多晶片堆疊封裝構造之截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸 比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例，一種薄型扇出式多晶片堆疊封裝構造100舉例說明於第1圖之截面示意圖以及第2A至2J圖其製造方法中各主要步驟之元件截面示意圖，而第3A與3B圖係繪示在該薄型扇出式多晶片堆疊封裝構造100之製程中單體化切割步驟之元件立體示意圖。一種薄型扇出式多晶片堆疊封裝構造100係包含一晶片堆疊體110、一虛置間隔片120、複數個不完整銲線130、一封膠體140以及一重配置線路結構150。
請參閱第1圖，該晶片堆疊體110係由複數個晶片111、111A堆疊所組成，該些晶片111、111A係為具有記憶體等IC半導體元件。該些晶片111、111A係區分為至少一第一晶片111以及一疊設於該第一晶片111下之第二晶片111A。每一之該些第一晶片111係具有一主動面112以及至少一位於該主動面112之電極113，該第二晶片111A係具有一主動面112A以及至少一位於該主動面112A之電極113A。當該些晶片111、111A相互堆疊，該些第一晶片111之主動面112係被局部覆蓋。該些第一晶片111之電極113係不被該第二晶片111A覆蓋，該第二晶片111A之一主動面112A係亦不被堆疊覆蓋。換言之，該些第一晶片111之該些電極113與該第二晶片111A之主動面112A係不被該些晶片111堆疊覆蓋，該晶片堆疊體110中較為完整未被堆疊覆蓋主動面係為該晶片堆疊體110中第二晶片111A之主動面112A。該主動面112、112A係為積體電路的形成表面，該些電極113、113A係與該晶片111、 111A內部積體電路的金屬內連線(未繪示)電性連接。每一之該些晶片111、111A之背面係可形成有一晶片貼附層114，用以黏接另一鄰近晶片111之主動面112，以構成該晶片堆疊體110。而被黏接主動面112的面積中約60~90%被該晶片貼附層114覆蓋。該些晶片111、111A之堆疊數量可在四個或四個以上，在本實施例中係為八個晶片的堆疊。而該些晶片111、111A的堆疊方式可以是階梯堆疊、十字堆疊或塔型堆疊。在本實施例中，該些晶片111、111A係可為階梯式錯位堆疊，以不遮蓋該些電極113、113A，該些電極113、113A係可包含複數個銲墊。當所有主動面112都朝向同一方向時，將會有一個主動面不被該些晶片111、111A堆疊覆蓋，其係為該第二晶片111A之主動面112A。
再請參閱第1圖，該虛置間隔片120係設置於該第二晶片111A之該主動面112A上，其中該第二晶片111A之至少一電極113A係不被該虛置間隔片120覆蓋。具體地，該虛置間隔片120係可選自於虛晶片(dummy chip)與散熱金屬片(heat dissipating metal plate)之其中之一，可適用於晶片取放的作業，並具有良好散熱效果。該虛置間隔片120之尺寸與厚度係可等於或小於該些晶片111、111A之單位尺寸與單位厚度。「虛晶片」係為形狀或外觀相似於晶片但不具有晶片內IC主動元件的半導體基板。該虛置間隔片120係可被研磨而局部犧牲並提供間隔墊片的功能，以防止該第二晶片111A之未堆疊覆蓋主動面112A受到研磨損害。此外，該虛置間隔片120更具有在模封時穩定該些不完整銲線130 的功能，以減輕模封沖線之問題。
所謂的「完整銲線」係指打線形成並且不懸空截斷而為兩端接合的銲線，而「不完整銲線」係指封裝製程的打線步驟中原本具有完整銲線的結構，但在封裝製程的後續步驟中被部份移除的銲線殘留體。每一不完整銲線130係具有一接合線頭131與一垂直線段132，該些不完整銲線130之該些接合線頭131係接合至該些晶片111、111A之該些電極113、113A並一體連接對應之垂直線段132。該些垂直線段132之長度係互補於被接合晶片之堆疊高度，即晶片111、111A之堆疊高度越高，接合於對應電極的該些不完整銲線130之該些垂直線段132之長度則越短。該些不完整銲線130係具有複數個模封之後以研磨露出之研磨斷面133，而不會有習知垂直銲線懸空截斷之切線擠壓痕跡。該些不完整銲線130之材質可以是金(Au)，也可以是銅(Cu)。
再請參閱第1圖，該封膠體140係密封該晶片堆疊體110、該虛置間隔片120與該些不完整銲線130，該封膠體140係為熱固型絕緣材料，如絕緣樹脂或模封環氧化合物。該封膠體140係具有一平坦面141，該平坦面141係位於一水平高度，其係異於該第二晶片111A之主動面112A，即兩者位於不同水平，並且該些不完整銲線130之該些複數個研磨斷面133與該虛置間隔片120係共平面顯露於該平坦面141。通常該平坦面141至該第二晶片111A之未堆疊覆蓋主動面112A的鄰近間隙係為該虛置間隔片120之研磨後厚度，約等於或小於一個晶片111、111A之厚度，藉 以達到該平坦面141與被指定主動面(即該第二晶片111A之主動面112A)兩者為鄰近但不水平重疊的效果。
請參閱第1圖，該重配置線路結構150係形成於該平坦面141上，該重配置線路結構150係包含複數個扇出線路151、一第一保護層152以及一第二保護層153，其中該第一保護層152係覆蓋該平坦面141與該虛置間隔片120但顯露出該些研磨斷面133，該些扇出線路151係形成於該第一保護層152上，並透過該第一保護層152連接至該些不完整銲線130之該些研磨斷面133，該第二保護層153係形成於該第一保護層152上並覆蓋該些扇出線路151。故該些扇出線路151可不需要直接形成於該平坦面141。該重配置線路結構150係不同於習知基板之線路層，是利用半導體沉積、電鍍與蝕刻設備予以製作。該些扇出線路151之結構係可為多層式金屬層，例如鈦/銅/銅(Ti/Cu/Cu)、鈦/銅/銅/鎳/金(Ti/Cu/Cu/Ni/Au)等，其中第一銅層為較薄(約0.2微米)，由沉積形成；第二銅層為較厚(約3微米)，由電鍍形成。也就是說，該些扇出線路151係可包含接合層、晶種層、電鍍層之組合。該些扇出線路151之線路厚度係可控制在不大於10微米，約介於2~6微米。而該第一保護層152與該第二保護層153之結構係可為有機絕緣層，例如聚亞醯胺(PI)，該第一保護層152與該第二保護層153之個別厚度係可約為5微米。故該重配置線路結構150在厚度薄化程度與線路密集度可優於習知基板線路層，當保護層開設孔洞，高覆蓋率的沉積金屬層即可電性連接底層之重配置線路，不僅可 以降低線路層的層數，也不需要製作基板鍍通孔之結構。
在本實施例中，該虛置間隔片120顯露於該平坦面141之面積係可等於或小於該第二晶片111A之該主動面112A，即未堆疊覆蓋主動面，以使該虛置間隔片120之周圍側面121被該封膠體140密封。藉此，該虛置間隔片120被該封膠體140與該第一保護層152共同密封而不易剝離。
再請參閱第1圖，該薄型扇出式多晶片堆疊封裝構造100係可另包含複數個外接端子160，係可接合於該重配置線路結構150上，以電性連接該些扇出線路151。當該些外接端子160為銲球時，可符合球格陣列(BGA)封裝類型。較佳地，該些外接端子160與該些扇出線路151之間係可設置有複數個端子承座170，用以加強該些外接端子160與該些扇出線路151之結合。該些端子承座170之結構係為凸塊下金屬層(UBM)，例如鎳/銅(Ni/Cu)。
因此，本發明提供之一種薄型扇出式多晶片堆疊封裝構造，可以改善特定封裝類型中的垂直銲線模封沖線之問題，而使得薄型扇出式多晶片堆疊封裝構造的製造有較佳的穩定度與良率。
關於上述薄型扇出式多晶片堆疊封裝構造100之製造方法係配合第2A至2J圖說明如後。
首先，請參閱第2A圖，利用晶片取放方式，逐一設置複數個晶片111、111A於一暫時載板10上。該暫時載板10之表面可預先形成一黏著層11，例如UV黏著膠。在UV光照射之後， 該黏著層11將失去黏性，以利於剝離該暫時載板10。該暫時載板10可以是晶圓承載系統(Wafer Support System,WSS)，亦可為面板承載系統(Panel Support System,PSS)，甚至可為一定位環固定之黏性膠膜。該暫時載板10之主體材質係可為矽或玻璃，該暫時載板10之外形係可為一晶圓或一面板。
之後，請參閱第2B圖，在往上堆疊足夠數量的晶片，能提供一晶片堆疊體110於該暫時載板10上。該晶片堆疊體110係由至少一第一晶片111與一第二晶片111A堆疊所組成，每一第一晶片111係具有一主動面112以及至少一位於該主動面112之電極113，該第二晶片111A係具有一主動面112A以及至少一位於該主動面112A之電極113A。當該些晶片111、111A堆疊之後，該些第一晶片111之主動面112係可被局部覆蓋，但該些第一晶片111之該電極113係不被該第二晶片111A覆蓋，該第二晶片111A之主動面112A則不被覆蓋。該些電極113、113A與該第二晶片111A之主動面112A係為不被堆疊覆蓋。一晶片貼附層114係可形成於每一晶片111、111A之背面，用以黏合鄰近第一晶片111之主動面112。其中，該些晶片111、111A係為階梯式錯位堆疊，以不遮蓋該些電極113、113A，該些電極113、113A係包含複數個銲墊。並且，設置一虛置間隔片120於該第二晶片111A之該主動面112A上，其中該第二晶片111A之至少一電極113A係不被該虛置間隔片120覆蓋。該虛置間隔片120係選自於虛晶片與金屬片之其中之一。
之後，請參閱第2C圖，以打線方式形成複數個完整銲線30以連接在該晶片堆疊體110與該虛置間隔片120之間，每一銲線30係具有一接合線頭131、一垂直線段132、一曲折線段34以及一線尾端35，該些銲線30之該些接合線頭131係接合至該些晶片111、111A之該些電極113、113A並一體連接對應之垂直線段132，並經由該些曲折線段34一體連接至該些線尾端35，該些線尾端35係接合於該虛置間隔片120。因此，該些銲線30對於模封沖擊具有較佳的抵抗力。此外，該些銲線30係具有一高於該虛置間隔片120之線弧高度，其係由該些曲折線段34定義，以使該些曲折線段34超出該虛置間隔片120之水平面。
之後，請參閱第2D圖，以轉移模封或壓縮模封方式形成一封膠體140於該暫時載板10上，該封膠體140係密封該晶片堆疊體110、該虛置間隔片120與該些銲線30。該封膠體140之模封厚度係大於該些銲線30由該暫時載板10起算之線弧高度。在本步驟中，該些銲線30與該虛置間隔片120係可被該封膠體140完全密封。
之後，請參閱第2E圖，以晶圓研磨或面板研磨方式進行機械研磨或化學研磨，以研磨該封膠體140，使得該封膠體140係具有一平坦面141，該平坦面141係不與該第二晶片111A之未堆疊覆蓋主動面112A為共平面，較佳兩者表面為平行向的鄰近，並移除該些曲折線段34與該些線尾端35，以使得該些銲線30為不完整並標示為130，該些不完整銲線130之複數個研磨斷面 133與該虛置間隔片120係共平面顯露於該平坦面141。該虛置間隔片120係可作為研磨深度的緩衝層，該虛置間隔片120之部份但非全部亦可被磨除，故該第二晶片111A之該未堆疊覆蓋主動面112A不會受到研磨損害。較佳地，該虛置間隔片120顯露於該平坦面141之面積係不大於該第二晶片111A之該未堆疊覆蓋主動面112A，以使該虛置間隔片120之周圍側面121被該封膠體140密封。
之後，請參閱第2F至2H圖，形成一重配置線路結構150於該平坦面141上，該重配置線路結構150係包含複數個扇出線路151、一第一保護層152以及一第二保護層153。在第2F圖中，該第一保護層152係形成於該平坦面141上，並使其圖案化而顯露出該些研磨斷面133，該第一保護層152係可更覆蓋於該虛置間隔片120之顯露表面。在第2G圖中，該些扇出線路151係形成於該第一保護層152上，並透過該第一保護層152連接至該些不完整銲線130之該些研磨斷面133。在第2H圖中，該第二保護層153係形成於該第一保護層152上並覆蓋該些扇出線路151。
之後，請參閱第2I圖，較佳地，可接合複數個外接端子160於該重配置線路結構150上，以電性連接該些扇出線路151。之後，請參閱第2J圖，移除該暫時載板10，而該封膠體140之外形係可如同一已封裝晶圓或一已封裝面板(如第3A圖所示)。
第3A與3B圖係繪示在該薄型扇出式多晶片堆疊封裝構造100之製程中單體化切割步驟之元件立體示意圖。請參閱第3A 圖，在一切割前定位步驟中，利用一壓合桿40將一切割膠膜41壓合貼附於該封膠體140。該切割膠膜41之周邊又固定於一定位環42。故該封膠體140相對於接合有該些外接端子160之一表面係為顯露，以供雷射標記(laser marking)，而該封膠體140供雷射標記之表面係可顯露出底層堆疊晶片之背面(如第3B圖所示)。請參閱第3B圖，在一單體化切割步驟中，沿著該封膠體140之預定義切割道，利用一單離切割器50切入該封膠體140已雷射標記之表面，以製作出複數個上述之薄型扇出式多晶片堆疊封裝構造100。
依據本發明之第二具體實施例，另一種薄型扇出式多晶片堆疊封裝構造200舉例說明於第4圖之截面示意圖。其中第二具體實施例中與第一具體實施例相同功能的元件將沿用相同圖號且不再細部贅述。該薄型扇出式多晶片堆疊封裝構造200係包含一晶片堆疊體110、一虛置間隔片120、複數個不完整銲線130、一封膠體140以及一重配置線路結構150。
該晶片堆疊體110係由至少一第一晶片111與一第二晶片111A堆疊所組成，每一晶片111、111A係具有一主動面112、112A以及複數個位於該主動面112、112A之電極113、113A，該些電極113、113A與其中一指定主動面112A係不被該些晶片111、111A堆疊覆蓋，該未堆疊覆蓋主動面係為該晶片堆疊體110中第二晶片111A之主動面112A。該些晶片111、111A之間係以一晶片貼附層114黏接。該虛置間隔片120係設置於該第二晶片111A之主動面112A上。每一不完整銲線130係具有一接合線頭131與 一垂直線段132，該些不完整銲線130之該些接合線頭131係接合至該些晶片111、111A之該些電極113、113A並一體連接對應之垂直線段132。
該封膠體140係密封該晶片堆疊體110、該虛置間隔片120與該些不完整銲線130，該封膠體140係具有一平坦面141，該平坦面141係不與該第二晶片111A之未堆疊覆蓋主動面112A為共平面，並且該些不完整銲線130之複數個研磨斷面133與該虛置間隔片120係共平面顯露於該平坦面141。
該重配置線路結構150係形成於該平坦面141上，該重配置線路結構150係包含複數個扇出線路151、一第一保護層152以及一第二保護層153，其中該第一保護層152係覆蓋該平坦面141與該虛置間隔片120但顯露出該些研磨斷面133，該些扇出線路151係形成於該第一保護層152上，並透過該第一保護層152連接至該些不完整銲線130之該些研磨斷面133，該第二保護層153係形成於該第一保護層152上並覆蓋該些扇出線路151。
在本實施例中，該封膠體140在相對於該平坦面141之一形成表面係顯露最底層堆疊晶片111之背面，一披覆層280係形成於該封膠體140之形成表面，以避免裸露晶片背面。該披覆層280係可為一有機絕緣膠層，以對抗該重配置線路結構150的形成應力，藉此達到封裝翹曲平衡。此外，該披覆層280亦可為一導熱層。
以上所揭露的僅為本發明較佳實施例而已，當然不 能以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。
100‧‧‧薄型扇出式多晶片堆疊封裝構造
110‧‧‧晶片堆疊體
111‧‧‧第一晶片
111A‧‧‧第二晶片
112‧‧‧主動面
112A‧‧‧主動面
113‧‧‧電極
113A‧‧‧電極
114‧‧‧晶片貼附層
120‧‧‧虛置間隔片
121‧‧‧側面
130‧‧‧不完整銲線
131‧‧‧接合線頭
132‧‧‧垂直線段
133‧‧‧研磨斷面
140‧‧‧封膠體
141‧‧‧平坦面
150‧‧‧重配置線路結構
151‧‧‧扇出線路
152‧‧‧第一保護層
153‧‧‧第二保護層
160‧‧‧外接端子
170‧‧‧端子承座

Claims (10)

  1. 一種薄型扇出式多晶片堆疊封裝構造，包含：一晶片堆疊體，主要係由複數個晶片堆疊所組成，每一晶片係具有一主動面以及至少一位於該主動面之電極，其中一第一晶片之至少一電極係不被一第二晶片覆蓋，並且該第二晶片之一主動面係亦不被堆疊覆蓋；一虛置間隔片，係設置於該第二晶片之該主動面上，其中該第二晶片之至少一電極係不被該虛置間隔片覆蓋；複數個銲線，每一銲線係具有一接合線頭與一垂直線段，該些銲線之該些接合線頭係接合至該些晶片之該些電極並一體連接對應之垂直線段；一封膠體，係密封該晶片堆疊體與該些銲線，該封膠體係具有一平坦面，該些銲線之複數個研磨斷面與該虛置間隔片係共平面顯露於該平坦面；以及一重配置線路結構，係形成於該平坦面上，該重配置線路結構係包含複數個扇出線路、一第一保護層以及一第二保護層，其中該第一保護層係覆蓋該平坦面與該虛置間隔片但顯露出該些研磨斷面，該些扇出線路係形成於該第一保護層上，並透過該第一保護層連接至該些銲線之該些研磨斷面，該第二保護層係形成於該第一保護層上並覆蓋該些扇出線路。
  2. 如申請專利範圍第1項所述之薄型扇出式多晶片堆疊封裝構造，另包含複數個外接端子，係接合於該重配置線路結構 上，以電性連接該些扇出線路。
  3. 如申請專利範圍第2項所述之薄型扇出式多晶片堆疊封裝構造，其中該些外接端子與該些扇出線路之間係設置有複數個端子承座。
  4. 如申請專利範圍第1項所述之薄型扇出式多晶片堆疊封裝構造，其中該些晶片係為階梯式錯位堆疊，以顯露出該些電極，該些電極係包含複數個銲墊。
  5. 如申請專利範圍第1至4項任一項所述之薄型扇出式多晶片堆疊封裝構造，其中該虛置間隔片係選自於虛晶片與金屬片之其中之一。
  6. 如申請專利範圍第5項所述之薄型扇出式多晶片堆疊封裝構造，其中該虛置間隔片顯露於該平坦面之面積係等於或小於該第二晶片之該主動面，以使該虛置間隔片之周圍側面被該封膠體密封。
  7. 一種薄型扇出式多晶片堆疊封裝構造之製造方法，包含：提供一晶片堆疊體於一暫時載板上，該晶片堆疊體主要係由複數個晶片堆疊所組成，每一晶片係具有一主動面以及至少一位於該主動面之電極，其中一第一晶片之至少一電極係不被一第二晶片覆蓋，並且該第二晶片之一主動面係亦不被堆疊覆蓋；設置一虛置間隔片於該第二晶片之該主動面上，其中該第二晶片之至少一電極係不被該虛置間隔片覆蓋；形成複數個銲線以連接在該晶片堆疊體與該虛置間隔片之 間，每一銲線係具有一接合線頭、一垂直線段、一曲折線段以及一線尾端，該些銲線之該些接合線頭係接合至該些晶片之該些電極並一體連接對應之垂直線段，並經由該些曲折線段一體連接至該些線尾端，該些線尾端係接合於該虛置間隔片；形成一封膠體於該暫時載板上，該封膠體係密封該晶片堆疊體、該虛置間隔片與該些銲線；研磨該封膠體，使得該封膠體係具有一平坦面，其係與該第二晶片之該主動面位於不同的水平，並移除該些曲折線段與該些線尾端，以使得該些銲線為不完整，該些銲線之複數個研磨斷面與該虛置間隔片係共平面顯露於該平坦面；形成一重配置線路結構於該平坦面上，該重配置線路結構係包含複數個扇出線路、一第一保護層以及一第二保護層，其中該第一保護層係覆蓋該平坦面與該虛置間隔片但顯露出該些研磨斷面，該些扇出線路係形成於該第一保護層上，並透過該第一保護層連接至該些銲線之該些研磨斷面，該第二保護層係形成於該第一保護層上並覆蓋該些扇出線路；以及移除該暫時載板。
  8. 如申請專利範圍第7項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，另包含：接合複數個外接端子於該重配置線路結構上，以電性連接該些扇出線路。
  9. 如申請專利範圍第7項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，其中該些晶片係為階梯式錯位堆疊，以顯露出該些電極，該些電極係包含複數個銲墊。
  10. 如申請專利範圍第7、8或9項所述之薄型扇出式多晶片堆疊封裝構造之製造方法，其中該虛置間隔片係選自於虛晶片與金屬片之其中之一，該虛置間隔片顯露於該平坦面之面積係等於或小於該第二晶片之該主動面，以使該虛置間隔片之周圍側面被該封膠體密封。
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