TWI710079B - 使用導線接合之混合式添加結構之可堆疊記憶體晶粒 - Google Patents

使用導線接合之混合式添加結構之可堆疊記憶體晶粒 Download PDF

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TWI710079B
TWI710079B TW107126637A TW107126637A TWI710079B TW I710079 B TWI710079 B TW I710079B TW 107126637 A TW107126637 A TW 107126637A TW 107126637 A TW107126637 A TW 107126637A TW I710079 B TWI710079 B TW I710079B
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semiconductor die
die
semiconductor
bonding pads
redistribution structure
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TW107126637A
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TW201913925A (zh
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艾夏克 帕查穆索
辰 Ｈ 游
約翰 Ｆ 凱汀
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美商美光科技公司
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Abstract

本文中揭示具有不包含預成形基板之重佈結構之半導體裝置以及相關聯系統及方法。在一些實施例中，一種半導體裝置包含附著至一重佈結構且經由複數個導線接合電耦合至該重佈結構之一第一半導體晶粒。該半導體裝置亦可包含堆疊於該第一半導體晶粒上之一或多個第二半導體晶粒，其中該第一半導體晶粒及該第二半導體晶粒之一或多者經由複數個導線接合電耦合至該重佈結構。該半導體裝置亦可包含該第一半導體晶粒及/或該第二半導體晶粒及該重佈結構之一表面上方之一模製材料。

Description

使用導線接合之混合式添加結構之可堆疊記憶體晶粒
本發明大體上係關於半導體裝置。特定而言，本發明係關於包含電耦合至不包含一預成形基板之一重佈結構之半導體晶粒之半導體裝置以及相關聯系統及方法。
微電子裝置大體上具有一晶粒(即，一晶片)，其包含具有一高密度之極小組件之積體電路。通常，晶粒包含電耦合至積體電路之一極小接合墊陣列。接合墊係供應電壓、信號等等透過其傳輸至積體電路及自積體電路傳輸之外部電接點。在形成晶粒之後，「封裝」晶粒以將接合墊耦合至可更容易耦合至各種電力供應線、信號線及接地線之一較大電端子陣列。用於封裝晶粒之習知程序包含將晶粒上之接合墊電耦合至引線、球墊或其他類型之電端子之一陣列且囊封晶粒以保護其免受環境因數(例如水分、微粒、靜電及實體衝擊)影響。
不同類型之晶粒可具有大不相同接合墊配置，但應與類似外部裝置相容。因此，既有封裝技術可包含將一晶粒電耦合至經組態以與外部裝置之接合墊配合之一中介層或其他預成形基板。預成形基板可與晶圓分開形成(諸如由一供應商提供)，且預成形基板接著在封裝程序期間附著至晶圓。此等預成形基板會相對較厚以藉此增大所得半導體封裝之大小。其他既有封裝技術可代以包含在一晶粒上直接形成一重佈層(RDL)。RDL包含將晶粒接合墊與RDL接合墊連接之線路及/或通路，RDL接合墊繼而經配置以與外部裝置之接合墊配合。在一典型封裝程序中，將諸多晶粒安裝於一載體上(即，在一晶圓或面板級處)且在移除載體之前囊封晶粒。接著，使用沈積及微影技術來使一RDL直接形成於晶粒之一正面上。最後，將引線、球墊或其他類型之電端子之一陣列安裝於RDL之接合墊上且分割晶粒以形成個別微電子裝置。
上述封裝技術之一缺點在於其使將多個半導體晶粒垂直堆疊成一單一封裝變困難及昂貴。即，由於在形成RDL之前囊封晶粒，所以堆疊晶粒一般需要矽穿孔(TSV)來將堆疊晶粒之接合墊電耦合至RDL。形成TSV需要特殊工具及/或技術，其會增加形成一微電子裝置之成本。
相關申請案之交叉參考
本申請案含有與名稱為「THRUMOLD POST PACKAGE WITH REVERSE BUILD UP HYBRID ADDITIVE STRUCTURE」之John F. Kaeding、Ashok Pachamuthu、Mark E. Tuttle及Chan H. Yoo之一同時申請美國專利申請案相關之標的。相關申請案(其揭示內容以引用的方式併入本文中)讓與Micron Technology公司且由代理檔案號010829-9216.US00識別。
下文將描述包含電耦合至不包含一預成形基板之一重佈結構之半導體晶粒之半導體裝置以及相關聯系統及方法之若干實施例之特定細節。在一些實施例中，一半導體裝置包含導線接合至不含一預成形基板之一重佈結構且由一模製材料囊封之一或多個半導體晶粒。在以下描述中，討論諸多特定細節以提供本發明之實施例之一透徹且可行描述。然而，熟悉相關技術者將認識到，可在無一或多個特定細節的情況下實踐本發明。在其他例項中，未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作以免使本發明之其他態樣不清楚。一般而言，應瞭解，除本文中所揭示之特定實施例之外，各種其他裝置、系統及方法亦可在本發明之範疇內。
如本文中所使用，術語「垂直」、「橫向」、「上」及「下」可係指半導體裝置中之構件鑑於圖中所展示之定向之相對方向或位置。例如，「上」或「最上」可涉及定位成比一構件更靠近於一頁之頂部之另一構件。然而，此等術語應被廣義解釋為包含具有其他定向(諸如其中頂部/底部、上方/下方、上面/下面、上/下及左/右可取決於定向而互換之相反或傾斜定向)之半導體裝置。
圖1A係一橫截面圖且圖1B係一俯視圖，其等繪示根據本發明之一實施例之一半導體裝置100 (「裝置100」)。參考圖1A，裝置100可包含一重佈結構130、耦合至重佈結構130且具有複數個接合墊112之一半導體晶粒110及位於重佈結構130之至少一部分及半導體晶粒110上方之一模製材料150。模製材料150可完全覆蓋半導體晶粒110及重佈結構130。如圖1A中所展示，僅一個半導體晶粒110耦合至重佈結構130，然而，在其他實施例中，裝置100可包含任何數目個半導體晶粒(例如堆疊於半導體晶粒110上之一或多個額外半導體晶粒)。半導體晶粒110可包含各種類型之半導體組件及功能構件，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式之積體電路記憶體、處理電路、成像組件及/或其他半導體構件。在一些實施例中，裝置100可包含安置於半導體晶粒110與重佈結構130之一第一表面133a之間之一晶粒附著材料109。晶粒附著材料109可為(例如)一黏著膜(例如一晶粒附著膜)、環氧樹脂、膠帶、膏糊或其他適合材料。
重佈結構130包含一介電材料132、介電材料132中及/或介電材料132上之複數個第一接點134及介電材料132中及/或介電材料132上之複數個第二接點136。重佈結構130進一步包含在介電材料132內、穿過介電材料132及/或在介電材料132上延伸以將第一接點134之個別者電耦合至第二接點136之對應者之複數個導線138 (例如包括導電通路及/或跡線)。在特定實施例中，第一接點134、第二接點136及導線138可由諸如銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料之一或多個導電材料形成。介電材料132可包括一適合介電、絕緣或鈍化材料之一或多個層。介電材料132使個別第一接點134、第二接點136及相關聯導線138彼此電隔離。重佈結構130亦包含面向半導體晶粒110之第一表面133a及與第一表面133a對置之一第二表面133b。第一接點134暴露於重佈結構130之第一表面133a處，而第二接點136暴露於重佈結構130之第二表面133b處。
在一些實施例中，重佈結構130之第二接點136之一或多者比對應第一接點134更與半導體晶粒110橫向間隔。即，第二接點136之若干者可自與其電耦合之對應第一接點134扇出或橫向向外定位。將第二接點136定位於第一接點134之橫向外促進裝置100連接至其他裝置及/或介面(其等包含具有大於半導體晶粒110之節距之一節距之連接)。再者，重佈結構130可包含半導體晶粒110下方之一晶粒附著區域。在圖1A所展示之實施例中，無第一接點134安置於重佈結構130之晶粒附著區域內。在其他實施例(例如，如圖4A中所展示)中，第一接點134之一或多者可安置於半導體晶粒110下方之晶粒附著區域內。當第一接點134位於晶粒附著區域內時，第一接點134可為電主動接點或非電主動之虛設接點。
重佈結構130之介電材料132形成一堆積基板，使得重佈結構130不包含一預成形基板(例如與一載體晶圓分開形成且隨後附著至載體晶圓之一基板)。因此，重佈結構130可被製成極薄的。例如，在一些實施例中，重佈結構130之第一表面133a與第二表面133b之間之一距離D1 小於約50 µm。在特定實施例中，距離D1 係約30 µm或小於約30 µm。因此，可相較於(例如)包含形成於一預成形基板上方之一習知重佈層之裝置而減小半導體裝置100之總大小。然而，重佈結構130之厚度係不受限制的。
裝置100進一步包含：(i)第一電連接器104，其等將半導體晶粒110之接合墊112電耦合至重佈結構130之對應第一接點134；及(ii)第二電連接器106，其等安置於重佈結構130之第二表面133b上且經組態以將重佈結構130之第二接點136電耦合至外部電路(圖中未展示)。第二電連接器106可為焊球、導電凸塊、導電支柱、導電環氧樹脂及/或其他適合導電元件。在一些實施例中，第二電連接器106在重佈結構130之第二表面133b上形成一球柵陣列。在特定實施例中，可省略第二電連接器106且可將第二接點136直接連接至外部裝置或電路。如圖1A中所展示，第一電連接器104可包括複數個導線接合。在其他實施例中，第一電連接器104可包括其他類型之導電連接器(例如導電支柱、凸塊、引線框等等)。
圖1B係展示半導體晶粒110及接合墊112的裝置100之一俯視圖(為便於說明，圖中未展示模製材料150)。如圖中所展示，第一電連接器104將半導體晶粒110之接合墊112電耦合至重佈結構130之第一接點134之對應者。在一些實施例中，一個別第一接點134可電耦合至一個以上接合墊112或僅一單一接合墊112。依此方式，裝置100可經組態使得半導體晶粒110之個別接針被個別隔離且可接取(例如信號接針)，及/或經組態使得多個接針可經由相同組之第一接點134及第二接點136共同接取(例如電力供應或接地接針)。在其他實施例中，電連接器104可依任何其他方式配置以提供半導體晶粒110與重佈結構130之第一接點134之間之電耦合之一不同組態。
如圖1B中所進一步展示，半導體晶粒110可具有其中接合墊112沿半導體晶粒110之對置縱向側配置之一矩形形狀。然而，在其他實施例中，半導體晶粒110可具有任何其他形狀及/或接合墊組態。例如，半導體晶粒110可呈矩形、圓形、正方形、多邊形及/或其他適合形狀。半導體晶粒110可進一步包含可依任何圖案配置於半導體晶粒110上之任何數目個接合墊(例如，多於或少於圖1B中所展示之14個實例性接合墊112)。
再次參考圖1A，模製材料150可形成於重佈結構130之第一表面133a、半導體晶粒110及第一電連接器104上方。模製材料150可囊封半導體晶粒110以保護半導體晶粒110免受污染及實體損壞。再者，由於裝置100不包含一預成形基板，所以模製材料150亦對裝置100提供所要結構強度。例如，模製材料150可經選擇以防止裝置100在將外力施加至裝置100時翹曲、彎曲等等。因此，在一些實施例中，重佈結構130可被製成極薄的(例如小於50 µm)，此係因為重佈結構130無需對裝置100提供很大結構強度。因此，可減小裝置100之總高度(例如厚度)。
圖2A至圖2J係繪示根據本發明之實施例之製造半導體裝置200之一方法中之各種階段的橫截面圖。一般而言，可將半導體裝置200製造成(例如)一離散裝置或一較大晶圓或面板之部分。在晶圓級或面板級製造中，形成一較大半導體裝置，接著將其分割以形成個別裝置。為便於解釋及理解，圖2A至圖2J繪示兩個半導體裝置200之製造。然而，熟悉技術者應易於瞭解，可將半導體裝置200之製造拓廣至晶圓及/或面板級(即，包含能夠分割成兩個以上半導體裝置之更多組件)，同時包含類似於本文中所描述之構件之構件且使用類似於本文中所描述之程序之程序。
首先參考圖2A至圖2D，半導體裝置200之製造開始於形成一重佈結構230 (圖2D)。參考圖2A，提供具有一正面261a及一背面261b之一載體260，且在載體260之正面261a上形成一釋放層262。釋放層262防止重佈結構230與載體260直接接觸且因此保護重佈結構230免受載體260上之可能污染。在特定實施例中，載體260可為由(例如)矽、絕緣體上矽、化合物半導體(例如氮化鎵)、玻璃或其他適合材料形成之一臨時載體。在某種程序上，載體260對後續處理階段提供機械支撐且亦在後續處理階段期間保護釋放層262之一表面以確保稍後可自重佈結構230適當移除釋放層262。在一些實施例中，可在隨後移除載體260之後重新使用載體260。釋放層262可為一次性膜(例如基於環氧樹脂之材料之一層疊膜)或其他適合材料。在一些實施例中，釋放層262可為雷射敏感或光敏的以促進其在一後續階段中經由一雷射或其他光源移除。
重佈結構230 (圖2D)係可由一添加堆積程序形成之導電及介電材料之一混合結構。即，將重佈結構230添加地直接堆積於載體260及釋放層262而非另一層疊或有機基板上。明確而言，藉由諸如濺鍍、物理氣相沈積(PVD)、電鍍、微影等等之半導體晶圓製程來製造重佈結構230。例如，參考圖2B，可在釋放層262上直接形成複數個第二接點236且可在釋放層262上形成一層介電材料232以使個別第二接點236電隔離。介電材料232可由(例如)聚對二甲苯、聚醯亞胺、低溫化學氣相沈積(CVD)材料(諸如四乙氧基矽烷(TEOS)、氮化矽(Si3 Ni4 )、氧化矽(SiO2 ))及/或其他適合介電、非導電材料形成。參考圖2C，可形成導電材料及介電材料232之額外層以堆積介電材料232及形成介電材料232內之導電部分235之導線238。
圖2D展示完全形成於釋放層262及載體260上之後之重佈結構230。如圖2D中所展示，形成電耦合至導線238之複數個第一接點234。因此，重佈結構230之導電部分235可包含第二接點236及第一接點234及導線238之一或多者。導電部分235可由銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料製成。在一些實施例中，導電部分235全部由相同導電材料製成。在其他實施例中，各導電部分235可包含一個以上導電材料(例如，第一接點234、第二接點236及導線238可包括一或多個導電材料)，及/或不同導電部分235可包括不同導電材料。第一接點234可經配置以界定重佈結構230上之晶粒附著區域239。
參考圖2E，半導體裝置200之製造接著將複數個第一半導體晶粒210耦合至重佈結構230之晶粒附著區域且形成將第一半導體晶粒210電耦合至重佈結構230之複數個電連接器204a。更明確而言，第一半導體晶粒210之一背面(例如與具有接合墊212之一正面對置之一側)經由一第一晶粒附著材料209a附著至重佈結構230之一暴露上表面233a處之一晶粒附著區域。第一晶粒附著材料209a可為一晶粒附著黏著膏或一黏著元件，例如一晶粒附著膜或一切割晶粒附著膜(熟悉技術者分別稱為「DAF」或「DDF」)。在一實施例中，第一晶粒附著材料209a可包含在被超過一臨限位準之壓力壓縮時將第一半導體晶粒210黏著至重佈結構230之一壓力固化黏著元件(例如膠帶或膜)。在另一實施例中，第一晶粒附著材料209a可為藉由暴露於UV輻射來固化之一UV固化膠帶或膜。如圖2E中所進一步展示，第一半導體晶粒210之接合墊212經由電連接器204a電耦合至重佈結構230之對應第一接點234。在所繪示之實施例中，電連接器204a包括複數個導線接合。在其他實施例中，電連接器204a可包括另一類型之導電構件，諸如(例如)導電凸塊、支柱、引線框等等。在其他實施例中，第一半導體晶粒210可經定位以具有一不同定向。例如，如下文將參考圖4A進一步詳細描述，第一半導體晶粒210可經定位成面向下，使得各第一半導體晶粒210之正面面向重佈結構230。
參考圖2F，半導體裝置200之製造接著將複數個第二半導體晶粒220堆疊於第一半導體晶粒210上且形成將第二半導體晶粒220電耦合至重佈結構230之複數個電連接器204b。因此，使複數個晶粒堆疊208沿重佈結構230彼此分離。如圖2F中所繪示，僅兩個晶粒208定位於重佈結構230上。然而，任何數目個晶粒堆疊208可沿重佈結構230及載體260彼此隔開。例如，在晶圓或面板級處，諸多晶粒堆疊208可沿晶圓或面板隔開。在其他實施例中，各晶粒堆疊208可包含不同數目個半導體晶粒。例如，各晶粒堆疊208可僅包含第一半導體晶粒210 (例如，如同圖1A及圖1B中所繪示之實施例)或可包含堆疊於第二半導體晶粒220上之額外半導體晶粒(例如3個、4個、8個、10個或甚至更多晶粒之堆疊)。
如圖2F中所展示，第二半導體晶粒220之一背面(例如與具有接合墊222之一正面對置之一側)經由一第二晶粒附著材料209b附著至第一半導體晶粒210之正面。即，第一半導體晶粒210及第二半導體晶粒220 (統稱為「晶粒210、220」)正面對背面堆疊。在其他實施例中，第二半導體晶粒220可經定位以具有一不同定向。例如，如下文將參考圖3A進一步詳細描述，第二半導體晶粒220可經定位成面向下，使得半導體晶粒220之正面面向第一半導體晶粒210之正面。第二晶粒附著材料209b可相同或不同於第一晶粒附著材料209a。在一些實施例中，第二晶粒附著材料209b具有適合與導線接合一起使用之一「導線覆膜(film-over-wire)」材料之形式。在此等實施例中，第二晶粒附著材料209b可為DAF或DDF。再者，第二晶粒附著材料209b之厚度可足以防止第二半導體晶粒220之背面與電連接器204a之間之接觸(例如導線接合)以避免損壞電連接器204a。在其他實施例中，可使用焊料或其他適合直接晶粒附著技術來將半導體晶粒220直接耦合至半導體晶粒210。
如圖2F中所進一步展示，第二半導體晶粒220之接合墊222經由電連接器204b電耦合至重佈結構230之第一接點234之對應者。在所繪示之實施例中，電連接器204b包括複數個導線接合。在其他實施例中，電連接器204b可包括另一類型之導電構件，諸如(例如)導電凸塊、支柱、引線框等等。例如，在其中晶粒210、220面對面(即，正面對正面)配置之特定實施例中，第二半導體晶粒220之接合墊222之一或多者可經由銅柱或焊料連接直接電耦合至一第一半導體晶粒210之接合墊212。如下文將參考圖2K進一步詳細描述，重佈結構230之一些第一接點234可電耦合至晶粒210、220之兩個或兩個以上接合墊212及/或222。在圖2F所展示之橫截面圖中，僅繪製電耦合至兩個晶粒210、220之第一接點234。
由於在將堆疊晶粒210、220安裝於載體260上之前於載體260上形成重佈結構230，所以可採用習知方法來將晶粒210、220電耦合至重佈結構230 (例如導線接合、直接晶片附著等等)。明確而言，可避免使用矽穿孔(TSV)來電耦合堆疊半導體晶粒。涉及首先將複數個半導體晶粒安裝至一載體且接著在晶粒上直接形成一重佈層之程序中需要TSV。在此一「後重佈層」方法中，必須在形成重佈層之前且在包覆模製之前堆疊半導體晶粒。即，半導體晶粒需要採用TSV (與(例如)導線接合相反)，此係因為在形成重佈層之前堆疊及包覆模製晶粒。本發明容許使用其他類型之電耦合，同時亦避免與TSV相關聯之成本及製造困難。
轉至圖2G，半導體裝置200之製造接著在重佈結構230之上表面233a上及晶粒210、220周圍形成一模製材料250。在所繪示之實施例中，模製材料250囊封晶粒210、220，使得晶粒210、220密封於模製材料250內。在一些實施例中，模製材料250亦可囊封電連接器204a及/或204b之部分或全部。模製材料250可由樹脂、環氧樹脂、基於聚矽氧之材料、聚醯亞胺及/或此項技術中使用或已知之其他適合樹脂形成。一旦被沈積，則模製材料250可藉由UV光、化學硬化劑、熱或此項技術中已知之其他適合固化方法來固化。固化模製材料250可包含一上表面251。在特定實施例中，可形成及/或磨削上表面251，使得上表面251具有高於重佈結構230之上表面233a之一高度，其僅略大於重佈結構230之上表面233a上方之電連接器204b及/或第二半導體晶粒220之一最大高度。即，模製材料250之上表面251可具有僅足以囊封電連接器204b及晶粒210、220之一高度。
參考圖2H，半導體裝置200之製造接著自載體260 (如圖2G中所展示)移除重佈結構230。例如，一真空、桿銷、雷射或其他光源或此項技術中已知之其他適合方法可使重佈結構230脫離釋放層262 (圖2G)。在一些實施例中，釋放層262允許載體260被容易移除，使得載體260可被再次重新使用。在其他實施例中，可藉由薄化載體260及/或釋放層262 (例如背面研磨、乾式蝕刻程序、化學蝕刻程序、化學機械拋光(CMP)等等)來至少部分移除載體260及釋放層262。移除載體260及釋放層262暴露重佈結構230之下表面233b (其包含複數個第二接點236)。
轉至圖2I，半導體裝置200之製造接著在重佈結構230之第二接點236上形成電連接器206。電連接器206可經組態以將重佈結構230之第二接點236電耦合至外部電路(圖中未展示)。在一些實施例中，電連接器206包括複數個焊球或焊料凸塊。例如，一模板印刷機可將焊料膏之離散區塊沈積至重佈結構230之第二接點236上。接著，可回焊焊料膏以在第二接點236上形成焊球或焊料凸塊。
圖2J展示彼此分割之後之半導體裝置200。如圖中所展示，可在複數個切割道253 (如圖2I中所繪示)處將重佈結構230與模製材料250一起切割以分割晶粒堆疊208且使半導體裝置200彼此分離。一旦被分割，則個別半導體裝置200可經由電連接器206附著至外部電路且因此併入至各種系統及/或裝置中。
圖2K繪示半導體裝置200之一者之一俯視圖。已省略模製材料250來展示具有接合墊222之第二半導體晶粒220。在所繪示之實施例中，第一半導體晶粒210完全定位於第二半導體晶粒220下方。如圖中所展示，電連接器204a將第一半導體晶粒210之接合墊212 (圖中未繪製)電耦合至重佈結構230之第一接點234之對應者。同樣地，電連接器204b將第二半導體晶粒220之接合墊222電耦合至重佈結構230之第一接點234之對應者。在一些實施例中，一個別第一接點234可電耦合至一個以上接合墊212及/或222。例如，如圖中所繪示，一個別第一接點234a可經由一導線接合204b電耦合至第二半導體晶粒220之一個別接合墊222a，且亦經由一導線接合204a電耦合至第一半導體晶粒210之一個別接合墊212 (圖中未繪製)。在特定實施例中，一個別第一接點234可僅耦合至一個接合墊212或222。例如，如圖中所繪示，一個別第一接點234b僅電耦合至第二半導體晶粒220之一接合墊222b且因此不電耦合至第一半導體晶粒210。依此方式，裝置200可經組態使得晶粒堆疊208中之一半導體晶粒之個別接針被個別隔離且可接取(例如信號接針)，及/或經組態使得晶粒堆疊208中之各半導體晶粒之共同接針可經由相同組之第一接點234及第二接接點236共同接取(例如電力供應或接地接針)。在其他實施例中，電連接器204a及204b可依任何其他方式配置以提供晶粒210、220與重佈結構230之第一接點234之間之電耦合之一不同組態。
在其他實施例中，晶粒210、220可經堆疊使得第一半導體晶粒210不直接位於第二半導體晶粒220下方，及/或晶粒210、220可具有彼此不同之尺寸或定向。例如，第二半導體晶粒220可經安裝使得其具有自第一半導體晶粒210外伸之一部分，或第一半導體晶粒210可大於第二半導體晶粒220，使得第二半導體晶粒220完全定位於第一半導體晶粒210之一覆蓋區內。晶粒210、220可進一步包含可依任何圖案配置於晶粒210、220上之任何數目個接合墊(例如，多於或少於圖2K中所展示之10個實例性接合墊)。
圖3A係一橫截面圖且圖3B係一俯視圖，其等繪示根據本發明之另一實施例之一半導體裝置300 (「裝置300」)。此實例更明確地展示配置成一「面對面」組態之一或多個半導體晶粒。裝置300可包含大體上類似於上文所詳細描述之半導體裝置100及200之構件之構件。例如，在圖3A所繪示之實施例中，裝置300包含一重佈結構330及耦合至重佈結構330之一上表面333a之一晶粒堆疊308。更明確而言，一第一半導體晶粒310之一背面(例如與具有複數個接合墊312之晶粒之一正面對置之一側)可經由一晶粒附著材料309附著至重佈結構330之上表面333a。具有複數個接合墊322之一第二半導體晶粒320可堆疊於第一半導體晶粒310上，且一模製材料350可形成於重佈結構330之上表面333a上及第一半導體晶粒310及第二半導體晶粒320周圍。第二半導體晶粒320經定位使得包含接合墊322之第二半導體晶粒320之一正面面向第一半導體晶粒之正面。複數個導電構件315將第二半導體晶粒320之接合墊322之至少若干者耦合至第一半導體晶粒310之接合墊312之對應者。在一些實施例中，導電構件315係銅柱。在特定實施例中，導電構件315可包括諸如(例如)銅、金、鋁等等之一或多個導電材料且可具有不同形狀及/或組態。
如圖3A及圖3B中所進一步展示，第一半導體晶粒310之接合墊312可經由導線接合304電耦合至重佈結構330之接點334之對應者。在一些實施例中，可在形成導線接合304之後形成導電構件315 (且因此附著第二半導體晶粒320)。在特定實施例中，可藉由諸如(例如)熱壓接合(例如銅-銅(Cu-Cu)接合)之一適合程序來形成導電構件315。一般而言，熱壓接合技術可利用熱及壓縮之一組合(例如z軸及/或垂直力控制)來形成第一半導體晶粒310之接合墊312與第二半導體晶粒320之接合墊322之間之一導電焊料接頭。導電構件315可進一步形成為具有足以使第二半導體晶粒320之正面不接觸且不會損壞導線接合304之一高度。在此等實施例中，裝置330包含隙間地形成於第一半導體晶粒310與第二半導體晶粒320之間之一間隙317。在特定實施例中，間隙317由模製材料350填充，使得模製材料350加強第一半導體晶粒310與第二半導體晶粒320之間之耦合。再者，模製材料350可對晶粒堆疊308提供結構強度以防止(例如)第二半導體晶粒320彎曲或翹曲。
圖3B展示將第一半導體晶粒310之接合墊312 (圖3A)電耦合至重佈結構330之接點334之導線接合304之一配置之一例示性實施例。圖3B中未繪製第一半導體晶粒310及接合墊312，此係因為其等完全位於第二半導體晶粒320下方，且為清楚起見，圖3B中未繪製模製材料350。如圖中所繪示，各接點334僅導線接合至一單一接合墊312。然而，導線接合304可依任何其他方式配置以提供接合墊312與接點334之間之電耦合之一不同組態。例如，在其他實施例中，部分或全部接點334可導線接合至一個以上接合墊312。在其他實施例中，部分或全部接點334可導線接合至第二半導體晶粒320之接合墊322及/或導電構件315。
圖4A係一橫截面圖且圖4B係一俯視圖，其等繪示根據本發明之另一實施例之一半導體裝置400 (「裝置400」)。在此實例中，一或多個半導體晶粒配置成一「背對背」組態。裝置400可包含大體上類似於上文所詳細描述之半導體裝置100及200之構件之構件。例如，在圖4A所繪示之實施例中，裝置400包含具有一上表面433a之一重佈結構430、耦合至上表面433a之一晶粒堆疊408及位於上表面433a上方且囊封晶粒堆疊408之一模製材料450。更明確而言，重佈結構430可包含暴露於重佈結構430之上表面433a處之複數個第一接點434a及複數個第二接點434b (統稱為「接點434」)。第二接點434b定位於晶粒堆疊408下方(例如，定位於直接在一第一半導體晶粒410下方之一晶粒附著區域內)，而第一接點434a與晶粒堆疊408橫向隔開(例如，定位於晶粒附著區域外)。
第一半導體晶粒410具有複數個接合墊412且附著至重佈結構430，使得半導體晶粒410之一正面(例如包含接合墊412之一側)面向重佈結構430之上表面433a。第一半導體晶粒410可依此方式使用已知覆晶安裝技術來附著至重佈結構430。如圖中所展示，複數個導電構件416可將第一半導體晶粒410之接合墊412耦合至重佈結構430之第二接點434b之對應者。在一些實施例中，導電構件416係銅柱。在其他實施例中，導電構件416可包括諸如(例如)銅、金、鋁等等之一或多個導電材料且可具有不同形狀及/或組態。可藉由諸如(例如)熱壓接合(例如銅-銅(Cu-Cu)接合)之一適合程序來形成導電構件416。在一些實施例中，導電構件416可具有使得裝置400包含隙間地形成於第一半導體晶粒410與重佈結構430之上表面433a之間之一間隙418之一高度。在一些此等實施例中，間隙418由模製材料450填充以加強第一半導體晶粒410與重佈結構430之間之耦合。再者，模製材料450可促進晶粒堆疊408防止(例如)第一半導體晶粒410彎曲或翹曲。
具有複數個接合墊422之一第二半導體晶粒420可背對背堆疊於第一半導體晶粒410上(例如，第一半導體晶粒410之一背面面向第二半導體晶粒420之一背面)。第二半導體晶粒420可經由一晶粒附著材料409附著至第一半導體晶粒410。如圖4A及圖4B中所進一步展示，第二半導體晶粒420之接合墊422可經由導線接合404電耦合至重佈結構430之第一接點434a之對應者。如圖4B中所展示，重佈結構430之第一接點434a之若干者可經由個別導線接合404電耦合至第二半導體晶粒420之一個以上接合墊422。同樣地，重佈結構430之第一接點434a之若干者可僅耦合至第二半導體晶粒420之一單一接合墊422。然而，導線接合404可依任何其他方式配置以提供接合墊422與第一接點434a之間之電耦合之一不同組態。例如，在一些實施例中，各第一接點434a僅導線接合至一單一對應接合墊422。
在本發明之其他實施例中，可使用本文中參考圖1A至圖4B所描述之正對背、正對正及/或背對背配置之任何者或其等之任何組合來提供包含具有兩個以上晶粒之一晶粒堆疊之一半導體裝置。例如，根據本發明之一半導體裝置可包含4重、6重、8重等等堆疊之多對正對正半導體晶粒、4重、6重、8重等等堆疊之多對正對背半導體晶粒或任何其他組合。
上文參考圖1A至圖4B所描述之半導體裝置之任何者可併入至各種更大及/或更複雜系統之任何者中，圖5中所示意性展示之系統590係該等系統之一代表性實例。系統590可包含一半導體晶粒總成500、一電源592、一驅動器594、一處理器596及/或其他子系統或組件598。半導體晶粒總成500可包含具有大體上類似於上述半導體裝置之構件之構件之半導體裝置。所得系統590可執行各種功能之任何者，諸如記憶體儲存、資料處理及/或其他適合功能。因此，代表性系統590可包含(但不限於)手持裝置(例如行動電話、平板電腦、數位讀取器及數位音訊播放器)、電腦及電器。系統590之組件可收容於一單一單元中或分佈於多個互連單元上(例如，透過一通信網路)。系統590之組件亦可包含遠端裝置及各種電腦可讀媒體之任何者。
應自上文瞭解，本文已為了說明而描述本發明之特定實施例，但可在不背離本發明的情況下作出各種修改。因此，本發明僅受限於隨附申請專利範圍。此外，亦可在其他實施例中組合或消除特定實施例之內文中所描述之新技術之特定態樣。再者，儘管已在該等實施例之內文中描述與新技術之特定實施例相關聯之優點，但其他實施例亦可展現此等優點，且未必需要落入本發明之範疇內之全部實施例展現此等優點。因此，本發明及相關聯技術可涵蓋本文中未明確展示或描述之其他實施例。
100‧‧‧半導體裝置104‧‧‧第一電連接器106‧‧‧第二電連接器109‧‧‧晶粒附著材料110‧‧‧半導體晶粒112‧‧‧接合墊130‧‧‧重佈結構132‧‧‧介電材料133a‧‧‧第一表面133b‧‧‧第二表面134‧‧‧第一接點136‧‧‧第二接點138‧‧‧導線150‧‧‧模製材料200‧‧‧半導體裝置204a‧‧‧電連接器204b‧‧‧電連接器206‧‧‧電連接器208‧‧‧晶粒堆疊209a‧‧‧第一晶粒附著材料209b‧‧‧第二晶粒附著材料210‧‧‧第一半導體晶粒212‧‧‧接合墊220‧‧‧第二半導體晶粒222‧‧‧接合墊222a‧‧‧接合墊222b‧‧‧接合墊230‧‧‧重佈結構232‧‧‧介電材料233a‧‧‧上表面233b‧‧‧下表面234‧‧‧第一接點234a‧‧‧第一接點234b‧‧‧第一接點235‧‧‧導電部分236‧‧‧第二接點238‧‧‧導線239‧‧‧晶粒附著區域250‧‧‧模製材料251‧‧‧上表面253‧‧‧切割道260‧‧‧載體261a‧‧‧正面261b‧‧‧背面262‧‧‧釋放層300‧‧‧半導體裝置304‧‧‧導線接合308‧‧‧晶粒堆疊309‧‧‧晶粒附著材料310‧‧‧第一半導體晶粒312‧‧‧接合墊315‧‧‧導電構件317‧‧‧間隙320‧‧‧第二半導體晶粒322‧‧‧接合墊330‧‧‧重佈結構333a‧‧‧上表面334‧‧‧接點350‧‧‧模製材料400‧‧‧半導體裝置404‧‧‧導線接合408‧‧‧晶粒堆疊409‧‧‧晶粒附著材料410‧‧‧第一半導體晶粒412‧‧‧接合墊416‧‧‧導電構件418‧‧‧間隙420‧‧‧第二半導體晶粒422‧‧‧接合墊430‧‧‧重佈結構433a‧‧‧上表面434‧‧‧接點434a‧‧‧第一接點434b‧‧‧第二接點450‧‧‧模製材料500‧‧‧半導體晶粒總成590‧‧‧系統592‧‧‧電源594‧‧‧驅動器596‧‧‧處理器598‧‧‧其他子系統/組件D1‧‧‧距離
圖1A及圖1B分別係繪示根據本發明之一實施例之一半導體裝置的一橫截面圖及俯視圖。
圖2A至圖2J係繪示根據本發明之一實施例之各種製造階段中之一半導體裝置的橫截面圖。
圖2K係圖2J中所展示之半導體裝置之一俯視圖。
圖3A及圖3B分別係繪示根據本發明之一實施例之一半導體裝置的一橫截面圖及俯視圖。
圖4A及圖4B分別係繪示根據本發明之一實施例之一半導體裝置的一橫截面圖及俯視圖。
圖5係包含根據本發明之一實施例所組態之一半導體裝置之一系統之一示意圖。
100‧‧‧半導體裝置
104‧‧‧第一電連接器
106‧‧‧第二電連接器
109‧‧‧晶粒附著材料
110‧‧‧半導體晶粒
112‧‧‧接合墊
130‧‧‧重佈結構
132‧‧‧介電材料
133a‧‧‧第一表面
133b‧‧‧第二表面
134‧‧‧第一接點
136‧‧‧第二接點
138‧‧‧導線
150‧‧‧模製材料
D1‧‧‧距離

Claims (22)

  1. 一種半導體裝置，其包括：一重佈結構，其具有一介電材料、具有數個第一導電接點之一第一表面、具有數個第二導電接點之一第二表面及透過該介電材料將該等第一導電接點之個別者電耦合至該等第二導電接點之對應者之數個導線，且其中該重佈結構不包含一預成形基板；一第一半導體晶粒，其附著至該重佈結構之該第一表面且包含數個第一接合墊；數個第一導線接合，其等將該等第一接合墊電耦合至該等第一導電接點之對應者；一第二半導體晶粒，其堆疊於該第一半導體晶粒上方且具有數個第二接合墊；數個第二導線接合，其等將該等第二接合墊電耦合至該等第一接合墊之對應者；及一模製材料，其覆蓋該重佈結構之至少一部分及該第一半導體晶粒。
  2. 如請求項1之半導體裝置，其進一步包括：將該第一半導體晶粒附著至該重佈結構之該第一表面之一第一晶粒附著材料；及將該第二半導體晶粒附著至該第一半導體晶粒之一第二晶粒附著材料。
  3. 如請求項1之半導體裝置，其中該第一半導體晶粒係一記憶體晶粒。
  4. 如請求項1之半導體裝置，其中：該模製材料位於該重佈結構之該第一表面上方且囊封該第一半導體晶粒、該第二半導體晶粒、該等第一導線結合及該等第二導線接合；及該裝置進一步包括該第一半導體晶粒與該重佈結構之該第一表面之間之一晶粒附著材料。
  5. 如請求項1之半導體裝置，其中該等第二接點之至少一者比與該第二接點電耦合之對應第一接點更與該第一半導體晶粒橫向間隔。
  6. 如請求項1之半導體裝置，其中該第一表面與該第二表面之間之該重佈結構之一厚度小於約50μm。
  7. 如請求項1之半導體裝置，其中該第一半導體晶粒及該第二半導體晶粒具有相同平面形形狀(planform shape)。
  8. 如請求項2之半導體裝置，其中該等第一導線結合之一部份延伸穿過該第二晶粒附著材料。
  9. 如請求項2之半導體裝置，其中該模製材料與該第一晶粒附著材料及該第二晶粒附著材料不同，且其中該第二半導體晶粒經由該第二晶粒附著 材料直接附著至該第一半導體晶粒。
  10. 一種製造一半導體裝置之方法，該方法包括：在一載體上形成一重佈結構，該重佈結構包含一絕緣材料、該重佈結構之一第一表面處之數個第一導電接點及該重佈結構之一第二表面處之數個第二導電接點，其中該等第二導電接點經由至少部分延伸穿過該絕緣材料之導線電耦合至該等第一導電接點之對應者；將一半導體晶粒安置於該重佈結構之該第一表面上方，其中該半導體晶粒包含數個接合墊；使用導線接合來將該等接合墊耦合至該等第一導電接點之對應者；在該重佈結構之該第一表面之至少一部分、該半導體晶粒及該等導線接合上方形成一模製材料；及移除該載體以暴露該重佈結構之該第二表面及該等第二導電接點。
  11. 如請求項10之方法，其中該半導體晶粒係一第一半導體晶粒，其中該等接合墊係第一接合墊，且該方法進一步包括：將一第二半導體晶粒堆疊於該第一半導體晶粒上，其中該第二半導體晶粒包含數個第二接合墊；及使用導線接合來將該等第二接合墊耦合至該等第一導電接點之對應者。
  12. 如請求項10之方法，其中該半導體晶粒係一第一半導體晶粒，且該方法包括： 將一第二半導體晶粒附著至該重佈結構之該第一表面，其中該第一半導體晶粒堆疊於該第二半導體晶粒上，且其中該第二半導體晶粒電耦合至該等第一導電接點之至少一者。
  13. 如請求項10之方法，其進一步包括：在移除該載體之後，將導電構件安置於該等暴露第二導電接點上。
  14. 如請求項10之方法，其進一步包括：將複數個半導體晶粒耦合至該重佈結構之該第一表面，其中各半導體晶粒包含數個接合墊；使用導線接合來將各半導體晶粒之該等接合墊耦合至該等第一導電接點之對應者；及在移除該載體之後，分割所得結構以界定複數個個別半導體裝置。
  15. 如請求項10之方法，其中該半導體晶粒係一第一半導體晶粒，其中該等接合墊係第一接合墊，其中該等導線接合係第一導線接合，且進一步其中：將該第一半導體晶粒安置於該重佈結構之該第一表面上方包括將該第一半導體晶粒經由一第一晶粒附著材料附著至該重佈結構之該第一表面；及該方法進一步包括：將一第二半導體晶粒經由一第二晶粒附著材料附著至該第一半導體晶粒，其中該第二半導體晶粒包括數個第二接合墊；及 將該等第二接合墊藉由數個第二導線結合附著至該等第一導電接點之對應者。
  16. 一種半導體裝置封裝，其包括：一第一半導體晶粒；一重佈結構，其包含直接形成於該第一半導體晶粒上之一堆積介電材料、具有數個第一接合墊之一第一側、具有數個封裝接點之一第二側及透過該介電材料將該等第一接合墊之個別者電耦合至該等封裝接點之對應者之數個導線，其中該重佈結構之該第一側附著至該第一半導體晶粒，且其中該第一半導體晶粒具有電耦合至該重佈結構之該等第一接合墊之對應者之數個第二接合墊；一第二半導體晶粒，其堆疊於該第一半導體晶粒上方且具有數個第三接合墊；及數個第一導線接合，其等將該等第三接合墊電耦合至該等第一接合墊之對應者。
  17. 如請求項16之半導體裝置封裝，其中該等第二接合墊經由第二導線接合電耦合至該等第一接合墊之該等對應者。
  18. 如請求項16之半導體裝置封裝，其中該等第二接合墊面向該重佈結構之該第一側且經由導電構件電耦合至該等第一接合墊之該等對應者。
  19. 如請求項16之半導體裝置封裝，其進一步包括位於該重佈結構之該 第一側上方且囊封該第一半導體晶粒、該第二半導體晶粒及該等第一導線接合之一模製材料。
  20. 如請求項16之半導體裝置封裝，其進一步包括堆疊於該第二半導體晶粒上方且具有數個第四接合墊之一第三半導體晶粒，其中該等第四接合墊電耦合至該重佈結構之該等第一接合墊之對應者。
  21. 如請求項16之半導體裝置封裝，其中該第一側與該第二側之間之該重佈結構之一厚度小於約50μm。
  22. 如請求項16之半導體裝置封裝，其中：該重佈結構之該第一側經由一第一晶粒附著材料附著至該第一半導體晶粒；該第二半導體晶粒經由一第二晶粒附著材料附著至該第一半導體晶粒；及該半導體裝置封裝進一步包括將該第一半導體晶粒之數個第四接合墊電耦合至該等第一接合墊之對應者之數個第二導線接合。
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