TWI757526B - 具有橫向偏移堆疊之半導體晶粒之半導體裝置及製造其之方法 - Google Patents

具有橫向偏移堆疊之半導體晶粒之半導體裝置及製造其之方法 Download PDF

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TWI757526B
TWI757526B TW107126265A TW107126265A TWI757526B TW I757526 B TWI757526 B TW I757526B TW 107126265 A TW107126265 A TW 107126265A TW 107126265 A TW107126265 A TW 107126265A TW I757526 B TWI757526 B TW I757526B
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semiconductor die
semiconductor
redistribution structure
die
package substrate
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TW107126265A
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TW201921625A (zh
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辰 Ｈ 游
艾夏克 帕查穆索
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美商美光科技公司
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Abstract

本文中揭示包含堆疊半導體晶粒之半導體裝置以及相關聯系統及方法。在一實施例中，一種半導體裝置包含：一第一半導體晶粒，其耦合至一封裝基板；及一第二半導體晶粒，其堆疊於該第一半導體晶粒上方且自該第一半導體晶粒橫向偏移。因此，該第二半導體晶粒可包含延伸超過該第一半導體晶粒之一側且面向該封裝基板之一外伸部分。在一些實施例中，該第二半導體晶粒在該外伸部分處包含數個接合墊，其等經由安置於該等接合墊與該封裝基板之間之導電構件電耦合至該封裝基板。在特定實施例中，該第一半導體晶粒可包含經由導線接合電耦合至該封裝基板之數個第二接合墊。

Description

具有橫向偏移堆疊之半導體晶粒之半導體裝置及製造其之方法
本發明大體上係關於半導體裝置。特定而言，本發明係關於具有包含橫向偏移半導體晶粒之一半導體晶粒堆疊之半導體裝置以及相關聯系統及方法。
微電子裝置(諸如記憶體裝置、微處理器及發光二極體)通常包含安裝至一基板且包裝於一保護覆蓋物中之一或多個半導體晶粒。半導體晶粒包含功能構件，諸如記憶體單元、處理器電路、互連電路等等。半導體晶粒製造商面臨由半導體晶粒佔用之體積減小但所得囊封總成之容量及/或速度提高之越來越大壓力。為滿足此等要求，半導體晶粒製造商通常使多個半導體晶粒彼此上下垂直堆疊以提高其上安裝半導體晶粒之電路板或其他元件上之有限體積內之一微電子裝置之容量或效能。
在一些半導體晶粒堆疊中，使堆疊晶粒直接電互連(例如，使用矽穿孔(TSV)或覆晶接合)以提供至其上安裝晶粒之電路板或其他元件之一電連接。然而，依此方式使晶粒互連需要額外處理步驟來產生使晶粒互連所需之通路及/或金屬化構件。在其他半導體晶粒堆疊中，將堆疊晶粒導線接合至電路板或其他元件。儘管使用導線接合可避免與使晶粒互連 相關聯之成本及複雜性，但導線接合增大晶粒堆疊之總高度，此係因為導線接合在堆疊中之各晶粒(其包含最上晶粒)上方連結成環。
在一實施例中，一種半導體裝置包括：一封裝基板；一第一半導體晶粒，其耦合至該封裝基板且具有背向該封裝基板之一上表面，該上表面包含數個第一接合墊；數個導線接合，其等將該第一半導體晶粒之該等第一接合墊電耦合至該封裝基板；一第二半導體晶粒，其耦合至該第一半導體晶粒之該上表面且具有面向該封裝基板之一下表面，其中該第二半導體晶粒橫向延伸超過該第一半導體晶粒之至少一側以界定該第二半導體晶粒之一外伸部分，且其中該下表面在該外伸部分處包含數個第二接合墊；及數個導電構件，其等將該第二半導體晶粒之該等第二接合墊電耦合至該封裝基板。
在另一實施例中，一種半導體裝置包括：一重佈結構，其具有一第一表面及與該第一表面對置之一第二表面，其中該第一表面包含數個第一導電接點及數個第二導電接點，其中該第二表面包含數個第三導電接點，且其中該等第一導電接點及該等第二導電接點藉由穿過一絕緣材料及/或在一絕緣材料上延伸之導線來電耦合至該等第三導電接點之對應者；一第一半導體晶粒，其耦合至該重佈結構且具有數個第一接合墊；數個導線接合，其等將該等第一接合墊電耦合至該重佈結構之該等第一導電接點；一第二半導體晶粒，其堆疊於該第一半導體晶粒上方且自該第一半導體晶粒橫向偏移，其中該第二半導體晶粒包含具有該第一半導體晶粒上方之一第一部分及該重佈結構之該等第二導電接點上方之一第二部分之一表面，且其中該第二部分包含數個第二接合墊；及數個導電支柱，其等將 該等第二導電接點耦合至該等第二接合墊。
在又一實施例中，一種製造一半導體裝置之方法包括：形成位於一封裝基板之一第一表面上且電耦合至該封裝基板之數個導電支柱；將一第一半導體晶粒耦合至該封裝基板；經由導線接合將該第一半導體晶粒之第一接合墊電耦合至該封裝基板；將一第二半導體晶粒耦合至該第一半導體晶粒及該等導電支柱，其中該等導電支柱將該第二半導體晶粒之第二接合墊電耦合至該封裝基板；及形成位於該封裝基板之該第一表面上方且至少部分圍繞該第一半導體晶粒、該等導電支柱、該等導線接合及該第二半導體晶粒之一模製材料。
100:半導體裝置
104:導線接合
106:導電構件
108:電連接器
110:第一半導體晶粒
112:第一接合墊
113a:上表面
113b:下表面
114:敞露部分
116:第一側
118:第二側
120:第二半導體晶粒
122:第二接合墊
123a:上表面
123b:下表面
124:外伸部分
130:封裝基板
132:第一接點
133a:第一側/第一表面
133b:第二側/第二表面
134:第二接點
135:絕緣材料
136:第三接點
138:導線
142:第一晶粒附著材料
144:第二晶粒附著材料
146:模製材料
239:晶粒附著區域
247:上表面
250:載體
251a:正面
251b:背面
252:釋放層
255:切割道
300:半導體裝置
304:第一導線接合
306:第一導電構件
310:第一半導體晶粒
312:第一接合墊
313a:上表面
313b:下表面
314:敞露部分
316:第一側
318:第二側
320:第二半導體晶粒320
322:第二接合墊
323a:上表面
323b:下表面
324:外伸部分
330:封裝基板
332:第一接點
334:第二接點
336:第三接點
338:導線
342:第一晶粒附著材料
344:第二晶粒附著材料
346:模製材料
348:第三晶粒附著材料
349:第四晶粒附著材料
360:第三半導體晶粒
362:第三接合墊
363a:上表面
363b:下表面
364:敞露部分
368:第二導線接合
370:第四半導體晶粒
372:第四接合墊
373a:上表面
373b:下表面
374:外伸部分
376:第二導電構件
400:半導體裝置
404:導線接合
410:第一半導體晶粒
412:第一接合墊
414:敞露部分
416:第一側
418:第二側
420:第二半導體晶粒
422:第二接合墊
424:外伸部分
430:封裝基板
432:第一接點
500:系統
502:處理器
504:記憶體
505:輸入/輸出裝置
508:其他子系統/組件
D:距離
X1:軸線
X3:軸線
X4:軸線
Y4:軸線
圖1A及圖1B分別係繪示根據本發明之實施例之一半導體裝置的一橫截面圖及一俯視圖。
圖2A至圖2J係繪示根據本發明之實施例之各種製造階段中之一半導體裝置的橫截面圖。
圖3A及圖3B分別係繪示根據本發明之實施例之一半導體裝置的一橫截面圖及俯視圖。
圖4係根據本發明之一實施例之一半導體裝置之一俯視圖。
圖5係包含根據本發明之實施例所組態之一半導體裝置之一系統之一示意圖。
下文將描述半導體裝置之若干實施例之特定細節。在下文將描述之若干實施例中，一種半導體裝置包含：一第一半導體晶粒，其耦 合至一封裝基板；及一第二半導體晶粒，其堆疊於該第一半導體晶粒上方且自該第一半導體晶粒橫向偏移。因此，該第二半導體晶粒可包含延伸超過該第一半導體晶粒之至少一側之一外伸部分。在一些實施例中，該第二半導體晶粒僅堆疊於該第一半導體晶粒之一第一部分上方且不堆疊於該第一半導體晶粒之一第二部分上方。在特定實施例中，(3)該第一半導體晶粒之接合墊定位於該第一部分處且經由導線接合電耦合至該封裝基板，及(b)該第二半導體晶粒之接合墊定位於該外伸部分處且經由導電支柱電耦合至該封裝基板。由於該第一半導體晶粒及該第二半導體晶粒兩者之接合墊直接電耦合至該封裝基板，所以無需在堆疊晶粒之間形成電互連。再者，該半導體裝置之高度不受限於該等導線接合之高度，此係因為該等導線接合僅耦合至該第一半導體晶粒且無需延伸超過該第二半導體晶粒之上表面。
在以下描述中，討論諸多特定細節以提供本發明之實施例之一透徹且可行描述。然而，熟悉相關技術者將認識到，可在無一或多個特定細節的情況下實踐本發明。在其他例項中，未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作以免使本發明之其他態樣不清楚。一般而言，應瞭解，除本文中所揭示之特定實施例之外，各種其他裝置、系統及方法亦可在本發明之範疇內。
如本文中所使用，術語「垂直」、「橫向」、「上」及「下」可係指半導體裝置中之構件鑑於圖中所展示之定向之相對方向或位置。例如，「上」或「最上」可涉及比一構件更靠近於一頁之頂部之另一構件。然而，此等術語應被廣義解釋為包含具有其他定向(諸如其中頂部/底部、上方/下方、上面/下面、上/下及左/右可取決於定向而互換之相反或傾斜 定向)之半導體裝置。
圖1A係一橫截面圖且圖1B係一俯視圖，其等繪示根據本發明之一實施例之一半導體裝置100(「裝置100」)。參考圖1A，裝置100包含由一封裝基板130承載之一第一半導體晶粒110及一第二半導體晶粒120(統稱為「半導體晶粒110、120」)。半導體晶粒110、120可各具有積體電路或組件、資料儲存元件、處理組件及/或製造於半導體基板上之其他構件。例如，半導體晶粒110、120可包含積體記憶體電路及/或邏輯電路，其可包含各種類型之半導體組件及功能構件，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式之積體電路記憶體、處理電路、成像組件及/或其他半導體構件。在一些實施例中，半導體晶粒110、120可為相同的(例如經製造以具有相同設計及規格之記憶體晶粒)，但在其他實施例中，半導體晶粒110、120可彼此不同(例如不同類型之記憶體晶粒或控制器、邏輯及/或記憶體晶粒之一組合)。
第一半導體晶粒110包含面向封裝基板130之一下表面113b及與下表面113b對置之一上表面113a。類似地，第二半導體晶粒120包含面向第一半導體晶粒110之上表面113a及封裝基板130之一下表面123b及與下表面123b對置之一上表面123a。在圖1A所繪示之實施例中，第二半導體晶粒120堆疊於第一半導體晶粒110上方，使得第二半導體晶粒120之下表面123b之一部分位於第一半導體晶粒110之上表面113a上方(例如，直接在第一半導體晶粒110之上表面113a上方及/或相鄰於第一半導體晶粒110之上表面113a)。即，第二半導體晶粒120自第一半導體晶粒110橫向偏移，使得第二半導體晶粒120包含不定位於第一半導體晶粒110上方之 一外伸部分124，且第一半導體晶粒110包含其中第二半導體晶粒120未定位於第一半導體晶粒110上方之一對應敞露部分114。更特定而言，參考圖1B，第一半導體晶粒110可包含對置第一側116及對置第二側118，且第二半導體晶粒120可僅延伸超過第一半導體晶粒110之第一側116之一者(圖1B中以虛線展示)(例如，沿大體上平行於第二側118之一軸線X1之一方向)以界定外伸部分124。在其他實施例(例如，如圖4中所展示)中，第二半導體晶粒120可延伸超過第一半導體晶粒110之第一側116及/或第二側118之一者以上以界定外伸部分124。
第一半導體晶粒110之敞露部分114及第二半導體晶粒120之外伸部分124之大小、形狀及相對範圍至少取決於半導體晶粒110、120之相對尺寸(例如寬度、厚度及長度)及定位(例如橫向偏移)。例如，如圖1B之俯視圖中所展示，半導體晶粒110、120可各具有相同矩形平面形狀及相同或實質上類似尺寸。因此，敞露部分114及外伸部分124兩者可具有矩形平面形狀及相同或實質上類似尺寸。然而，在其他實施例中，半導體晶粒110、120之形狀、大小及偏移可不同。例如，第一半導體晶粒110及/或第二半導體晶粒120可呈圓形、方形、多邊形及/或其他適合形狀。因此，第一半導體晶粒110之敞露部分114及/或第二半導體晶粒120之外伸部分124可具有不同相對形狀及/或大小。
第一半導體晶粒110進一步包含位於敞露部分114處之上表面113a上(例如，暴露於敞露部分114處之上表面113a處)且背向封裝基板130之第一接合墊112。類似地，第二半導體晶粒120包含位於外伸部分124處之下表面123b上且面向封裝基板130之第二接合墊122。即，半導體晶粒110、120可配置成其中各半導體晶粒之接合墊面向相反方向之一面 對面組態。如圖1B中所繪示，第一接合墊112及第二接合墊122(統稱為「接合墊112、122」；圖1B中以虛線展示第二半導體晶粒之接合墊122)可各具有直線形狀且可分別沿半導體晶粒110、120之一側形成一單一行。然而，在其他實施例中，接合墊112、122可具有任何其他形狀或組態。例如，接合墊112、122可呈圓形、多邊形等等且可沿半導體晶粒110、120之一個以上側配置成多個列及/或行，等等。
如圖1A中所展示，裝置100僅包含兩個半導體晶粒。然而，在其他實施例中，裝置100可包含任何數目個半導體晶粒。例如，裝置100可包含堆疊於第一半導體晶粒110及/或第二半導體晶粒120上之一或多個額外半導體晶粒，或裝置100可具有相鄰於第一半導體晶粒110及/或第二半導體晶粒120耦合至封裝基板130之其他半導體晶粒。
再次參考圖1A，裝置100可進一步包含至少部分形成於第一半導體晶粒110之下表面113b與封裝基板130之間之一第一晶粒附著材料142及至少部分形成於第一半導體晶粒110之上表面113a與第二半導體晶粒120之下表面123b之間之一第二晶粒附著材料144。第一晶粒附著材料142及第二晶粒附著材料144可為(例如)黏著膜(例如晶粒附著膜)、環氧樹脂、膠帶、糊膏或其他適合材料。在一些實施例中，第一晶粒附著材料142及第二晶粒附著材料144係相同材料及/或具有實質上相同厚度。如圖1A之實施例中所展示，第二晶粒附著材料144可至少部分延伸至第二半導體晶粒120之外伸部分124上。然而，在其他實施例中，第二晶粒附著材料144可僅延伸於第一半導體晶粒110與第二半導體晶粒120之間。同樣地，在一些實施例中，第二晶粒附著材料144可至少部分延伸至第一半導體晶粒110之敞露部分114上。
封裝基板130可包含一重佈結構、一中介層、一印刷電路板、一介電間隔物、另一半導體晶粒(例如一邏輯晶粒)或另一適合基板。更明確而言，在圖1A所繪示之實施例中，封裝基板130具有一第一側133a及與第一側133a對置之一第二側133b，且包含使封裝基板130之導電部分絕緣之一絕緣材料135。封裝基板之導電部分可包含位於絕緣材料135中及/或絕緣材料135上且暴露於第一表面133a處之第一接點132及第二接點134。如圖1B中所更清楚繪示，第一接點132與第一半導體晶粒110之第一側116之一者橫向向外間隔(例如，位於第一半導體晶粒110之第一側116之一者外)。第二接點134(在圖1B中被遮蔽)可與第一側116之另一者橫向向外間隔且位於第二半導體晶粒120之外伸部分124下方。在一些實施例中，第二接點134與第二半導體晶粒120之第二接合墊122垂直對準(例如，疊置於第二半導體晶粒120之第二接合墊122下方)。
封裝基板130之導電部分亦可包含：(a)導電第三接點136，其等位於絕緣材料135中及/或絕緣材料135上且暴露於封裝基板130之第二表面133b處；及(b)導線138(例如通路及/或跡線)，其等延伸於絕緣材料135內及/或絕緣材料135上以將第一接點132及第二接點134之個別者電耦合至第三接點136之對應者。在一些實施例中，第三接點136之一或多者可定位於與第三接點136電耦合之對應第一接點132或第二接點134之橫向外(例如，自對應第一接點132或第二接點134扇出)。將第三接點136之至少若干者定位於第一接點132及/或第二接點134之橫向外促進裝置100連接至其他裝置及/或介面(其含有具有大於第一半導體晶粒110及/或第二半導體晶粒120之節距之一節距之連接)。在一些實施例中，第三接點136之一個別者可經由對應導線138電耦合至一個以上第一接點132及/或第 二接點134。依此方式，裝置100可經組態使得半導體晶粒110、120之個別接針被個別隔離且可經由單獨第三接點136接取(例如信號接針)，及/或經組態使得多個接針可經由相同第三接點136共同接取(例如電力供應或接地接針)。在特定實施例中，第一接點132、第二接點134、第三接點136及導線138可由諸如銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料之一或多個導電材料形成。
在一些實施例中，封裝基板130係不包含一預成形基板(即，與一載體晶圓分開形成且接著附著至載體晶圓之一基板)之一重佈結構。在此等實施例中，且如下文將參考圖2A至圖2D進一步詳細描述，絕緣材料135可包括(例如)使層添加地彼此上下疊置成形之一適合介電材料(例如一鈍化材料)之一個多個層。同樣地，可經由一適合堆積程序來添加地形成重佈結構之導電部分。在其中重佈結構不包含一預成形基板之實施例中，封裝基板130可為極薄的。例如，在一些此等實施例中，封裝基板130之第一表面133a與第二表面133b之間之一距離D可小於50μm。在特定實施例中，距離D係約30μm或小於30μm。因此，可相較於(例如)包含形成於一預成形基板上方之一習知重佈層之裝置而減小半導體裝置100之總大小。然而，封裝基板130之厚度係不受限制的。在其他實施例中，封裝基板130可包含不同構件及/或構件可具有一不同配置。
裝置100進一步包含電耦合至封裝基板130之第三接點136且經組態以將裝置100電耦合至外部裝置或電路(圖中未展示)之電連接器108(例如焊球、導電凸塊、導電支柱、導電環氧樹脂及/或其他適合導電元件)。在一些實施例中，電連接器108在封裝基板130之第二表面133b上形成一球柵陣列。在特定實施例中，可省略電連接器108且可將第三接點 136直接連接至外部裝置或電路。
裝置100進一步包含：(a)導線接合104，其等將第一半導體晶粒110之第一接合墊112電耦合至封裝基板130之第一接點132；及(b)導電構件106，其等將第二半導體晶粒120之第二接合墊122電耦合至封裝基板130之第二接點134。尤其在圖1A所繪示之實施例中，封裝基板130(或(例如)第一半導體晶粒110之上表面113a)上方之導線接合104之一最大高度不大於封裝基板130上方之第二半導體晶粒120之一高度。即，導線接合104不向上延伸超過與第二半導體晶粒120之上表面123a共面之一平面。再者，如圖1B之俯視圖中所繪示，各第一接點132可經由導線接合104之一單一者電耦合至第一半導體晶粒110之接合墊112之僅一單一者。然而，在其他實施例中，第一接點132之個別者可經由兩個或兩個以上導線接合104電耦合至兩個或兩個以上第一接合墊112(例如，用於將一共同信號提供至第一半導體晶粒110之兩個接針)。導電構件106可具有各種適合結構(諸如支柱、柱、短軸、凸塊等等)且可由銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料製成。在特定實施例中，導電構件106係焊料接頭，而在特定實施例中，導電構件106係銅柱。在其他實施例中，導電構件106可包含更複雜結構，諸如氮化物上凸塊結構或其他已知覆晶安裝結構。
顯而易見，第二半導體晶粒120無需與第一半導體晶粒110或透過第一半導體晶粒110直接電互連，此係因為第二半導體晶粒120直接連接至封裝基板130。相比而言，諸多習知半導體裝置需要相對較複雜且昂貴之互連結構來將堆疊半導體晶粒耦合至一封裝基板。例如，諸多已知半導體裝置包含延伸穿過一堆疊中之下半導體晶粒以將堆疊中之上晶粒 電連接至一封裝基板之矽穿孔(TSV)。此等裝置不僅需要形成TSV，且亦需要形成用於連接堆疊中之相鄰半導體晶粒之TSV之互連件(例如凸塊下金屬化構件、焊料連接等等)。同樣地，諸多已知半導體裝置包含面對面配置且覆晶接合在一起之堆疊半導體晶粒。此外，此等裝置需要形成連接對向晶粒之接合墊之互連結構且在諸多例項中，需要形成半導體晶粒之間之一重佈層(RDL)來提供各晶粒之接合墊之間之一適合映射。本文中所描述之裝置100無需半導體晶粒110、120之間之直接電互連且因此避免與相關聯互連結構相關聯之成本及複雜性。例如，裝置100可僅包含半導體晶粒110、120之間之第二晶粒附著材料144來替代形成半導體晶粒110、120之間之一RDL。
如圖1A中所進一步展示，裝置100包含封裝基板130之第一側133a上方之一模製材料146(為便於繪示，圖1B中未展示模製材料146)。模製材料146至少部分包圍第一半導體晶粒110、第二半導體晶粒120、導線接合104及/或導電構件106以保護此等組件之一或多者免受污染及/或實體損壞。例如，在圖1A所繪示之實施例中，模製材料146囊封(例如，密封)第一半導體晶粒110、導線接合104及導電構件106，同時僅第二半導體晶粒120之上表面123a自模製材料146暴露。
顯而易見，模製材料146未相對於封裝基板130延伸超過第二半導體晶粒120(例如，超過第二半導體晶粒120之上表面123a共面之一平面)，同時亦實質上囊封導線接合104及導電構件106。相比而言，諸多習知半導體裝置包含各導線接合至一封裝基板之半導體晶粒之一堆疊。在此等裝置中，堆疊中之最上半導體晶粒之導線接合延伸超過最上晶粒來連接至該晶粒之接合墊(例如，依類似於圖1A中之導線接合104之一方式， 其包含第一半導體晶粒110之上表面113a上方之一「環圈高度」)。然而，由於第二半導體晶粒120經由導電構件106(而非經由導線接合)直接電耦合至封裝基板130，所以模製材料146無需延伸超過第二半導體晶粒120。
因此，可減小裝置100之高度(例如厚度)及裝置100中所使用之模製材料146之總量。減小裝置100中之模製材料146之數量可降低裝置100隨溫度變化而翹曲之趨勢。特定而言，模製材料一般具有大於矽半導體晶粒之一熱膨脹係數(CTE)。因此，藉由減小模製材料之高度來減小模製材料146之體積可降低裝置100之總平均CTE(例如，藉由增大由半導體晶粒110、120佔用之相對體積)。然而，在其他實施例中，模製材料146可延伸超過第二半導體晶粒120。例如，在一些實施例中，模製材料146可略微延伸超過第二半導體晶粒120以覆蓋上表面123a，同時亦相較於(例如)其中將最上半導體晶粒導線接合至一封裝基板之一半導體裝置而減小裝置100之總高度。
此外，在一些實施例中，模製材料146可至少部分填充第二半導體晶粒120之外伸部分124下方之空間。因此，模製材料146可支撐外伸部分124以防止第二半導體晶粒120因外力而翹曲或受其他損壞。再者，在其中封裝基板130係不包含一預成形基板之一重佈結構之實施例中，模製材料146亦可對裝置100提供所要結構強度。例如，模製材料146可經選擇以防止裝置100在將外力施加至裝置100時翹曲、彎曲等等。因此，在一些實施例中，重佈結構可被製成極薄的(例如，小於50μm)，此係因為重佈結構無需對裝置100提供很大結構強度。因此，可進一步減小裝置100之總高度(例如厚度)。
圖2A至圖2J係繪示根據本發明之實施例之製造半導體裝置 100之一方法中之各種階段的橫截面圖。一般而言，可將一半導體裝置100製造成(例如)一離散裝置或一較大晶圓或面板之部分。在一晶圓級或面板級製造中，形成一較大半導體裝置，接著將其分割以形成複數個個別裝置。為便於解釋及理解，圖2A至圖2J繪示兩個半導體裝置100之製造。然而，熟悉技術者應易於瞭解，可將半導體裝置100之製造拓廣至晶圓及/或面板級(即，包含能夠分割為兩個以上半導體裝置100之更多組件)，同時包含類似於本文中所描述之構件之構件且使用類似於本文中所描述之程序之程序。
更明確而言，圖2A至圖2D繪示半導體裝置100(圖1A)之一封裝基板(其係不包含一預成形基板之一重佈結構)之製造。在其他實施例中，可對半導體裝置100提供一不同類型之封裝基板(例如一中介層、一印刷電路板等等)，且製造半導體裝置100之方法可開始於(例如)提供封裝基板之後之圖2E中所繪示之階段。
參考圖2A，在具有一背面251b及一正面251a之一載體250上形成封裝基板130(即，重佈結構)，載體250包含形成於其上之一釋放層252。載體250對後續處理階段提供機械支撐且可為由(例如)矽、絕緣體上矽、化合物半導體(例如氮化鎵)、玻璃或其他適合材料形成之一臨時載體。在一些實施例中，可在隨後移除載體250之後重新使用載體250。載體250亦在後續處理階段期間保護釋放層252之一表面以確保稍後可自封裝基板130適當移除釋放層252。釋放層252防止封裝基板130與載體250直接接觸且因此保護封裝基板130免受載體250上之可能污染。釋放層252可為一次性膜(例如基於環氧樹脂之材料之一層疊膜)或其他適合材料。在一些實施例中，釋放層252係雷射敏感或光敏的以促進其在一後續階段中被 移除。
封裝基板130(圖1A)包含可由一添加堆積程序形成之導電及介電材料。即，封裝基板130添加地直接堆積於載體250及釋放層252而非另一層疊或有機基板上。明確而言，藉由諸如濺鍍、物理氣相沈積(PVD)、電鍍、微影等等之半導體晶圓製程來製造封裝基板130。例如，參考圖2B，可在釋放層252上直接形成第三接點136，且可在釋放層252上形成一層絕緣材料135以電隔離第三接點136。絕緣材料135可由(例如)聚對二甲苯、聚醯亞胺、低溫化學氣相沈積(CVD)材料(諸如四乙氧基矽烷(TEOS)、氮化矽(Si3Ni4)、氧化矽(SiO2))及/或其他適合介電、非導電材料形成。參考圖2C，可形成堆積絕緣材料135之一或多個額外絕緣材料層，且可形成將導線138堆積於絕緣材料135上及/或絕緣材料135內之一或多個額外導電材料層。
圖2D展示完全形成於載體250上方之後之封裝基板130。如上文所描述，形成經由導線138之一或多者電耦合至第三接點136之對應者之第一接點132及第二接點134。第一接點132、第二接點134、第三接點136及導線138可由銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料製成。在一些實施例中，此等導電部分全部由相同導電材料製成。在其他實施例中，第一接點132、第二接點134、第三接點136及/或導線138可包括一個以上導電材料。第一接點132及第二接點134可經配置以界定封裝基板130上之晶粒附著區域239。
參考圖2E，半導體裝置100之製造接著在封裝基板130之第二接點134上形成導電構件106。可藉由此項技術中熟知之一適合電鍍或無電電鍍技術來製造導電構件106。在其他實施例中，可使用其他沈積技 術(例如濺鍍沈積)來替代電鍍。在其他實施例中，導電構件106可包括安置於第二接點134上之焊球或焊料凸塊。導電構件106可具有一圓形、矩形、六邊形、多邊形或其他橫截面形狀且可為單層或多層結構。
參考圖2F，半導體裝置100之製造接著(a)將第一半導體晶粒110耦合至封裝基板130之晶粒附著區域239(圖2D)之對應者且(b)形成導線接合104使得其將第一半導體晶粒110之第一接合墊112電耦合至封裝基板130之第一接點132。更特定而言，第一半導體晶粒110可經由第一晶粒附著材料142附著至封裝基板之晶粒附著區域239。第一晶粒附著材料142可為一晶粒附著黏著膏或一黏著元件，例如一晶粒附著膜或一切割晶粒附著膜(熟悉技術者分別稱為「DAF」或「DDF」)。在一些實施例中，第一晶粒附著材料142可包含在其被超過一臨限位準之壓力壓縮時將第一半導體晶粒110黏著至封裝基板130之一壓力固化黏著元件(例如膠帶或膜)。在其他實施例中，第一晶粒附著材料142可為藉由暴露於UV輻射來固化之一UV固化膠帶或膜。
圖2G展示將第二半導體晶粒120堆疊於第一半導體晶粒110上方且耦合至導電構件106之後之半導體裝置100。更明確而言，可將第二半導體晶粒120覆晶接合至封裝基板130，使得第二半導體晶粒120之第二接合墊122經由導電構件106電耦合至封裝基板130之第二接點134之對應者。在一些實施例中，使用焊料或焊料膏來將第二接合墊122耦合至導電構件106。在其他實施例中，可使用諸如熱壓接合(例如銅-銅(Cu-Cu)接合)之另一程序來形成第二接合墊122與導電構件106之間之導電Cu-Cu接頭。
可經由第二晶粒附著材料144將第二半導體晶粒120附著至 第一半導體晶粒110之至少一部分。如上文所描述，無需在半導體晶粒110與120之間形成電互連(例如金屬化構件、焊料凸塊、RDL等等)。第二晶粒附著材料144可大體上類似於第一晶粒附著材料142(例如DAF、DDF等等)且在一些實施例中，相同於第一晶粒附著材料142及/或具有相同於第一晶粒附著材料142之厚度。在圖2G所繪示之實施例中，第二晶粒附著材料144延伸至第二半導體晶粒120之外伸部分124上。在一些此等實施例中，在將第二接合墊122耦合至導電構件106之前自第二半導體晶粒120之第二接合墊122剝離或否則移除第二晶粒附著材料144或防止第二晶粒附著材料144覆蓋第二半導體晶粒120之第二接合墊122。在其他實施例中，不在外伸部分124上形成第二晶粒附著材料144或自外伸部分124完全移除第二晶粒附著材料144。
圖2H展示使模製材料146安置於封裝基板130之第一表面133a上且至少部分圍繞第一半導體晶粒110、導線接合104、第二半導體晶粒120及/或導電構件106安置之後之半導體裝置100。模製材料146可由樹脂、環氧樹脂、基於聚矽氧之材料、聚醯亞胺及/或此項技術中使用或已知之其他適合樹脂形成。一旦被沈積，則模製材料146可藉由UV光、化學硬化劑、熱或此項技術中已知之其他適合固化方法來固化。固化模製材料146可包含一上表面247。在圖2H所繪示之實施例中，上表面247大體上與第二半導體晶粒120之上表面123a共面，使得上表面123a不被模製材料146覆蓋。在一些實施例中，在一步驟中形成模製材料146，使得第二半導體晶粒120之上表面123a暴露於模製材料146之上表面247處。在其他實施例中，形成且接著磨削模製材料146以平坦化上表面247且藉此暴露第二半導體晶粒120之上表面123a。如圖2H中所進一步展示，在一些實施例 中，模製材料146囊封第一半導體晶粒110、導線接合104及導電構件106，使得此等構件密封於模製材料146內。
圖2I繪示(a)使封裝基板130與載體250(圖2H)分離且(b)在封裝基板130之第三接點136上形成電連接器108之後之半導體裝置100。在一些實施例中，真空、桿銷、雷射或其他光源或此項技術中已知之其他適合方法可使封裝基板130脫離釋放層252(圖2H)。在特定實施例中，釋放層252(圖2H)允許載體250被容易地移除，使得載體250可被再次重新使用。在其他實施例中，可藉由薄化載體250及/或釋放層252(例如使用背面研磨、乾式蝕刻程序、化學蝕刻程序、化學機械拋光(CMP)等等)來至少部分移除載體250及釋放層252。移除載體250及釋放層252暴露封裝基板130之第二表面133b(其包含第三接點136)。電連接器108形成於第三接點136上且可經組態以將第三接點136電耦合至外部電路(圖中未展示)。在一些實施例中，電連接器108包括複數個焊球或焊料凸塊。例如，一模板印刷機可將焊料膏之離散區塊沈積至第三接點136上，接著可回焊焊料膏以在第三接點136上形成焊球或焊料凸塊。
圖2J展示彼此分割之後之半導體裝置100。如圖中所展示，可在複數個切割道255(如圖2I中所繪示)處切割封裝基板130及模製材料146以分割堆疊半導體晶粒110、120且使半導體裝置100彼此分離。一旦被分割，個別半導體裝置100可經由電連接器108附著至外部電路且因此併入至各種系統及/或裝置中。
圖3A係一橫截面圖且圖3B係一俯視圖，其等繪示根據本發明之另一實施例之一半導體裝置300(「裝置300」)。此實例更明確地展示具有兩個以上堆疊半導體晶粒之根據本發明所組態之另一半導體裝 置。裝置300可包含大體上類似於上文所詳細描述之半導體裝置100之構件之構件。例如，在圖3A所繪示之實施例中，裝置300包含由一封裝基板330(例如不包含一預成形基板之一重佈結構)承載之一第一半導體晶粒310及一第二半導體晶粒320(統稱為「半導體晶粒310、320」)。更明確而言，第二半導體晶粒320堆疊於第一半導體晶粒310上方且自第一半導體晶粒310橫向偏移以界定第二半導體晶粒320之一外伸部分324及第一半導體晶粒310之一敞露部分314。第一半導體晶粒310具有經由一第一晶粒附著材料342附著至封裝基板330之一下表面313b及面向第二半導體晶粒320且具有暴露於第一半導體晶粒310之敞露部分314處之第一接合墊312之一上表面313a。第二半導體晶粒320具有經由一第二晶粒附著材料344部分附著至第一半導體晶粒310之上表面313a之一下表面323b及與下表面323b對置之一上表面323a。第二半導體晶粒320進一步包含下表面323b上之第二接合墊322，其暴露於第二半導體晶粒320之外伸部分324處且面向封裝基板330。封裝基板330包含第一接點332及第二接點334。第一導線接合304將第一接合墊312電耦合至封裝基板330之第一接點332，且第一導電構件306將第二接合墊322電耦合至封裝基板330之第二接點334。第一接點332及第二接點334經由導線338電耦合至封裝基板之對應第三接點336。
裝置300進一步包含堆疊於半導體晶粒310、320上方之一第三半導體晶粒360及一第四半導體晶粒370(統稱為「半導體晶粒360、370」)。半導體晶粒360、370可大體上類似於半導體晶粒110、120(圖1)及半導體晶粒310、320來配置。例如，如圖3A之實施例中所繪示，第四半導體晶粒370可自第三半導體晶粒360橫向偏移以界定第四半導體晶粒 370之一外伸部分374及第三半導體晶粒360之一敞露部分364。更特定而言，參考圖3B，第三半導體晶粒360可具有對置第一側316及對置第二側318。如圖中所展示，第四半導體晶粒370可僅延伸超過第三半導體晶粒360之第一側316之一者(圖3B中以虛線展示)(例如，沿大體上平行於第二側318之一軸線X3之一方向)以界定外伸部分374。在一些實施例中，半導體晶粒360、370之橫向偏移量(例如沿軸線X3之一距離)相同於或實質上相同於半導體晶粒310、320之橫向偏移。再者，如圖3B之俯視圖中所更清楚繪示，半導體晶粒310、320及半導體晶粒360、370可沿相同或實質上相同方向(例如，沿軸線X3之一方向)橫向偏移。在其他實施例中，半導體晶粒310、320及半導體晶粒360、370可沿一個以上方向偏移或偏移不同量(例如，第二半導體晶粒320之外伸部分324及第四半導體晶粒370之外伸部分374可具有不同形狀、定向及/或尺寸)。
第三半導體晶粒360可具有經由一第三晶粒附著材料348附著至第二半導體晶粒320之上表面323a之一下表面363b及面向第四半導體晶粒370且具有暴露於第三半導體晶粒360之敞露部分364處之第三接合墊362之一上表面363a。第四半導體晶粒370具有一上表面373a及經由一第四晶粒附著材料349部分附著至第三半導體晶粒360之上表面363a之一下表面373b。第四半導體晶粒370之下表面373b包含外伸部分374處之第四接合墊372。第四接合墊372定位於封裝基板330之第二接點334之至少一部分上方(例如，與封裝基板330之第二接點334之至少一部分垂直對準，疊置於封裝基板330之第二接點334之至少一部分上方，等等)。
裝置300進一步包含：(a)第二導線接合368，其等將第三半導體晶粒360之第三接合墊362電耦合至封裝基板330之第一接點332之 對應者；及(b)第二導電構件376，其等將第四半導體晶粒370之第四接合墊372電耦合至封裝基板330之第二接點334之對應者。在特定實施例中，封裝基板330上方及/或第三半導體晶粒360之上表面363a上方之第二導線接合368之一最大高度不大於封裝基板330上方及/或第三半導體晶粒360之上表面363a上方之第四半導體晶粒370之一高度。如圖3B之實施例中所繪示，第一接點332及第二接點334(圖中未繪製；位於以虛線展示之第二接合墊322及第四接合墊372下方)可配置成一或多個行(例如兩行)且可各耦合至各種半導體晶粒之接合墊之一或多者。在其他實施例中，第一接點332及第二接點334之配置可具有任何其他適合組態(例如，配置成一個行，配置成數個列、偏移列及/或行，等等)。第一導電構件306及第二導電構件376可具有各種適合結構(諸如支柱、柱、短軸、凸塊等等)且可由銅、鎳、焊料(例如基於SnAg之焊料)、填充有導體之環氧樹脂及/或其他導電材料製成。
顯而易見，裝置300中之各半導體晶粒直接電耦合至封裝基板330之第一接點332或第二接點334。因此，第一半導體晶粒310、第二半導體晶粒320、第三半導體晶粒360及第四半導體晶粒370(統稱為「半導體晶粒310至370」)之任何者之間無需互連件或其他結構來將半導體晶粒310至370電連接至封裝基板330。例如，在一些實施例中可經由第二晶粒附著材料344、第三晶粒附著材料348及第四晶粒附著材料349之一或多者將半導體晶粒310至370耦合在一起以替代半導體晶粒310至370之間之互連結構(例如RDL)。在一些實施例中，裝置300中之各晶粒附著材料係相同材料及/或具有相同厚度。
裝置300可進一步包含封裝基板330之一上表面上方之一模 製材料346(為便於繪示，圖3B中未展示模製材料346)。在一些實施例中，模製材料346至少部分包圍半導體晶粒310至370、第一導線接合304及第二導線接合368及/或第一導電構件306及第二導電構件376以保護此等組件之一或多者免受污染及/或實體損壞。例如，在圖3A所繪示之實施例中，僅第四半導體晶粒370之上表面373a自模製材料346暴露。顯而易見，模製材料346未相對於封裝基板330延伸超過第四半導體晶粒370(例如，超過與第四半導體晶粒370之上表面373a共面之一平面)，同時仍囊封第一導線接合304及第二導線接合368及第一導電構件306及第二導電構件376。因此，可相較於(例如)具有耦合裝置中之最上晶粒之導線接合且因此具有高於最上晶粒之一線環高度之習知半導體裝置而減小裝置300之高度(例如厚度)。同樣地，由於模製材料346無需延伸超過第四半導體晶粒370之上表面373a，所以可減少裝置300中所使用之模製材料346之總量(例如，進而降低裝置300之成本及/或翹曲)。
圖4係根據本發明之另一實施例之一半導體裝置400(「裝置400」)之一俯視圖。此實例更明確地繪示沿半導體裝置之兩個軸線橫向偏移之堆疊半導體晶粒。裝置400可包含大體上類似於上文所詳細描述之半導體裝置100之構件之構件。例如，裝置400包含耦合至一封裝基板430之一第一半導體晶粒410及堆疊於第一半導體晶粒410上方且自第一半導體晶粒410橫向偏移之一第二半導體晶粒420(統稱為「半導體晶粒410、420」)。與參考圖1A至圖3B所詳細描述之諸多實施例相比，第二半導體晶粒420自第一半導體晶粒410之兩側橫向偏移。更明確而言，第一半導體晶粒410可包含對置第一側416及對置第二側418。第二半導體晶粒420可延伸超過(例如，沿大體上平行於第二側418之一軸線X4之一方向)第一 側416之一者(以虛線部分展示)且超過(例如，沿大體上平行於第一側416之一軸線Y4之一方向)第二側418之一者(以虛線部分展示)以界定第二半導體晶粒420之一外伸部分424及第一半導體晶粒410之一敞露部分414。在圖4所繪示之實施例中，第二半導體晶粒420之外伸部分424及第一半導體晶粒410之敞露部分414具有一大體上呈「L形」形狀。在一些實施例中，當半導體晶粒410、420具有相同平面形狀及尺寸時，敞露部分414及外伸部分424之尺寸可相同。在其他實施例中，半導體晶粒410、420可具有不同平面形狀及/或尺寸，使得外伸部分424及敞露部分414具有不同形狀及/或尺寸。例如，當兩個半導體晶粒410、420之一者大於另一者時，敞露部分414及/或外伸部分424可具有沿較大晶粒之三個邊緣之一大體上呈「U形」形狀。
如圖4中所進一步展示，第一半導體晶粒410可具有位於第一半導體晶粒410之一上表面上且暴露於敞露部分414處之第一接合墊412。類似地，第二半導體晶粒420可具有位於第二半導體晶粒420之一下表面上、暴露於外伸部分424處及面向封裝基板430之第二接合墊422(圖中以虛線展示)。如圖4中所繪示，第一接合墊412及第二接合墊422(統稱為「接合墊412、422」)可分別沿第一半導體晶粒410之敞露部分414及第二半導體晶粒420之外伸部分424配置成一L形形狀。在其他實施例中，接合墊412、422可具有其他配置(例如，定位成僅相鄰於半導體晶粒410、420之一單一側，定位成一個以上列及/或行，等等)。在特定實施例中，半導體晶粒410、420取決於半導體晶粒410、420之接合墊412、422之組態而橫向偏移。例如，半導體晶粒410、420之偏移可經選擇使得第一半導體晶粒410之第一接合墊412之各者暴露於敞露部分414處且第二半導體 晶粒420之第二接合墊422之各者暴露於外伸部分424處。
封裝基板430可包含第一接點432及第二接點(在圖4中被遮蔽；例如，垂直對準於第二接合墊422下方)。裝置400進一步包含：導線接合404，其等將第一半導體晶粒410之第一接合墊412電耦合至封裝基板430之第一接點432；及導電構件(圖中未繪製；例如導電支柱)，其等將第二半導體晶粒420之第二接合墊422電耦合至封裝基板430之第二接點。第一接點432及第二接點可具有任何適合配置。例如，在一些實施例中，封裝基板430係不包含一預成形基板且添加地堆積(圖2A至圖2D)之一重佈結構。因此，封裝基板430可為可適應半導體晶粒410、420及接合墊412、422之特定配置之一撓性結構。
具有上文參考圖1A至圖4所描述之構件之半導體裝置之任何者可併入至各種更大及/或更複雜系統之任何者中，圖5中所示意性展示之系統500係該等系統之一代表性實例。系統500可包含一處理器502、一記憶體504(例如SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置505及/或其他子系統或組件508。上文參考圖1A至圖4所描述之半導體裝置可包含於圖5所展示之元件之任何者中。所得系統500可經組態以執行各種適合運算、處理、儲存、感測、成像及/或其他功能之任何者。因此，系統500之代表性實例包含(但不限於)電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路設備、手持式裝置(例如掌上型電腦、可穿戴電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等等)、平板電腦、多處理器系統、基於處理器或可程式化之消費型電子產品、網路電腦及迷你電腦。系統500之額外代表性實例包含燈、相機、車輛等等。關於此等及其他實例，系統500可收容於一單一單元中或 分佈於多個互連單元上(例如，透過一通信網路)。因此，系統500之組件可包含本端及/或遠端記憶體儲存裝置及各種適合電腦可讀媒體之任何者。
應自上文瞭解，本文已為了說明而描述本發明之特定實施例，但可在不背離本發明的情況下作出各種修改。此外，亦可在其他實施例中組合或消除特定實施例之內文中所描述之本發明之特定態樣。例如，參考圖1A至圖4所描述之各種實施例可經組合以併入依不同方式橫向偏移之不同數目個堆疊半導體晶粒(例如3個晶粒、5個晶粒、6個晶粒、8個晶粒等等)。因此，本發明僅受限於隨附申請專利範圍。再者，儘管已在該等實施例之內文中描述與新技術之特定實施例相關聯之優點，但其他實施例亦可展示此等優點，且未必需要落入本發明之範疇內之全部實施例展現此等優點。因此，本發明及相關聯技術可涵蓋本文中未明確展示或描述之其他實施例。
100:半導體裝置
104:導線接合
106:導電構件
108:電連接器
110:第一半導體晶粒
112:第一接合墊
113a:上表面
113b:下表面
114:敞露部分
120:第二半導體晶粒
122:第二接合墊
123a:上表面
123b:下表面
124:外伸部分
130:封裝基板
132:第一接點
133a:第一側/第一表面
133b:第二側/第二表面
134:第二接點
135:絕緣材料
136:第三接點
138:導線
142:第一晶粒附著材料
144:第二晶粒附著材料
146:模製材料
D:距離

Claims (24)

  1. 一種製造一半導體裝置之方法，該方法包括：形成位於一重佈結構之一第一表面上且電耦合至該重佈結構之數個導電支柱，其中該第一表面與一第二表面對置，且其中該重佈結構不包含在該第一表面與該第二表面之間的一預成形基板；將一第一半導體晶粒耦合至該重佈結構之該第一表面；經由導線接合將該第一半導體晶粒之第一接合墊電耦合至該重佈結構；將一第二半導體晶粒耦合至該第一半導體晶粒及該等導電支柱，其中該等導電支柱將該第二半導體晶粒之第二接合墊電耦合至該重佈結構；形成位於該重佈結構之該第一表面上方且至少部分圍繞該第一半導體晶粒、該等導電支柱、該等導線接合及該第二半導體晶粒之一模製材料；及在該第二表面上形成數個導電元件，該等導電元件經由該重佈結構電耦合至該等導電支柱及/或該等導線接合之一或多者。
  2. 如請求項1之方法，其中該模製材料不相對於該重佈結構延伸超過該第二半導體晶粒。
  3. 如請求項1之方法，其進一步包括：在一載體上形成該重佈結構；在形成該模製材料之後，移除該載體以暴露該重佈結構之該第二表 面。
  4. 如請求項1之方法，其中將該第二半導體晶粒耦合至該等導電支柱包含：將該第二半導體晶粒之該等第二接合墊熱壓接合至該等導電支柱。
  5. 如請求項3之方法，其中在該載體上形成該重佈結構包含在該載體上形成複數個導電及介電材料層。
  6. 一種半導體裝置，其包括：一重佈結構，其具有一上表面及與該上表面對置的一下表面，其中該重佈結構不包含在該上表面與該下表面之間的一預成形基板；一第一半導體晶粒，其耦合至該重佈結構且具有背向該重佈結構之一上表面，其中該第一半導體晶粒之該上表面包含數個第一接合墊；數個第一導線接合，其等將該第一半導體晶粒之該等第一接合墊電耦合至該重佈結構；一第二半導體晶粒，其具有面向該重佈結構之一下表面及背向該重佈結構之一上表面，其中該第二半導體晶粒之該下表面耦合至該第一半導體晶粒之該上表面，其中該第二半導體晶粒橫向延伸超過該第一半導體晶粒之至少一側以界定該第二半導體晶粒之一外伸部分，且其中該第二半導體晶粒之該下表面包含該外伸部分處之數個第二接合墊；數個導電構件，其等將該第二半導體晶粒之該等第二接合墊電耦合至該重佈結構；一第三半導體晶粒，其具有面向該重佈結構之一下表面及背向該重 佈結構之一上表面，其中該第三半導體晶粒之該下表面整個位在該第二半導體晶粒之該上表面上方且耦合至該第二半導體晶粒之該上表面，且其中該第三半導體晶粒之該上表面包含數個第三接合墊；及數個第二導線接合，其等將該第三半導體晶粒之該等第三接合墊電耦合至該重佈結構。
  7. 如請求項6之半導體裝置，其中該第三半導體晶粒之該下表面整個經由一晶粒附著材料直接地貼附至該第二半導體晶粒之該上表面。
  8. 如請求項6之半導體裝置，其中該第二半導體晶粒及該第三半導體晶粒具有相同平面形狀及尺寸。
  9. 如請求項6之半導體裝置，其中該第二半導體晶粒之該上表面及該第三半導體晶粒之該下表面具有相同形狀及尺寸，使得該第三半導體晶粒之該下表面整個直接相鄰於該第二半導體晶粒之該上表面。
  10. 如請求項6之半導體裝置，其進一步包括：一第四半導體晶粒，其具有面向該重佈結構之一下表面及背向該重佈結構之一上表面，其中該第四半導體晶粒之該下表面耦合至該第三半導體晶粒之該上表面，其中該第四半導體晶粒橫向延伸超過該第三半導體晶粒之至少一側以界定該第四半導體晶粒之一外伸部分，且其中該第四半導體晶粒之該下表面包含該第四半導體晶粒之該外伸部分處之數個第四接合墊；及 數個第二導電構件，其等將該第四半導體晶粒之該等第四接合墊電耦合至該重佈結構。
  11. 如請求項10之半導體裝置，其進一步包括該重佈結構上方之一模製材料，其中該模製材料不從該重佈結構延伸超過一平面，該平面與該第四半導體晶粒之該上表面共面。
  12. 如請求項10之半導體裝置，其中該第二半導體晶粒之該外伸部分及該第四半導體晶粒之該外伸部分具有相同形狀及尺寸。
  13. 如請求項10之半導體裝置，其中該第二半導體晶粒在一方向上橫向延伸超過該第一半導體晶粒之該至少一側，且其中該第四半導體晶粒在相同的該方向上橫向延伸超過該第三半導體晶粒之該至少一側。
  14. 如請求項10之半導體裝置，其中該等第一導電構件及該等第二導電構件係導電支柱。
  15. 如請求項10之半導體裝置，其中該第一半導體晶粒包含對置第一側及對置第二側，且其中該第二半導體晶粒僅橫向延伸超過該第一半導體晶粒之該等第一側之一者或該等第二側之一者。
  16. 如請求項15之半導體裝置，其中該第三半導體晶粒包含對置第一側及對置第二側，且其中該第四半導體晶粒僅橫向延伸超過該第三半導體晶 粒之該等第一側之一者或該等第二側之一者。
  17. 如請求項15之半導體裝置，其中該第四半導體晶粒橫向延伸超過該第一半導體晶粒之該等第一側之一者及該等第二側之一者。
  18. 如請求項10之半導體裝置，其中該第一半導體晶粒、該第二半導體晶粒、該第三半導體晶粒、及該第四半導體晶粒係相同的，且其中該第一半導體晶粒上之該等第一接合墊之一配置相同於(a)該第二半導體晶粒上之該等第二接合墊之一配置、(b)該第三半導體晶粒上之該等第三接合墊之一配置、及(c)該第四半導體晶粒上之該等第四接合墊之一配置。
  19. 如請求項6之半導體裝置，其中該第一半導體晶粒包含一對對置側，且其中該第二半導體晶粒僅沿延伸於該對對置側之間且平行於該對對置側之一軸線自該第一半導體晶粒橫向偏移。
  20. 如請求項6之半導體裝置，其中該重佈結構之該上表面與該下表面之間之一厚度小於約50μm。
  21. 如請求項6之半導體裝置，其中該重佈結構包含由一添加堆積程序形成之複數個導電及介電材料層。
  22. 一種半導體裝置，其包括：一重佈結構，其具有一上表面及與該上表面對置的一下表面，其中 該重佈結構不包含在該上表面與該下表面之間的一預成形基板；一第一半導體晶粒，其耦合至該重佈結構且具有背向該重佈結構之一上表面，其中該第一半導體晶粒之該上表面包含數個第一接合墊；數個第一導線接合，其等將該第一半導體晶粒之該等第一接合墊電耦合至該重佈結構；一第二半導體晶粒，其具有面向該重佈結構之一下表面及背向該重佈結構之一上表面，其中該第二半導體晶粒之該下表面耦合至該第一半導體晶粒之該上表面，其中該第二半導體晶粒在一方向上橫向延伸超過該第一半導體晶粒之至少一側以界定該第二半導體晶粒之一外伸部分，且其中該第二半導體晶粒之該下表面包含該外伸部分處之數個第二接合墊；數個第一導電柱，其等將該第二半導體晶粒之該等第二接合墊電耦合至該重佈結構；一第三半導體晶粒，其具有面向該重佈結構之一下表面及背向該重佈結構之一上表面，其中該第三半導體晶粒之該下表面整個位在該第二半導體晶粒之該上表面上方且耦合至該第二半導體晶粒之該上表面，且其中該第三半導體晶粒之該上表面包含數個第三接合墊；數個第二導線接合，其等將該第三半導體晶粒之該等第三接合墊電耦合至該重佈結構；一第四半導體晶粒，其具有面向該重佈結構之一下表面及背向該重佈結構之一上表面，其中該第四半導體晶粒之該下表面耦合至該第三半導體晶粒之該上表面，其中該第四半導體晶粒在該方向上橫向延伸超過該第三半導體晶粒之至少一側以界定該第四半導體晶粒之一外伸部分，且其中該第四半導體晶粒之該下表面包含該第四半導體晶粒之該外伸部分處之數 個第四接合墊；及數個第二導電柱，其等將該第四半導體晶粒之該等第四接合墊電耦合至該重佈結構。
  23. 如請求項22之半導體裝置，其中該第二半導體晶粒之該外伸部分及該第四半導體晶粒之該外伸部分具有相同形狀及尺寸。
  24. 如請求項22之半導體裝置，其中該第二半導體晶粒之該上表面及該第三半導體晶粒之該下表面具有相同形狀及尺寸，使得該第三半導體晶粒之該下表面整個直接相鄰於該第二半導體晶粒之該上表面。
TW107126265A 2017-08-24 2018-07-30 具有橫向偏移堆疊之半導體晶粒之半導體裝置及製造其之方法 TWI757526B (zh)

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