TW201725687A - 包含不同尺寸的封裝穿孔的封裝上封裝構件 - Google Patents

包含不同尺寸的封裝穿孔的封裝上封裝構件 Download PDF

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TW201725687A
TW201725687A TW105104841A TW105104841A TW201725687A TW 201725687 A TW201725687 A TW 201725687A TW 105104841 A TW105104841 A TW 105104841A TW 105104841 A TW105104841 A TW 105104841A TW 201725687 A TW201725687 A TW 201725687A
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die
package
layer structure
vias
redistribution layer
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TW105104841A
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TWI578483B (zh
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施信益
吳鐵將
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美光科技公司
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本發明披露一種封裝上封裝構件,包含一底部封裝以及一疊設於該底部封裝上的頂部封裝。底部封裝包含一重佈線層結構、至少一晶粒,設於該重佈線層結構上並且被一成型模料包覆、複數個位於該晶粒中的穿矽通孔(TSVs)、複數個沿著該晶粒週邊設置的穿模通孔(TMVs),以及複數個焊錫凸塊或錫球。其中各該穿模通孔的孔徑大於各該穿矽通孔的孔徑。頂部封裝是經由該穿矽通孔(TSVs)與該穿模通孔(TMVs)與該底部封裝電連接。

Description

包含不同尺寸的封裝穿孔的封裝上封裝構件
本發明概括而言係關於半導體封裝領域,特別係關於一種包含不同尺寸的封裝穿孔的封裝上封裝構件,可用來將不同功能的晶片封裝至一封裝體中。
隨著日新月異的半導體製造技術,微電子組件的尺寸越來越小,其中的電路也越來越密集。為了進一步縮小尺寸,安裝在電路板的微電子組件封裝結構也必須更加緊密。
3D封裝技術,例如封裝上封裝技術,可製作出具有較高集程度以及較緊密封裝接腳的封裝構件。一般而言,封裝上封裝構件包含一個位於頂部的半導體晶粒封裝體,接合到另一個位於底部的晶粒封裝體。習知的封裝上封裝構件,多是藉由位於周圍的錫球或穿模通孔,使頂部封裝體和底部封裝體電連接。
然而,習知的封裝上封裝構件,無法實現極緊密的堆疊結構。另外,習知的封裝上封裝構件體積較大並且容易發生翹曲的問題。因此,本技術領域仍要一個改良的封裝上封裝構件,包含利用不同尺寸的封裝穿孔,將不同功能的晶片安裝在一起,形成一個具有較緊密堆疊結構的封裝體。
本發明主要目的為提供一改良的封裝上封裝構件,其中包含不同尺寸的通孔結構。
本發明一方面提供一種封裝上封裝構件,包含一底部封裝以及一疊設於該底部封裝上的頂部封裝。底部封裝包含一重佈線層結構,其中該重佈線層結構具有一第一面及相對該第一面的一第二面;至少一晶粒,設於該第一面上;一成型模料,設於該第一面並包覆該晶粒;複數個穿矽通孔,位於該晶粒中;複數個穿模通孔,設於一週邊區域且貫穿該第一面上的該成型模料,其中各該穿模通孔的孔徑大於各該穿矽通孔的孔徑。複數個焊錫凸塊或錫球,設於該第二面上。頂部封裝是經由該穿矽通孔(TSVs)與該穿模通孔(TMVs)與該底部封裝電連接。
本發明另一方面提供一種重佈線層先製(RDL-first)的半導體元件製作方法,其中包含提供一載板,並於於該載板上形成一重佈線層結構。接著,於該重佈線層結構上形成一鈍化層。接著,在該重佈線層結構上形成凸塊,並於該重佈線層結構上安置一晶粒。該晶粒包含複數個穿矽通孔(TSVs),且該晶粒係透過該凸塊與該重佈線層結構電連接。接著,以一成型模料模封該晶粒,並研磨該成型模料與該晶粒,以顯露出各該穿矽通孔的一端面。接著,在該晶粒周圍的該成型模料中形成複數個穿模通孔(TMVs)。
本發明再另一方面提供一種晶片先製(chip-first)的半導體元件製作方法,其中包含提供一載板,於該第一載板上設置一晶粒,其中該晶粒包含複數個穿矽通孔。接著,以一成型模料模封該晶粒,並於該晶粒的一主動面上及該成型模料表面上形成一重佈線層結構。然後,於該重佈線層結構上形成一防銲層,並於該重佈線層結構上形成複數個焊錫凸塊或錫球。使該複數個焊錫凸塊或錫球貼合置一第二載板後,研磨該成型模料與該晶粒,以顯露出各該穿矽通孔的一端面。接著,在該晶粒周圍的該成型模料中形成複數個穿模通孔。
無庸置疑的,該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後,均可了解本發明的目的。
接下來的詳細敘述須參照相關圖式所示內容,用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節,可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內,可做結構、邏輯和電性上的修改應用在其他實施例上。
因此,接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者,也應屬本發明涵蓋的範圍。
下面的描述須參照相關附圖內容以便徹底理解本發明,其中相同或類似的特徵通常以相同的附圖標記描述,描述的結構並不必然按比例繪製。
在本說明書中,“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意,可交替使用。
在本說明書中,“晶圓”、“基板”和“載板”意指任何包含一暴露面,可依據本發明實施例所示在其上沉積材料,製作積體電路結構的結構物,例如重佈線層。須了解的是“基板” 和“載板”包含半導體晶圓,但並不限於此。"基板"和“載板”在製程中也意指包含製作於其上的材料層的半導體結構物。
首先,請參考第1圖和第2圖。第1圖為根據本發明一實施例的封裝上封裝構件1的示意性剖面圖,其中包含不同大小的封裝穿孔(TAVs)100。第2圖為第1圖所示實施例的封裝上封裝構件的封裝穿孔(TAVs)的設置和佈局的示意圖。
如第1圖和第2圖所示,封裝上封裝構件1包含一底部封裝10以及一疊設於底部封裝10上的頂部封裝20。底部封裝10包含重佈線層結構400。重佈線層結構400包含第一面400a及相對於第一面400a的第二面400b。重佈線層結構400包含介電層412,以及位於介電層412中的至少一層金屬層414。介電層412可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者,但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似者,但不限於此。須了解的是,圖中所示金屬層414的配置和疊層僅為便於說明和描述的目的,並非本發明的限制。重佈線層結構400可另包含鈍化層413和鈍化層415。可選擇性的在鈍化層415上設置防焊層419。
半導體晶粒(晶粒)420安裝在重佈線層結構400第一面400a的晶片安裝區201內。晶粒420包含一直接面向重佈線層結構400的主動面420a。複數個凸塊(或微凸塊)104設置在主動面420a以及重佈線層結構400之間,用來將晶粒420與重佈線層結構400電連接。晶粒420中包含複數個穿矽通孔(TSVs)110,延伸於晶粒420的主動面420a與暴露的下表面420c 之間。穿矽通孔110可由習知的製程步驟製作。穿矽通孔110可沿著晶粒420的邊緣設置,但並不限於此。
晶粒420的主動面420a上可包含複數個輸入/輸出(I/O)接墊(圖未示),分別與對應的凸塊104對準。雖然圖中並未特別標示,但該領域的技術人員應可理解在輸入/輸出接墊上可設有凸塊或柱狀體,例如銅柱。雖然第1圖中的底部封裝10僅繪示一個晶粒420,但在其他實施例中,也可包含複數個晶粒。
成型模料500設於第一面400a上,包覆晶粒420並覆蓋住重佈線層結構400。根據本發明一實施例,可藉由一固化製程(curing process)使成型模料500固化。根據本發明一實施例,成型模料500可包含環氧樹脂(epoxy)和矽石填充物(silica fillers),但不限於此。晶粒420的下表面420c與成型模料500的上表面齊平。
底部封裝10的週邊區域202中可包含複數個穿模通孔(TMVs)210。週邊區域202鄰近晶片安裝區201。穿模通孔210可沿著晶粒420的周圍排列,但不限於此。穿模通孔210貫穿成型模料500以及鈍化層413,與重佈線層結構400的金屬層414電連接。根據本發明一實施例,穿矽通孔110具有孔徑r1 ,r1 小於穿模通孔210的孔徑r2 。在下文中,可將穿矽通孔110與穿模通孔210通稱為封裝穿孔(through assembly vias, TAVs) 100。
根據本發明一實施例,穿矽通孔110可用來傳遞信號,例如高頻的信號或類似者。穿模通孔210可用來傳遞功率或接地信號,但不限於此。
在一些實施例中,穿模通孔210可以僅沿著晶粒420的邊緣420b的其中三邊設置。例如第3圖所示實施例,底部封裝10a的成型模料500中,包含兩個並排的晶粒,分別是晶粒420’以及晶粒420”。穿模通孔210可沿著底部封裝10a的週邊區域設置。第3圖中,穿模通孔210僅沿著晶粒420’以及晶粒420”個別的邊緣420b的其中三邊設置。須了解的是,第3圖所示的穿模通孔210的設置方式僅為說明和描述的目的,並非本發明的限制。穿模通孔210的配置與佈局須根據實際設計上的需求。
回到第1圖。頂部封裝20分別藉由焊錫凸塊(或錫球)250a和250b,與對應的穿矽通孔110和穿模通孔210電性連接。根據本發明一實施例,焊錫凸塊(或錫球)250a是與穿矽通孔110對準,焊錫凸塊(或錫球)250b是與穿模通孔210對準。頂部封裝20可包含一已模封的半導體晶片220。
請參考第4圖至第11圖,為根據本發明一實施例的製作方法的示意性剖面圖,可製得如第1圖所示,包含不同大小的封裝穿孔(TAVs)的封裝上封裝構件。
首先,如第4圖所示,提供一預備好的載板300。載板300可為包含黏著層302的可卸式的基底材料,但不限於此。
接著,在載板300上形成重佈線層結構400。載板300的上表面形成至少一介電層或鈍化層415。鈍化層415可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者。
然後,在鈍化層415上形成至少一層介電層412和一層金屬層414。介電層412可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者,但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似者。根據本發明一實施例,金屬層414包含複數個自介電層412的上表面暴露出來的焊墊414a。
然後,形成鈍化層413。鈍化層413覆蓋住介電層412和焊墊414a。鈍化層413可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者。
如第5圖所示,接著可在鈍化層413中形成開孔(圖未示),使個別的焊墊414a暴露出來。可利用例如習知的焊錫凸塊電鍍法,在暴露出來的個別的焊墊414a上形成凸塊416a,然後將覆晶晶片或晶粒420以主動面420a朝下面向重佈線層結構400的方位安裝至凸塊416a上,形成晶片對晶圓(chip-to-wafer, C2P)接合的堆疊結構。
晶粒420的主動面420a上可包含複數個輸入/輸出(I/O)接墊421。輸入/輸出接墊421與凸塊416a對準。晶粒420可為具特定功能的主動積體電路晶片,例如,繪圖處理器(GPUs)、中央處理器(CPUs),記憶體晶片等,但不限於此。雖然未繪示於圖中,但熟習本領域技術者應可理解,可在輸入/輸出接墊421上形成凸塊或銅柱體,以供後續連接使用。
根據本發明一實施例,每個晶粒420可包含沿著晶粒420邊緣設置的穿矽通孔(TSVs)110。穿矽通孔110可以是沿著晶粒420的四邊420b設置,但不限於此。例如,在一些實施例中,穿矽通孔110可以僅沿著晶粒420的四邊420b其中的三邊設置。
如第6圖所示,接著塗佈成型模料500。成型模料500覆蓋住晶粒420。可藉由一固化製程(curing process)使成型模料500固化。根據本發明一實施例,成型模料500可包含環氧樹脂(epoxy)和矽石填充物(silica fillers),但不限於此。
如第7圖所示,接著可以用研磨的方法,移除部分成型模料500的頂部,使每一個晶粒420的下表面420c暴露出來。在研磨成型模料500的過程中,晶片420的一部分也會被移除掉,使每一個穿矽通孔110的一端面暴露出來。此時,暴露出來的晶粒420的下表面420c與成型模料500的上表面齊平。
如第8圖所示,接著可在成型模料500和鈍化層413中形成複數個開孔510,連通重佈線層結構400的金屬層414。根據本發明一實施例,可藉由雷射鑽孔的方式形成開孔510,但不限於此。可在開孔510中填入例如金屬層,形成穿模通孔(TMVs)210。
接下來,如第9圖和第10圖所示,移除載板300和黏著層302,使鈍化層415的一表面暴露出來。剝離載板300的方法可利用例如雷射剝離法、紫外光照射法、研磨法或蝕刻法,但不限於此。剝離載板300後,可在鈍化層415暴露出來的表面上形成防焊層419。接著,在鈍化層415和防焊層419中形成開孔(圖未示),暴露出位於金屬層414中個別的焊墊(solder pad)。然後,可在暴露的個別的焊墊上形成焊錫凸塊或錫球520,供後續連接使用。接著,如第10圖所示,切割由上述步驟而製得的晶圓級封裝,得到個別的底部封裝10。
如第11圖所示,將包含已模封的半導體晶粒220的頂部封裝20疊設至底部封裝10上。頂部封裝20分別藉由焊錫凸塊250a和250b,與對應的穿矽通孔110和穿模通孔210電連接。
請參考第12圖至第18圖。第12圖至第18圖為根據本發明另一實施例的製作方法的示意性剖面圖,可製得包含不同大小的封裝穿孔(TAVs)的封裝上封裝構件。
如第12圖所示,同樣的,先提供一預備好的載板300。載板300可為包含黏著層302的可卸式的基底材料,但不限於此。接著,將晶粒420以主動面420a朝下面向載板300和下表面420c朝上的方位,安裝至載板300上。
晶粒420的主動面420a上可包含複數個輸入/輸出(I/O)接墊421。晶粒420可為具特定功能的主動積體電路晶片,例如,繪圖處理器(GPUs)、中央處理器(CPUs),記憶體晶片等,但不限於此。根據本發明一實施例,每個晶粒420可包含沿著晶粒420邊緣設置的穿矽通孔(TSVs)110。
如第13圖所示,接著塗佈成型模料500。成型模料500覆蓋住晶粒420以及黏著層302的上表面。可藉由一固化製程(curing process)使成型模料500固化。根據本發明一實施例,成型模料500可包含環氧樹脂(epoxy)和矽石填充物(silica fillers),但不限於此。接下來,移除載板300和黏著層302。
如第14圖所示,接著在暴露出來的晶粒420的主動面420a以及成型模料500的表面上,形成重佈線層結構400。重佈線層結構400包含至少一介電層412和一金屬層414。介電層412可包含有機材料,例如聚醯亞胺(polyimide, PI),或無機材料,例如氮化矽、氧化矽或類似者,但不限於此。屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似者。金屬層414與個別晶粒420的輸入/輸出(I/O)接墊421電連接。
接下來,在重佈線層結構400上形成防焊層419。可在防焊層419中形成開孔(圖未示),使金屬層414中的個別的焊墊(solder pad)暴露出來。可在暴露出來的個別的焊墊上形成焊錫凸塊或錫球520,供後續連接使用。
然後,如第15圖所示,藉由黏著層602,將錫球520貼合至另一載板600上。
如第16圖所示,利用研磨的方法,移除部分成型模料500的頂部以及部分晶粒420,使得穿矽通孔110的一端面自晶粒420的下表面420c暴露出來。接著,可在成型模料500中形成複數個開孔510,連通重佈線層結構400的金屬層414。根據本發明一實施例,開孔510可藉由雷射鑽孔的方式形成,但不限於此。接著,可在開孔510中填入例如金屬層,形成穿模通孔(TMVs)210。
接著,如第17圖和第18圖所示,在移除載板600和黏著層602後,切割由上述步驟製得的晶圓級封裝,得到個別的底部封裝10b。然後,將包含已模封的半導體晶粒220的頂部封裝20疊設至底部封裝10b上。頂部封裝20分別藉由焊錫凸塊250a和250b,與對應的穿矽通孔110和穿模通孔210電連接。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
1‧‧‧封裝上封裝構件
10、10a‧‧‧底部封裝
20‧‧‧頂部封裝
100‧‧‧封裝穿孔
104‧‧‧凸塊
110‧‧‧穿矽通孔
201‧‧‧晶片安裝區
202‧‧‧週邊區域
210‧‧‧穿模通孔
220‧‧‧半導體晶粒
250a、250b‧‧‧焊錫凸塊
300‧‧‧載板
302‧‧‧黏著層
400‧‧‧重佈線層結構
400a‧‧‧第一面
400b‧‧‧第二面
412‧‧‧介電層
414‧‧‧金屬層
413、415‧‧‧鈍化層
414a‧‧‧焊墊
416a‧‧‧凸塊
419‧‧‧防焊層
420、420'、420"‧‧‧晶粒
420a‧‧‧主動面
420b‧‧‧四邊
420c‧‧‧下表面
421‧‧‧輸入/輸出(I/O)接墊
500‧‧‧成型模料
510‧‧‧開孔
520‧‧‧錫球
600‧‧‧載板
602‧‧‧黏著層
第1圖為示意性剖面圖,說明根據本發明一實施例的封裝上封裝構件。    第2圖為說明如第1圖所示實施例的封裝上封裝構件中的封裝穿孔(TAVs)的設置和佈局的示意圖。    第3圖為說明另一實施例的封裝上封裝構件中的封裝穿孔(TAVs)的設置和佈局的示意圖。    第4圖至第11圖為示意性剖面圖,說明根據本發明一實施例,製作如第1圖所示,包含不同大小的封裝穿孔(TAVs) 的封裝上封裝構件的方法。    第12圖至第18圖為示意性剖面圖,說明根據本發明另一實施例,製作包含不同大小的封裝穿孔(TAVs)的封裝上封裝構件的方法。
1‧‧‧封裝上封裝構件
10‧‧‧底部封裝
20‧‧‧頂部封裝
100‧‧‧封裝穿孔
104‧‧‧凸塊
110‧‧‧穿矽通孔
201‧‧‧晶片安裝區
202‧‧‧週邊區域
210‧‧‧穿模通孔
220‧‧‧半導體晶粒
250a、250b‧‧‧焊錫凸塊
400‧‧‧重佈線層結構
400a‧‧‧第一面
400b‧‧‧第二面
412‧‧‧介電層
414‧‧‧金屬層
413、415‧‧‧鈍化層
419‧‧‧防焊層
500‧‧‧成型模料
520‧‧‧錫球
420‧‧‧晶粒
420a‧‧‧主動面
420c‧‧‧下表面

Claims (14)

  1. 一種封裝上封裝構件,包含:    一底部封裝,包含有: 一重佈線層結構,具有一第一面及相對該第一面的一第二面; 至少一晶粒,設於該第一面上; 一成型模料,設於該第一面並包覆該晶粒; 複數個穿矽通孔,位於該晶粒中; 複數個穿模通孔,設於一週邊區域且貫穿該第一面上的該成型模料,其中各該穿模通孔的孔徑大於各該穿矽通孔的孔徑;及 複數個焊錫凸塊或錫球,設於該第二面上;    一頂部封裝,疊設於該底部封裝上,且經由該穿矽通孔與該穿模通孔與該底部封裝電連接。
  2. 如申請專利範圍第1項所述的封裝上封裝構件,其中該重佈線層結構包含一介電層以及至少一金屬層,其中該金屬層位於該介電層中。
  3. 如申請專利範圍第2項所述的封裝上封裝構件,其中該重佈線層結構另包含一鈍化層。
  4. 如申請專利範圍第1項所述的封裝上封裝構件,其中該穿矽通孔係沿著該晶粒的邊緣設置。
  5. 如申請專利範圍第1項所述的封裝上封裝構件,其中另包含凸塊,位於該晶粒與該重佈線層結構之間。
  6. 一種製作半導體元件的方法,包含:    提供一載板;    於該載板上形成一重佈線層結構;    於該重佈線層結構上形成一鈍化層;    於該重佈線層結構上形成凸塊;    於該重佈線層結構上安置一晶粒,其中該晶粒包含複數個穿矽通孔,且該晶粒係透過該凸塊與該重佈線層結構電連接;    以一成型模料模封該晶粒;    研磨該成型模料與該晶粒,以顯露出各該穿矽通孔的一端面;及    在該晶粒周圍的該成型模料中形成複數個穿模通孔。
  7. 如申請專利範圍第6項所述的製作半導體元件的方法,其中各該穿模通孔的孔徑係大於各該穿矽通孔的孔徑。
  8. 如申請專利範圍第6項所述的製作半導體元件的方法,其中在形成該複數個穿模通孔之後,另包含: 移除該載板;    於該重佈線層結構上形成一防銲層;及    於該重佈線層結構上及該防銲層上形成複數個焊錫凸塊或錫球。
  9. 如申請專利範圍第6項所述的製作半導體元件的方法,其中該複數個穿矽通孔係沿著該晶粒的邊緣設置。
  10. 一種製作半導體元件的方法,包含:    提供一第一載板;    於該第一載板上設置一晶粒,其中該晶矽包含複數個穿矽通孔; 以一成型模料模封該晶粒;    於該晶粒的一主動面上及該成型模料表面上形成一重佈線層結構;    於該重佈線層結構上形成一防銲層; 於該重佈線層結構上形成複數個焊錫凸塊或錫球;    使該複數個焊錫凸塊或錫球貼合置一第二載板;    研磨該成型模料與該晶粒,以顯露出各該穿矽通孔的一端面;及    在該晶粒周圍的該成型模料中形成複數個穿模通孔。
  11. 如申請專利範圍第10項所述的製作半導體元件的方法,其中各該穿模通孔的孔徑係大於各該穿矽通孔的孔徑。
  12. 如申請專利範圍第10項所述的製作半導體元件的方法,其中該複數個穿矽通孔係沿著該晶粒的邊緣設置。
  13. 如申請專利範圍第10項所述的製作半導體元件的方法,其中在以該成型模料模封該晶粒之後,另包含:    移除該第一載板。
  14. 如申請專利範圍第10項所述的製作半導體元件的方法,其中在該晶粒周圍的該成型模料中形成複數個穿模通孔係包含:    於該成型模料中形成開孔,連通該重佈線層結構的一金屬層;及    將金屬填入該開孔。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10593568B2 (en) 2017-08-24 2020-03-17 Micron Technology, Inc. Thrumold post package with reverse build up hybrid additive structure
US11037910B2 (en) 2017-08-24 2021-06-15 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
TWI809012B (zh) * 2017-12-08 2023-07-21 美商應用材料股份有限公司 用於晶圓級晶粒橋接之方法及設備

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101933425B1 (ko) * 2017-11-30 2018-12-28 삼성전기 주식회사 반도체 패키지
DE102018130035B4 (de) 2018-09-28 2020-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package und verfahren
US10867879B2 (en) 2018-09-28 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11195823B2 (en) * 2019-02-01 2021-12-07 Nanya Technology Corporation Semiconductor package and manufacturing method thereof
CN110071084A (zh) * 2019-04-11 2019-07-30 广东气派科技有限公司 一种双面焊接封装产品及其组装方法
TWI697080B (zh) * 2019-04-17 2020-06-21 力成科技股份有限公司 晶片封裝結構及其製造方法
CN110957291A (zh) * 2019-12-18 2020-04-03 江苏中科智芯集成科技有限公司 一种晶圆级双面扇出结构及其封装方法
US11830851B2 (en) 2020-04-07 2023-11-28 Mediatek Inc. Semiconductor package structure
DE102021107982B4 (de) 2020-04-07 2024-02-22 Mediatek Inc. Halbleiter-packagestruktur

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148167B (zh) * 2010-02-08 2013-03-27 日月光半导体制造股份有限公司 可堆栈式封装结构的制造方法
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US9991190B2 (en) * 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US9165887B2 (en) * 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9818734B2 (en) * 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
US20140225248A1 (en) * 2013-02-13 2014-08-14 Qualcomm Incorporated Power distribution and thermal solution for direct stacked integrated circuits
US10381326B2 (en) * 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9852998B2 (en) * 2014-05-30 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Ring structures in device die

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10593568B2 (en) 2017-08-24 2020-03-17 Micron Technology, Inc. Thrumold post package with reverse build up hybrid additive structure
US11037910B2 (en) 2017-08-24 2021-06-15 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
TWI757526B (zh) * 2017-08-24 2022-03-11 美商美光科技公司 具有橫向偏移堆疊之半導體晶粒之半導體裝置及製造其之方法
US11929349B2 (en) 2017-08-24 2024-03-12 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
TWI809012B (zh) * 2017-12-08 2023-07-21 美商應用材料股份有限公司 用於晶圓級晶粒橋接之方法及設備

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