TWI809012B - 用於晶圓級晶粒橋接之方法及設備 - Google Patents

用於晶圓級晶粒橋接之方法及設備 Download PDF

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TWI809012B
TWI809012B TW107143545A TW107143545A TWI809012B TW I809012 B TWI809012 B TW I809012B TW 107143545 A TW107143545 A TW 107143545A TW 107143545 A TW107143545 A TW 107143545A TW I809012 B TWI809012 B TW I809012B
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rdl
die
mold layer
forming
electrical interconnect
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TW107143545A
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TW201926610A (zh
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熊健剛
艾文德 桑達羅傑
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美商應用材料股份有限公司
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Abstract

將晶圓級橋接晶粒用黏合劑層附貼到已經暫時地接合到載體的重分佈層（RDL）。在該RDL上和該橋接晶粒上形成電互連件並將其封裝在第一模層中。將多個晶粒耦接到該RDL和該橋接晶粒，使得晶粒電連接到該RDL的至少一個電互連件和該橋接晶粒的至少一個電互連件。在該第一模層上形成第二模層以封裝該多個晶粒。然後，破壞暫時接合並去除載體，從而暴露RDL連接。

Description

用於晶圓級晶粒橋接之方法及設備
本原理的實施方式總體涉及半導體製程。
積體電路通常根據所期望的功能由不同製程形成。一個功能的多個晶圓一般被構造在單個晶圓上，並且然後被切分以形成單個晶粒或「晶圓」。在其它實例中，多個晶圓可以具有多個功能並包括晶粒劃分和多個功能晶粒集成。晶圓具有輸入和輸出（「I/O」），晶圓的I/O需要電連接到其它晶圓的I/O連接。例如，處理晶圓可以需要連接到記憶體晶圓以正確地執行功能。一種電連結兩個晶圓的方式是使用稱為「橋接」的有源或無源元件。橋接提供從一個晶圓的I/O連接到另一個晶圓的I/O連接的路徑。橋接可以是具有無源連接路徑或具有有源功能的矽晶粒。然而，使用橋接來提供連接通常增加半導體元件的製造複雜性，並且因此也可能會限制可製造半導體元件的製造者。形成在基板中的橋接通常是如前述情況那樣，這可能會限制製造廠（晶圓的製造商）的製程，這與外包組裝和測試（OSAT）設施（限於晶圓級製造）相反。在橋接和晶圓放置之後形成重分佈層（RDL）的一些晶圓級製程存在因低RDL產量而不得不丟棄昂貴晶圓的風險。
因此，發明人已提供了一種用於形成晶圓級晶粒橋接的改進的方法和設備。
一種形成晶圓級橋接晶粒的方法的一些實施方式包括：形成重分佈層（RDL）；和將橋接晶粒附貼在所述RDL上，所述橋接晶粒在與所述RDL相對的暴露表面上具有電連接。
一種形成晶圓級橋接晶粒的方法的一些實施方式還包括：在載體上形成所述RDL；或使用所述橋接晶粒與所述RDL之間的黏合劑將所述橋接晶粒附貼在所述RDL上；或在所述RDL上形成至少一個電互連件；在所述橋接晶粒上形成至少一個電互連件；在所述RDL和所述橋接晶粒上面形成第一模層；和將多個晶粒耦接到所述RDL並耦接到所述橋接晶粒，使得晶粒電連接到所述RDL的至少一個電互連件並電連接到所述橋接晶粒的至少一個電互連件；或在所述第一模層上和在所述多個晶粒上形成第二模層；或在所述第一模層上形成至少一個集成無源元件；和在所述第一模層上、在所述多個晶粒上和在所述至少一個集成無源元件上形成第二模層；或使用銅基材料在所述RDL上形成至少一個電互連件或在所述橋接晶圓上形成至少一個電互連件；或在所述RDL上形成至少一個電互連件；在所述橋接晶粒上形成至少一個電互連件；在所述RDL上形成至少一個穿模通孔（TMV）的至少一個第一部分；在所述RDL和所述橋接晶粒上面形成第一模層；形成所述至少一個TMV的至少一個第二部分；將多個晶粒耦接到所述RDL並耦接到所述橋接晶粒，使得晶粒電連接到所述RDL的至少一個電互連件並電連接到所述橋接晶粒的至少一個電互連件；和在所述第一模層上和在所述多個晶粒上形成第二模層，所述至少一個TMV在所述第二模層的頂表面處具有電連接以用於支援封裝層疊（PoP）電連接；或使用電鍍製程形成所述至少一個TMV。
一種形成晶圓級橋接晶粒的方法的一些實施方式包括：暫時地將重分佈層（RDL）結合在載體上；將橋接晶粒附貼在所述RDL上，所述橋接晶粒在與所述RDL相對的暴露表面上具有電連接；在所述RDL上形成至少一個電互連件；在所述橋接晶粒的所述暴露表面上形成至少一個電互連件；在所述RDL和所述橋接晶粒上形成第一模層；將多個晶粒耦接到所述RDL並耦接到所述橋接晶粒，使得晶粒電連接到所述RDL的至少一個電互連件並電連接到所述橋接晶粒的至少一個電互連件；在所述第一模層上和在所述多個晶粒上形成第二模層；和從所述RDL上去除所述載體。
一種形成晶圓級橋接晶粒的方法的一些實施方式還包括：將熱交換層附貼到所述多個晶粒中的至少一個的頂表面；或將所述RDL電連接到基板或印刷電路板；或在形成所述第二模層之前在所述第一模層上形成至少一個集成無源元件；或形成從所述RDL到所述第二模層的頂表面的至少一個穿模通孔。
一種用於連接半導體元件的設備的一些實施方式包括：重分佈層（RDL）；橋接晶粒；和插置在所述RDL與所述橋接晶粒之間的黏合劑層。
一種用於連接半導體元件的設備的一些實施方式還包括：在所述RDL上的至少一個電互連件；在所述橋接晶粒上的至少一個電互連件；和在所述RDL和所述橋接晶粒上的第一模層；或多個晶粒，耦接到所述RDL並耦接到所述橋接晶粒，使得晶粒電連接到所述RDL的所述至少一個電互連件中的至少一個並電連接到所述橋接晶粒的所述至少一個電互連件中的至少一個；和在所述第一模層上和在所述多個晶粒上的第二模層；或多個晶粒，耦接到所述RDL並耦接到所述橋接晶粒，使得晶粒電連接到所述RDL的所述至少一個電互連件中的至少一個並電連接到所述橋接晶粒的所述至少一個電互連件中的至少一個；在所述第一模層上的至少一個集成無源元件；和在所述第一模層上、在所述多個晶粒上和在所述至少一個集成無源元件上的第二模層；或在所述RDL上的至少一個電互連件；在所述RDL上的至少一個集成無源元件；在所述橋接晶粒上的至少一個電互連件；在所述RDL上的至少一個穿模通孔（TMV）的至少一個第一部分；和在所述RDL和所述橋接晶粒上的第一模層；或所述至少一個TMV的至少一個第二部分；多個晶粒，耦接到所述RDL並耦接到所述橋接晶粒，使得晶粒電連接到所述RDL的所述至少一個電互連件中的至少一個並電連接到所述橋接晶粒的所述至少一個電互連件中的至少一個；和在所述第一模層上和在所述多個晶粒上的第二模層，所述至少一個TMV在所述第二模層的頂表面處具有電連接以用於支援封裝層疊（PoP）電連接。
晶圓級晶粒橋接附貼到重分佈層（RDL）。RDL可以預製造並暫時地接合到載體或用暫時黏合的黏合劑直接地形成在載體上。一般，RDL具有低生產量（高故障率）。細間距RDL結構甚至更難製造。通過首先預製造RDL並將RDL附接到載體或首先在載體上形成RDL，可以丟棄任何有缺陷的RDL而不丟棄其它有價值的部件，從而降低總生產成本。此外，由於首先構造RDL，因此其它半導體元件（諸如晶粒）的熱預算不會限制RDL形成製程。另一個優點是可以實現RDL的延長的高溫固化，而不會有損壞其它昂貴部件的風險。
橋接晶粒通過遵循線後端（BEOL）製程流程（例如，雙鑲嵌製程）或標準RDL製程流程（半添加製程）單獨地製造，這可以實現小於1/1線/間隔（典型，0.8/0.8L/S或0.4/0.4μm）設計。細間距電路能夠滿足晶圓對晶圓的互連需要。另外，由於晶粒橋接是在晶圓級處生產的，並且不需要鑄造工作，因此該製程還與外包裝配和測試（OSAT）設施高度相容。如果RDL是在晶圓放置之後構建的，那麼大多數的（即使不是全部）OSAT設施很可能不具有正確地形成RDL的精度對準能力，從而限制鑄造廠的生產並增加製造成本。
由於首先形成RDL，因此細線間隔可以是2/2或更小。RDL形成在載體上，該載體可具有非常光滑的表面。當在其它模層和晶粒上形成RDL時，在晶粒/磨具交點處形成階梯高度。階梯高度產生不適合形成細間距RDL的形貌，大大降低更細間距RDL產量，並且隨後，當RDL製程失敗時，因製造時間的損失和晶圓成本的損失而增加成本。RDL第一晶圓級晶粒橋接製程具有更好地控制RDL製程（沒有晶粒熱預算問題）、提高RDL品質（因平坦形貌而引起的細間距控制）和提高RDL產量而沒有損失昂貴晶粒的風險的優點。晶圓級晶粒橋接製程成本也低於使用插置器的橋接方案。由於沒有插置器，也可以減小大小，因此晶粒替代插入物成為尺寸的限制因素。尺寸減小允許晶圓級橋接晶粒與更大的封裝相容（2X掩模版大小的突破）。
圖1示出了根據本原理的一些實施方式的用於形成RDL第一晶圓級橋接晶粒的方法100。方法100涉及圖3A至3G中所示的設備，這將被相應地參考。在框102中，如圖3A所示的結構300A包括RDL 306，其中至少一個電互連件314形成在RDL 306上，RDL 306用接合層304或RDL 306暫時地接合到載體302，並且至少一個電連接件314形成在載體302上的接合層304上。載體302可以由諸如玻璃、GaN、矽或聚丙烯（預浸漬）基板等的材料製成。在框104中，如圖3B所示的結構300B包括用黏合劑308附貼在RDL 306上的橋接晶粒310。黏合劑308有助於在進一步的處理期間定位和保持橋接晶粒，從而允許方法100被執行。黏合劑308可以是通常用於引線接合技術中的有機或無機物質或化合物。在框106中，結構300B還包括形成在橋接晶圓310與RDL 306相對的暴露表面330上的至少一個電互連件312。電互連件312、314允許在形成後續層（下面討論）之後與RDL 306和橋接晶粒310進行連接。電互連件312、314有時被稱為柱，並且可以由導電材料形成，導電材料諸如例如包括銅基材料、鎢基材料和銀基材料的金屬和/或例如導電聚合物基材料等。典型地使用電鍍製程來形成電互連件312、314。任選的集成無源元件（IPD）322也可以放置在RDL 306的頂表面394上。包括IPD是方法100相對於其它技術的另一個優點。
在框108中，如圖3C所示的結構300C包括形成在RDL 306和橋接晶粒310上的第一模層316。第一模層316可以由諸如例如聚醯亞胺、苯并環丁烯、聚苯并惡唑、環氧模塑膠（EMC）（有或沒有填料）等的材料形成。在形成第一模層316之後可以採用平坦化製程諸如化學機械拋光（CMP）以平坦化第一模層316的頂表面360來進一步暴露電互連件312、314。在框110中，如圖3D所示的結構300D包括放置在第一模層316上並經由電互連件312、314耦合到RDL 306和橋接晶粒310的多個晶粒318、320。另一個任選的集成無源元件（IPD）322也可以放置在第一模層316的頂表面360上。
在框112中，如圖3E所示的結構300E包括形成在第一模層316上和多個晶粒318、320上（以及任選的IPD上）的第二模層324。第二模層324可以由諸如例如聚醯亞胺、苯并環丁烯、聚苯并惡唑、環氧模塑膠（EMC）（有或沒有填料）等的材料形成。在形成第二模層324之後可以採用平坦化製程諸如CMP以平坦化第二模層324的頂表面370來進一步暴露多個晶粒318、320的頂表面380。平坦化可以允許多個晶粒的頂表面380與熱交換層等之間的更好的接觸（下面討論）。在框114中，如圖3F所示的結構300F具有載體302，載體302從RDL 306上去除（去接合）。例如球焊可以用於形成任選的球326以將RDL 306的下表面390連接到其它電路。如圖3G所示的結構300G包括任選的基板或印刷電路板354和與多個晶粒318、320的頂表面380接觸以在多個晶粒318、320的操作期間移除熱的任選的熱交換層350。基板或印刷電路板354可以包含經由形成在RDL 306的下表面390上的任選的球326連接的另外的電路。
圖2是根據本原理的一些實施方式的用於形成RDL第一晶圓級橋接晶粒的另一種方法200。方法200涉及圖4A至4F中所示的設備，這將被相應地參考。在適當時使用相似的元件符號來簡化說明。在框202中，如圖4A所示的結構400A包括RDL 306，RDL 306用接合層304暫時地接合到載體302，或RDL 306形成在載體302上的接合層304上。載體302可以由諸如玻璃、GaN、矽或聚丙烯（預浸漬）基板等的材料製成。在框204中，結構400A還包括用黏合劑308附貼在RDL 306上的橋接晶粒310。黏合劑308有助於在進一步的處理期間定位和保持橋接晶粒，從而允許方法200被執行。黏合劑308可以是通常用於引線接合技術中的有機或無機物質。
在框206中，結構400A還包括形成在橋接晶圓310與RDL 306相對的暴露表面330上的至少一個電互連件312。電互連件312、314允許在形成後續層（下面討論）之後與RDL 306和橋接晶粒310進行連接。電互連件312、314有時被稱為柱，並且可以由導電材料形成，導電材料諸如例如包括銅基材料、鎢基材料和銀基材料的金屬和/或例如導電聚合物基材料等。典型地使用電鍍製程來形成電互連件312、314。在框208中，結構400A還包括延伸穿過RDL 306的至少一個穿模通孔（TMV）（圖4C-4E中的406）的至少一個第一部分402。至少一個TMV 406的至少一個第一部分402可以由類似材料（金屬、導電聚合物等）並用與電互連件312、314類似的製程（包括電鍍製程等）形成。雖然未示出，但是至少一個TMV 406可以電連接到RDL 306。包括TMV是方法200相對於其它技術的另一個優點。
在框210中，如圖4B所示的結構400B包括形成在RDL 306和橋接晶粒310上的第一模層316。在形成第一模層316之後可以採用平坦化製程諸如CMP以平坦化第一模層316的頂表面360來進一步暴露電互連件312、314和至少一個TMV 406的至少一個第一部分402。在框212中，如圖4C所示的結構400C包括至少一個TMV 406的至少一個第二部分404。至少一個TMV 406的至少一個第二部分404可以例如使用電鍍製程等形成，以在至少一個TMV 406的至少一個第一部分402上形成至少一個第二部分404。
在框214中，如圖4D所示的結構400D包括放置在第一模層316上並經由電互連件312、314耦合到RDL 306和橋接晶粒310的多個晶粒318、320。任選的集成無源元件（IPD）322（未示出）也可以與具有頂表面420的至少一個TMV 406一起放置在第一模層316的頂表面360上。在框216中，結構400D還包括形成在第一模層316上和多個晶粒318、320上（以及任選的IPD上）的第二模層324。在形成第二模層324之後可以採用平坦化製程諸如CMP以平坦化第二模層324的頂表面370來進一步暴露多個晶粒318、320的頂表面380。平坦化可以允許多個晶粒的頂表面380與熱交換層等之間的更好的接觸（上面討論）。
在框218中，如圖4E所示的結構400E具有載體302，載體302從RDL 306上去除（去接合）。例如球焊可以用於形成任選的球326以將RDL 306的下表面390連接到其它電路。如圖4F所示的結構400F包括任選的半導體封裝408，任選的半導體封裝408經由由至少一個TMV 406的頂表面420的球焊形成的任選的球410連接到至少一個TMV 406。至少一個TMV 406有利地允許支持封裝層疊（PoP）電連接。
上述方法具有的優點是更高的晶粒和橋接晶粒放置精度以及RDL相對於基於襯底的製程的更嚴格的公差。該方法還具有與高溫介電質相容的優點，因為首先構造RDL（不受晶粒熱預算限制）。該方法還具有的優點是使得OSAT能夠在沒有鑄造廠協助的情況下在內部形成製程。
雖然前述內容針對的是本原理的實施方式，但是也可在不脫離本原理的基本範圍的情況下設計本原理的其它和進一步實施方式。
100‧‧‧方法 102‧‧‧框 104‧‧‧框 106‧‧‧框 108‧‧‧框 110‧‧‧框 112‧‧‧框 114‧‧‧框 200‧‧‧方法 202‧‧‧框 204‧‧‧框 206‧‧‧框 208‧‧‧框 210‧‧‧框 212‧‧‧框 214‧‧‧框 218‧‧‧框 300A-G‧‧‧結構 302‧‧‧載體 304‧‧‧接合層 306‧‧‧RDL 308‧‧‧黏合劑 310‧‧‧橋接晶粒 312‧‧‧電互連件 314‧‧‧電互連件 316‧‧‧第一模層 318‧‧‧多個晶粒 320‧‧‧多個晶粒 322‧‧‧集成無源元件 324‧‧‧第二模層 326‧‧‧任選的球 330‧‧‧暴露的表面 350‧‧‧任選的熱交換層 354‧‧‧印刷電路板 360‧‧‧頂表面 370‧‧‧頂表面 380‧‧‧暴露的頂表面 390‧‧‧下表面 394‧‧‧頂表面 400A-F‧‧‧結構 402‧‧‧第一部分 404‧‧‧一個第二部分 406‧‧‧TMV 408‧‧‧任選的半導體封裝 410‧‧‧任選的球
可以參考附圖中描繪的本原理的說明性實施方式來理解在以上簡要地概述且以下更詳細討論的本原理的實施方式。然而，附圖僅示出了本原理的典型實施方式，並且因此不應視為限制範圍，因為本原理可允許其它同等有效實施方式。
圖1是根據本原理的一些實施方式的形成晶圓級橋接晶粒的方法。
圖2是根據本原理的一些實施方式的形成晶圓級橋接晶粒的另一種方法。
圖3A至3G描繪了根據本原理的一些實施方式的從圖1的方法形成的設備。
圖4A至4F描繪了根據本原理的一些實施方式的從圖2的方法形成的設備。
為了促進理解，已經儘可能地使用相同的附圖標記標示各圖共有的相同要素。各圖未按比例繪製，並且為了清楚起見，可以進行簡化。一些實施方式的要素和特徵可有益地結合在其它實施方式中，而不贅述。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
306‧‧‧RDL
308‧‧‧黏合劑
310‧‧‧橋接晶粒
312‧‧‧電互連件
314‧‧‧電互連件
316‧‧‧第一模層
318‧‧‧多個晶粒
320‧‧‧多個晶粒
324‧‧‧第二模層
326‧‧‧任選的球
400F‧‧‧結構
406‧‧‧TMV
408‧‧‧任選的半導體封裝
410‧‧‧任選的球

Claims (16)

  1. 一種形成一晶圓級橋接晶粒的方法，包括以下步驟：形成一重分佈層(RDL)；將一橋接晶粒附貼在該RDL上，該橋接晶粒在與該RDL相對的一暴露表面上具有電連接；在該RDL上形成至少一個電互連件；在該橋接晶粒上形成至少一個電互連件；在該RDL上形成至少一個穿模通孔(TMV)的至少一個第一部分；在該RDL和該橋接晶粒上面形成一第一模層；形成該至少一個TMV的至少一個第二部分；將多個晶粒耦接到該RDL並耦接到該橋接晶粒，使得一晶粒電連接到該RDL的至少一個電互連件並電連接到該橋接晶粒的至少一個電互連件；和在該第一模層上和在該多個晶粒上形成一第二模層，該至少一個TMV在該第二模層的一頂表面處具有一電連接以用於支援封裝層疊(PoP)電連接。
  2. 如請求項1所述的方法，還包括以下步驟：在一載體上形成該RDL。
  3. 如請求項1所述的方法，還包括以下步驟：使用該橋接晶粒與該RDL之間的一黏合劑將該橋 接晶粒附貼在該RDL上。
  4. 如請求項1所述的方法，還包括以下步驟：在該第一模層上形成至少一個集成無源元件；和在該第一模層上、在該多個晶粒上和在該至少一個集成無源元件上形成該第二模層。
  5. 如請求項1所述的方法，還包括以下步驟：使用一銅基材料在該RDL上形成至少一個電互連件或在該橋接晶粒上形成至少一個電互連件。
  6. 如請求項1所述的方法，還包括以下步驟：使用一電鍍製程形成該至少一個TMV。
  7. 一種形成一晶圓級橋接晶粒的方法，包括以下步驟：暫時地將一重分佈層(RDL)接合在一載體上；將一橋接晶粒附貼在該RDL上，該橋接晶粒在與該RDL相對的一暴露表面上具有電連接；在該RDL上形成至少一個電互連件；在該橋接晶粒的該暴露表面上形成至少一個電互連件；在該RDL和該橋接晶粒上形成一第一模層；將多個晶粒耦接到該RDL並耦接到該橋接晶粒，使得一晶粒電連接到該RDL的至少一個電互連件並電連接到該橋接晶粒的至少一個電互連件； 在該第一模層上和在該多個晶粒上形成一第二模層；從該RDL去除該載體；和形成從該RDL到該第二模層的一頂表面的至少一個穿模通孔。
  8. 如請求項7所述的方法，還包括以下步驟：將一熱交換層附貼到該多個晶粒中的至少一個的一頂表面。
  9. 如請求項7所述的方法，還包括以下步驟：將該RDL電連接到一基板或印刷電路板。
  10. 如請求項7所述的方法，還包括以下步驟：在形成該第二模層之前在該第一模層上形成至少一個集成無源元件。
  11. 一種由如請求項1至10中任一項所述之方法所製造之用於連接半導體元件的設備，包括：一重分佈層(RDL)；一橋接晶粒；一黏合劑層，插置在該RDL與該橋接晶粒之間。
  12. 如請求項11所述的設備，還包括：在該RDL上的至少一個電互連件；在該橋接晶粒上的至少一個電互連件；和 在該RDL和該橋接晶粒上的一第一模層。
  13. 如請求項12所述的設備，還包括：多個晶粒，耦接到該RDL並耦接到該橋接晶粒，使得一晶粒電連接到該RDL的該至少一個電互連件中的至少一個並電連接到該橋接晶粒的該至少一個電互連件中的至少一個；和在該第一模層上和在該多個晶粒上的一第二模層。
  14. 如請求項12所述的設備，還包括：多個晶粒，耦接到該RDL並耦接到該橋接晶粒，使得一晶粒電連接到該RDL的該至少一個電互連件中的至少一個並電連接到該橋接晶粒的該至少一個電互連件中的至少一個；在該第一模層上的至少一個集成無源元件；和在該第一模層上、在該多個晶粒上和在該至少一個集成無源元件上的一第二模層。
  15. 如請求項11所述的設備，還包括：在該RDL上的至少一個電互連件；在該RDL上的至少一個集成無源元件；在該橋接晶粒上的至少一個電互連件；在該RDL上的至少一個穿模通孔(TMV)的至少一個第一部分；和在該RDL和該橋接晶粒上的一第一模層。
  16. 如請求項15所述的設備，還包括：該至少一個TMV的至少一個第二部分；多個晶粒，耦接到該RDL並耦接到該橋接晶粒，使得一晶粒電連接到該RDL的該至少一個電互連件中的至少一個並電連接到該橋接晶粒的該至少一個電互連件中的至少一個；和在該第一模層上和在該多個晶粒上的一第二模層，該至少一個TMV在該第二模層的一頂表面處具有一電連接以用於支援封裝層疊(PoP)電連接。
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