TWI585906B - 超薄封裝上封裝ＰｏＰ之封裝 - Google Patents

超薄封裝上封裝ＰｏＰ之封裝 Download PDF

Info

Publication number
TWI585906B
TWI585906B TW103103658A TW103103658A TWI585906B TW I585906 B TWI585906 B TW I585906B TW 103103658 A TW103103658 A TW 103103658A TW 103103658 A TW103103658 A TW 103103658A TW I585906 B TWI585906 B TW I585906B
Authority
TW
Taiwan
Prior art keywords
interposer
die
package
terminals
coupled
Prior art date
Application number
TW103103658A
Other languages
English (en)
Other versions
TW201438159A (zh
Inventor
翟軍
Original Assignee
蘋果公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 蘋果公司 filed Critical 蘋果公司
Publication of TW201438159A publication Critical patent/TW201438159A/zh
Application granted granted Critical
Publication of TWI585906B publication Critical patent/TWI585906B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24101—Connecting bonding areas at the same height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/244—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

超薄封裝上封裝PoP之封裝
本發明係關於半導體封裝及用於封裝半導體裝置之方法。更特定言之，本發明係關於PoP(封裝上封裝)的底部封裝。
封裝上封裝(「PoP」)技術已隨著在半導體工業中持續需求較低成本、較高效能、增加的積體電路密度及增加的封裝密度而變得愈來愈流行。隨著對愈來愈小封裝的急切要求增加，晶粒及封裝的整合(例如，「預堆疊」或系統單晶片(「SoC」)技術與記憶體技術之整合)允許較薄的封裝。此預堆疊已變為薄且細間距PoP封裝的關鍵組件。
減小封裝(例如，PoP封裝中的頂部封裝(記憶體封裝)或底部封裝(SoC封裝))之大小的一個限制為用於封裝中的基板之大小。已使用薄基板及/或空心基板(例如，層合基板)來將封裝之大小減小至某些程度。然而，可需要大小的進一步減小以便為下一代裝置提供甚至更小的封裝。
在減小封裝之大小時出現的潛在問題為隨著封裝變得愈來愈薄，愈來愈可能在封裝中發生扭曲。扭曲問題可導致PoP封裝之故障或降低的效能及/或在利用PoP封裝之裝置的可靠性方面的問題。舉例而言，PoP封裝中之頂部封裝與底部封裝之間的扭曲特性之差異可造成耦接封裝之焊接點的良率損失。由於對頂部封裝及底部封裝之嚴格扭曲規範，可能扔掉PoP結構之一大部分(不合格)。不合格之PoP結構 促成了低的預堆疊良率、浪費的材料及增加的製造成本。
儘管已採用及預期許多進步及/或設計修改來抑制使用薄或空心基板的封裝中之扭曲。但減少甚至比具有薄或空心基板之封裝更小的封裝中之扭曲可需要進一步進步或設計修改。
在某些實施例中，PoP封裝包括底部封裝及頂部封裝。底部封裝可包括耦接於中介層與重新分佈層(RDL)之間的晶粒。晶粒可至少部分地圍封於在中介層與重新分佈層之間的囊封物中。晶粒可藉由黏著層耦接至中介層。在晶粒之周邊上的一或多個端子可將中介層耦接至重新分佈層。端子可至少部分地圍封於囊封物中。
一或多個端子可將中介層的頂部耦接至頂部封裝之底部。頂部封裝可為記憶體封裝(例如，包括一或多個記憶體晶粒)。耦接中介層與頂部封裝之端子可分佈於中介層之表面上的任何處(例如，端子不限於在底部封裝中之晶粒的周邊上)。底部封裝中之中介層及RDL幫助抑制底部封裝中之扭曲且減小PoP封裝的總厚度。
100‧‧‧PoP封裝
102‧‧‧中介層
104‧‧‧端子
106‧‧‧作用層
108‧‧‧晶粒
110‧‧‧黏著層
112‧‧‧囊封物
114‧‧‧重新分佈層(RDL)
116‧‧‧端子
120‧‧‧底部封裝
130‧‧‧頂部封裝
132‧‧‧端子
140‧‧‧垂直連接器
藉由參考結合隨附圖式進行的對根據本發明之當前較佳(但仍為說明性的)實施例之以下詳細描述，將更完整瞭解本發明之方法及設備的特徵及優點，其中：圖1A至圖1E描繪用於形成PoP封裝之製程流程的實施例之橫截面表示。
雖然本發明易受各種修改及替代形式之影響，但在圖式中以舉例方式展示了其特定實施例，且將在本文中對其進行詳細描述。該等圖式可不按比例繪製。應理解，該等圖式及對其之詳細描述並非意欲將本發明限於所揭示的特定形式，而正相反，本發明將涵蓋屬於附加申請專利範圍所界定的本發明之精神及範疇內的所有修改、等效物及 替代物。
圖1A至圖1E描繪用於形成PoP封裝之製程流程的實施例之橫截面表示。圖1A描繪中介層102之實施例的橫截面表示，其中端子104耦接至中介層之底部表面(側)。在某些實施例中，將中介層/端子組合提供至製程流程，其中端子104已經附接(例如，預附接)至中介層102。舉例而言，端子104可為鋁球或另一合適導電材料之球。在一些實施例中，端子104塗佈有焊料或塗佈有Sn。
在某些實施例中，中介層102包括兩個作用層106(例如，兩個作用金屬層)以使得中介層為2層中介層。在一些實施例中，中介層102包括兩個以上作用層106。中介層102中之多個作用層106可經設計以提供穿過中介層之非垂直佈線(例如，中介層之作用層經設計成好像其在多層PCB(印刷電路板)中)。因此，中介層102可經設計以耦接端子，該等端子並非彼此的鏡像(例如，端子並不在中介層的對置側上直接彼此對置)。
在某些實施例中，中介層102包括層合物材料。舉例而言，中介層102可包括BT(雙馬來醯亞胺/三嗪)層合物或任何其他合適的預浸體(預浸漬)層合物材料。作用層106可包括導電金屬層，諸如銅、鋁或金。中介層102可使用用於形成層合物材料之此項技術領域中已知的技術來形成。
在某些實施例中，中介層102包括兩個或多個作用層106(例如，導電層)。作用層106可為藉由一或多個垂直連接器140而互連之在中介層102中的非垂直層。在某些實施例中，中介層102包括在絕緣材料中(例如，層合物材料)的兩個或多個作用層106。作用層106可為藉由一或多個垂直連接器140而互連之在中介層102中經水平置換的非垂直層。
在形成/提供附接有端子104之中介層102之後，晶粒可耦接至中介層。圖1B描繪耦接至晶粒108之中介層102的實施例之橫截面表示。在某些實施例中，晶粒108為處理器或邏輯晶粒，或晶粒108為系統單晶片(「SoC」)。舉例而言，晶粒108可為半導體晶片晶粒，諸如覆晶晶粒。
晶粒108可使用用於晶粒/層合物界面之已知結合技術而耦接(例 如，附接)至中介層102。在某些實施例中，晶粒藉由黏著層110耦接至中介層102。舉例而言，黏著層110可為可固化環氧樹脂或另一合適的晶粒附接膜。
在晶粒108耦接至中介層102之後，晶粒及端子104至少部分地囊封於耦接至中介層之囊封物中。圖1C描繪囊封於囊封物112中之晶粒110及端子104的實施例之橫截面表示。舉例而言，囊封物112可為聚合物或模製化合物。在一些實施例中，中介層102、端子104及晶粒108被置於重新建構(reconstruction)上，且囊封物(模製物)形成於端子及晶粒之上且囊封端子及晶粒。端子104及晶粒108之底部表面的至少某一部分可被囊封物112曝露以允許端子及晶粒耦接(例如，結合)至PoP封裝中的稍後形成之層。
在囊封晶粒108及端子104之後，重新分佈層(RDL)可經形成且耦接至晶粒及/或端子以形成底部封裝。圖1D描繪耦接至晶粒108及端子104以形成底部封裝120之重新分佈層(RDL)114的實施例之橫截面表示。RDL 114亦可耦接至囊封物112。RDL 114可包括若干材料，諸如(但不限於)PI(聚醯亞胺)、PBO(聚苯并噁唑)、BCB(苯并環丁烯)及WPR(晶圓光阻劑，諸如以商品名WPR市售的清漆型酚醛樹脂及聚(羥基苯乙烯)(PHS)，WPR包括WPR-1020、WPR-1050及WPR-1201(WPR為日本東京JSR公司的註冊商標))。可使用此項技術中已知的技術(例如，用於聚合物沈積之技術)將RDL 114形成於晶粒108、端子104及囊封物112上。在某些實施例中，RDL 114包括用於耦接至端子104之一或多個定位襯墊。舉例而言，RDL 114可包括用於耦接至端子104之鋁定位襯墊或塗佈有焊料或塗佈有Sn之鋁定位襯墊。
在形成RDL 114之後，端子116可耦接至RDL，如圖1D中所示。端子116可用以將底部封裝120耦接至主機板或印刷電路板(PCB)。端子116可包括鋁或另一合適導電材料。在一些實施例中，端子116塗佈 有焊料或塗佈有Sn。
在某些實施例中，RDL 114包括晶粒108與端子116中之一或多者之間的佈線(例如，導線或連接)及/或端子104與端子116中之一或多者之間的佈線。因此，RDL 114允許經由端子116結合及電耦接至用於晶粒108及/或端子104的在遠離該晶粒及該等端子之位置處的主機板或PCB。
相比於通常用於SOC封裝(例如，在PoP封裝中之底部封裝)之基板，RDL 114可為相對較薄的層。舉例而言，RDL 114可具有小於約50μm(例如，約25μm)之厚度，而典型薄基板具有約300μm至400μm之厚度，且空心基板具有在約200μm之範圍中的厚度。因此，在底部封裝120中使用RDL 114會減小底部封裝及含有底部封裝之PoP封裝的總厚度。舉例而言，底部封裝120可具有約350μm或350μm以下的厚度。
另外，在底部封裝120之頂部上使用中介層102及在底部封裝之底部上使用RDL 114可減小底部封裝中之扭曲問題。舉例而言，中介層102及RDL 114可具有類似熱性質(例如，熱膨脹係數(「CTE」)及/或收縮率)以使得中介層及RDL以相對類似的速率膨脹/收縮，從而抑制底部封裝120中之扭曲。在一些實施例中，可由於中介層102及RDL 114之使用而使底部封裝120變扁平(例如，使用壓縮力)。使底部封裝120變扁平可減小或消除底部封裝中之扭曲。減小底部封裝120中之扭曲問題可產生PoP封裝之較高良率(例如，減小歸因於扭曲問題而不合格的封裝之數目)，藉此增加可靠性且降低製造成本。
在某些實施例中，頂部封裝130耦接至底部封裝120以形成PoP封裝100，如圖1E中所示。頂部封裝130可使用一或多個端子132耦接至底部封裝120。端子132可與中介層102中之開口(例如，中介層中之通往作用層106的開口)耦接。中介層102可預形成有用於將端子132耦接 至作用層106的開口(例如，如圖1A中所示，中介層102可已經具有開口)。舉例而言，端子132可為焊球、銅柱或用於在頂部封裝130與中介層102之間進行接觸的其他合適端子。
典型PoP封裝中之頂部封裝具有圍繞頂部封裝之周邊定位的端子(例如，端子之導線自晶粒扇出)。端子扇出以使得可在底部封裝中之晶粒的周邊上形成連接，此係因為底部封裝中之晶粒通常曝露於底部封裝中之囊封物之上。因為頂部封裝130中之端子132耦接至中介層102且中介層實質上覆蓋底部封裝120之頂部表面並覆蓋晶粒108，所以端子132不限於僅位於該周邊上(例如，端子可位於中介層之表面上任何處)。因此，PoP封裝100可使用比典型PoP封裝更高的數目個端子132將頂部封裝130耦接至底部封裝120。使用更多的端子132及端子之位置可用性的增大允許頂部封裝130之設計更為靈活，及因此PoP封裝100中之較佳完整性。舉例而言，頂部封裝130可具有不同於典型PoP封裝之大小的記憶體晶粒，及/或頂部封裝可具有扇入導線結合型樣而非扇出導線結合型樣。
頂部封裝130可包括基板及圍封於囊封物中之一或多個晶粒。頂部封裝130中之晶粒可使用(例如)一或多個導線結合而耦接(例如，連接)至基板。舉例而言，頂部封裝130中之晶粒可為半導體晶片，諸如導線結合晶粒或覆晶晶粒。在某些實施例中，頂部封裝130中之晶粒為記憶體晶粒(例如，DRAM晶粒)。
在某些實施例中，頂部封裝130包括具有最小層數之記憶體晶粒。舉例而言，頂部封裝130可包括具有兩層(2L)層數的記憶體晶粒。在頂部封裝130中具有最小層數可最小化PoP封裝100之總厚度。在某些實施例中，頂部封裝130具有約450μm之厚度。因此，若底部封裝120具有約350μm之厚度，則PoP封裝可具有約800μm之總厚度。可藉由(例如)使頂部封裝130抑或底部封裝120變扁平而進一步減 小PoP封裝之厚度。
在某些實施例中，協同設計頂部封裝130及中介層102(例如，各自的佈局/佈線係結合彼此而設計的)。協同設計頂部封裝130及中介層102可改良及/或最大化頂部封裝與中介層之間的信號完整性，因此改良PoP封裝100之效能。
鑒於本描述，對於熟習此項技術者而言，本發明之各種態樣的進一步修改及替代性實施例將為顯而易見的。因此，本描述應被理解為僅為說明性的，且係為了向熟習此項技術者教示執行本發明的一般方式之目的。應理解，本文中展示且描述的本發明之形式應被視為目前較佳實施例。元件及材料可替代本文中說明及描述之元件及材料，各部分且製程可反轉，且可獨立利用本發明之某些特徵，以上所有部分對得益於本發明之此描述的熟習此項技術者將為顯而易見的。在不脫離如在以下申請專利範圍中所述的本發明之精神及範疇的情況下，可對本文中描述之元件作出改變。
100‧‧‧PoP封裝
102‧‧‧中介層
104‧‧‧端子
106‧‧‧作用層
108‧‧‧晶粒
110‧‧‧黏著層
112‧‧‧囊封物
114‧‧‧重新分佈層(RDL)
116‧‧‧端子
120‧‧‧底部封裝
130‧‧‧頂部封裝
132‧‧‧端子
140‧‧‧垂直連接器

Claims (14)

  1. 一種半導體裝置封裝，其包含：一重新分佈層；一囊封物，其在該重新分佈層之上；一中介層，其在該囊封物之上，該中介層包含複數個導電層，其中該等導電層包含藉由至少一導電垂直連接器而互連之在該中介層中之多個非垂直層；一晶粒，其至少部分地圍封於該囊封物中，其中該晶粒耦接至且直接接觸該重新分佈層之一上表面及該晶粒耦接至該中介層之一下表面；及一或多個端子，其將該中介層之至少部分耦接至該重新分佈層之至少部分，其中該等端子位於該囊封物中在該晶粒之一周邊上。
  2. 如請求項1之封裝，其中該晶粒藉由一黏著層耦接至該中介層之該下表面。
  3. 如請求項1之封裝，其進一步包含一記憶體封裝，該記憶體封裝經由位於該中介層之與該晶粒對置的一側上之一或多個額外端子耦接至該中介層。
  4. 如請求項3之封裝，其中該等額外端子既定位於該晶粒之該周邊上，又定位於該晶粒之上。
  5. 如請求項3之封裝，其中該中介層包含佈線，該佈線對應於將該中介層之至少部分耦接至該重新分佈層的至少部分之該一或多個端子及位於該中介層之與該晶粒對置的一側上之該一或多個額外端子之位置。
  6. 一種用於形成一半導體裝置封裝之方法，其包含： 將一或多個第一端子耦接至一中介層之一第一側；將一晶粒耦接至該中介層之該第一側，其中該等第一端子位於該晶粒之一周邊上；在將該等第一端子耦接至該中介層且將該晶粒耦接至該中介層之後，將該晶粒及該等第一端子至少部分地囊封於一囊封物中；及將一重新分佈層耦接至且直接接觸該晶粒及該等第一端子。
  7. 如請求項6之方法，其進一步包含藉由一黏著層將該晶粒耦接至該中介層。
  8. 如請求項6之方法，其進一步包含使用位於該中介層之與該第一側對置的一第二側上之一或多個額外端子將一記憶體封裝耦接至該中介層。
  9. 如請求項6之方法，其進一步包含將一或多個額外端子耦接至該重新分佈層之一下表面，及將該等額外端子耦接至一主機板或一印刷電路板。
  10. 一種半導體裝置封裝，其包含：一模製材料，其經定位於一中介層與一重新分佈層之間，其中該中介層包含在一絕緣材料中的複數個導電層，及其中該等導電層包含藉由至少一導電垂直連接器而互連之在該中介層中之水平位移的多個非垂直層；一晶粒，其至少部分地圍封於該模製材料中，其中該晶粒耦接至該中介層及該晶粒耦接至且直接接觸該重新分佈層；及一或多個端子，其將該中介層耦接至該重新分佈層，其中該等端子位於該模製材料中在該晶粒之一周邊上。
  11. 如請求項10之封裝，其中該晶粒藉由一黏著層耦接至該中介層。
  12. 如請求項10之封裝，其進一步包含位於該中介層之與該晶粒對置的一側上之一或多個額外端子，其中該等額外端子經組態以將該封裝耦接至一記憶體封裝。
  13. 如請求項10之封裝，其中該重新分佈層包含將該晶粒耦接至在該晶粒之該周邊上的一或多個額外端子之電佈線。
  14. 如請求項10之封裝，其中該中介層包含一兩層式中介層。
TW103103658A 2013-01-29 2014-01-29 超薄封裝上封裝ＰｏＰ之封裝 TWI585906B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/753,014 US20140210106A1 (en) 2013-01-29 2013-01-29 ULTRA THIN PoP PACKAGE

Publications (2)

Publication Number Publication Date
TW201438159A TW201438159A (zh) 2014-10-01
TWI585906B true TWI585906B (zh) 2017-06-01

Family

ID=50070699

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103103658A TWI585906B (zh) 2013-01-29 2014-01-29 超薄封裝上封裝ＰｏＰ之封裝

Country Status (6)

Country Link
US (1) US20140210106A1 (zh)
JP (1) JP2016504774A (zh)
KR (1) KR20150109477A (zh)
CN (1) CN104969347A (zh)
TW (1) TWI585906B (zh)
WO (1) WO2014120483A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10770433B1 (en) 2019-02-27 2020-09-08 Apple Inc. High bandwidth die to die interconnect with package area reduction

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9006030B1 (en) * 2013-12-09 2015-04-14 Xilinx, Inc. Warpage management for fan-out mold packaged integrated circuit
KR102367404B1 (ko) 2015-08-03 2022-02-25 삼성전자주식회사 반도체 패키지의 제조 방법
TWI566356B (zh) 2015-10-15 2017-01-11 力成科技股份有限公司 封裝結構及其製造方法
JP2018078274A (ja) * 2016-11-10 2018-05-17 サムソン エレクトロ−メカニックス カンパニーリミテッド． イメージセンサー装置及びそれを含むイメージセンサーモジュール
CN108928802A (zh) * 2017-05-27 2018-12-04 北京万应科技有限公司 芯片晶圆封装方法、微机电系统封装方法及微机电系统
US10515936B1 (en) 2018-06-25 2019-12-24 Powertech Technology Inc. Package structure and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201118963A (en) * 2009-09-15 2011-06-01 Stats Chippac Ltd Integrated circuit packaging system with package-on-package and method of manufacture thereof
TW201208021A (en) * 2010-08-12 2012-02-16 Siliconware Precision Industries Co Ltd Chip Scale Package and fabrication method thereof
TW201240040A (en) * 2010-12-02 2012-10-01 Tessera Inc Stacked microelectronic assembly with TSVs formed in stages with plural active chips
TW201246499A (en) * 2010-12-22 2012-11-16 Intel Corp A multi-chip package having a substrate with a plurality of vertically embedded die and a process forming the same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3772066B2 (ja) * 2000-03-09 2006-05-10 沖電気工業株式会社 半導体装置
DE102004058395A1 (de) * 2004-12-03 2006-06-08 Infineon Technologies Ag Verfahren zum Verdrahten von einem stapelbaren Halbleiterchip und eine Halbleitervorrichtung mit gestapelten Halbleiterchips
US20070069389A1 (en) * 2005-09-15 2007-03-29 Alexander Wollanke Stackable device, device stack and method for fabricating the same
US7884464B2 (en) * 2006-06-27 2011-02-08 Advanced Chip Engineering Technologies Inc. 3D electronic packaging structure having a conductive support substrate
SG148901A1 (en) * 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
US7858440B2 (en) * 2007-09-21 2010-12-28 Infineon Technologies Ag Stacked semiconductor chips
TWI360207B (en) * 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
JP2010147153A (ja) * 2008-12-17 2010-07-01 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2010205851A (ja) * 2009-03-02 2010-09-16 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法、並びに電子装置
US7960827B1 (en) * 2009-04-09 2011-06-14 Amkor Technology, Inc. Thermal via heat spreader package and method
US8383457B2 (en) * 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
EP2309535A1 (en) * 2009-10-09 2011-04-13 Telefonaktiebolaget L M Ericsson (Publ) Chip package with a chip embedded in a wiring body
US8508954B2 (en) * 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package
US8951839B2 (en) * 2010-03-15 2015-02-10 Stats Chippac, Ltd. Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP
US8941222B2 (en) * 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US8466544B2 (en) * 2011-02-25 2013-06-18 Stats Chippac, Ltd. Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP
US8597986B2 (en) * 2011-09-01 2013-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. System in package and method of fabricating same
US8552556B1 (en) * 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201118963A (en) * 2009-09-15 2011-06-01 Stats Chippac Ltd Integrated circuit packaging system with package-on-package and method of manufacture thereof
TW201208021A (en) * 2010-08-12 2012-02-16 Siliconware Precision Industries Co Ltd Chip Scale Package and fabrication method thereof
TW201240040A (en) * 2010-12-02 2012-10-01 Tessera Inc Stacked microelectronic assembly with TSVs formed in stages with plural active chips
TW201246499A (en) * 2010-12-22 2012-11-16 Intel Corp A multi-chip package having a substrate with a plurality of vertically embedded die and a process forming the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10770433B1 (en) 2019-02-27 2020-09-08 Apple Inc. High bandwidth die to die interconnect with package area reduction
TWI720801B (zh) * 2019-02-27 2021-03-01 美商蘋果公司 具有封裝面積縮減的高頻寬晶粒對晶粒互連
US11587909B2 (en) 2019-02-27 2023-02-21 Apple Inc. High bandwidth die to die interconnect with package area reduction

Also Published As

Publication number Publication date
KR20150109477A (ko) 2015-10-01
US20140210106A1 (en) 2014-07-31
JP2016504774A (ja) 2016-02-12
TW201438159A (zh) 2014-10-01
WO2014120483A1 (en) 2014-08-07
CN104969347A (zh) 2015-10-07

Similar Documents

Publication Publication Date Title
US11508695B2 (en) Redistribution layers in semiconductor packages and methods of forming same
US10867976B2 (en) Semiconductor packages having dummy connectors and methods of forming same
US11929349B2 (en) Semiconductor device having laterally offset stacked semiconductor dies
US11456257B2 (en) Semiconductor package with dual sides of metal routing
TWI667762B (zh) 半導體封裝中的重佈線層及其形成方法
US9502335B2 (en) Package structure and method for fabricating the same
TWI585906B (zh) 超薄封裝上封裝ＰｏＰ之封裝
US8889484B2 (en) Apparatus and method for a component package
US8922005B2 (en) Methods and apparatus for package on package devices with reversed stud bump through via interconnections
US20140210080A1 (en) PoP Device
US11158619B2 (en) Redistribution layers in semiconductor packages and methods of forming same
TW201440186A (zh) 堆疊式晶圓雙倍資料率封裝
TWI777358B (zh) 半導體封裝
TW201813021A (zh) 電子封裝件及其製法
TWI567843B (zh) 封裝基板及其製法
US20230377905A1 (en) Dummy through vias for Integrated Circuit Packages and Methods of Forming the Same
CN116344476A (zh) 基板结构及其制造方法