CN104969347A - 超薄PoP封装件 - Google Patents

超薄PoP封装件 Download PDF

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Publication number
CN104969347A
CN104969347A CN201480006272.0A CN201480006272A CN104969347A CN 104969347 A CN104969347 A CN 104969347A CN 201480006272 A CN201480006272 A CN 201480006272A CN 104969347 A CN104969347 A CN 104969347A
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CN
China
Prior art keywords
nude film
couple
layer
insert layer
terminal
Prior art date
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Pending
Application number
CN201480006272.0A
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English (en)
Inventor
翟军
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Apple Inc
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Apple Computer Inc
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Publication date
Application filed by Apple Computer Inc filed Critical Apple Computer Inc
Publication of CN104969347A publication Critical patent/CN104969347A/zh
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

本发明公开了一种PoP(层叠封装)封装件，该PoP封装件包括耦接到顶部封装件的底部封装件。该底部封装件包括利用粘合剂层耦接到插入层的裸片。一个或多个端子耦接到位于裸片的周边上的插入层。端子和裸片至少部分地封装于封装剂中。端子和裸片耦接到再分布层(RDL)。RDL的底部上的端子用于将PoP封装件耦接到母板或印刷电路板(PCB)。一个或多个附加端子将插入层耦接到顶部封装件。附加端子可位于沿插入层的表面的任何地方。

Description

超薄PoP封装件
技术领域
本发明涉及半导体封装件以及用于封装半导体器件的方法。更具体地，本发明涉及PoP(层叠封装)的底部封装件。
背景技术
随着在半导体工业中对更低成本、更高性能、更大集成电路密度和更大封装密度的需求的持续，层叠封装(“PoP”)技术已变得越来越普及。随着对越来越小的封装件的推进增强，裸片和封装件的集成(例如，“预堆叠”或片上系统(“SoC”)技术与存储器技术的集成)允许更薄的封装件。此类预堆叠已成为薄细间距PoP封装件的关键组成部分。
减小封装件的尺寸(例如，PoP封装件中的顶部封装件(存储器封装件)或底部封装件(SoC封装件))的一个限制是在封装件中使用的衬底的尺寸。薄衬底和/或无核衬底(例如，层压衬底)已被用于将封装件的尺寸减小到特定水平。然而，为了给下一代器件提供更小的封装件，可能需要进一步减小尺寸。
在减小封装件的尺寸时可能出现的一个潜在问题是，在封装件变得越来越薄时，封装件中翘曲的可能性增大。翘曲问题可能会导致PoP封装件的失效或性能降低和/或利用PoP封装件的器件的可靠性问题。例如，PoP封装件中的顶部封装件和底部封装件之间的翘曲行为的差异可能会导致耦接封装件的焊料结合部中的良率损失。由于对顶部封装件和底部封装件提出了严苛的翘曲指标，可能有大部分的PoP结构会被丢弃(废弃)。废弃的PoP结构导致预堆叠良率低、材料浪费和制造成本升高。
尽管正在采取和构想很多改进和/或设计修改来抑制使用薄衬底或无核衬底的封装件中发生翘曲，但在比利用薄衬底或无核衬底的那些封装件更小的封装件中减小翘曲仍可能需要进一步的改进或设计修改。
发明内容
在某些实施例中，一种PoP封装件包括底部封装件和顶部封装件。底部封装件可包括耦接在入层和再分布层(RDL)之间的裸片。裸片可至少部分地包封在介于插入层和再分布层之间的封装剂中。可利用粘合剂层将裸片耦接到插入层。裸片的周边上的一个或多个端子可将插入层耦接到再分布层。端子可至少部分地包封于封装剂中。
一个或多个端子可将所述插入层的顶部耦接到顶部封装件的底部。顶部封装件可以是存储器封装件(例如，包括一个或多个存储器裸片)。耦接插入层和顶部封装件的端子可分布于插入层的表面上的任何地方(例如，端子不限于在底部封装件中的裸片的周边上)。底部封装件中的插入层和RDL有助于抑制底部封装件中的翘曲并减小PoP封装件的总厚度。
附图说明
当与附图结合时，根据本发明参考目前优选的但仅为示例性实施例的以下详细描述，将更充分地理解本发明的方法与装置的特征和优点，在该附图中：
图1A-E示出了用于形成PoP封装件的工艺流程的实施例的横截面图。
尽管本发明易受各种修改形式和替代形式的影响，但附图中以举例的方式示出了其具体实施例并将在本文进行详细描述。附图可能不是按比例的。然而，应当理解，附图及对其的详细描述并非旨在将本发明限制于所公开的特定形式，而正相反，本发明在于覆盖落在由所附权利要求所限定的本发明的实质和范围内的所有修改形式、等同形式和替代形式。
具体实施方式
图1A-E示出了用于形成PoP封装件的工艺流程的实施例的横截面图。图1A示出了插入层102的实施例的横截面图，其中端子104耦接到插入层的下表面(侧)。在某些实施例中，在端子104已附接(例如，预附接)到插入层102的情况下向工艺流程提供插入层/端子的组合。端子104可以是例如铝球或另一种合适导电材料的球。在一些实施例中，端子104涂布有焊料或涂布有Sn。
在某些实施例中，插入层102包括两个有源层106(例如，两个有源金属层)，使得插入层为2层插入层。在一些实施例中，插入层102包括多于两个有源层106。可设计插入层102中的多个有源层106以提供穿过插入层的非垂直布线(例如，将插入层的有源层设计成如同它们在多层PCB(印刷电路板)中那样)。因此，可设计插入层102以耦接彼此不是镜像的端子(例如，该端子在插入层的相对侧上彼此不正对)。
在某些实施例中，插入层102包括层压材料。例如，插入层102可包括BT(双马来酰亚胺/三嗪)层压体或任何其他合适的预浸(预先浸渍的)层压材料。有源层106可包括导电金属层诸如铜、铝或金。可使用用于形成层压材料的本领域中已知的技术来形成插入层102。
在形成/提供了附接有端子104的插入层102之后，可将裸片耦接到插入层。图1B示出了耦接到裸片108的插入层102的实施例的横截面图。在某些实施例中，裸片108是处理器或逻辑裸片，或者裸片108是片上系统(“SoC”)。裸片108可以是例如半导体芯片裸片诸如倒装芯片裸片。
可使用用于裸片/层压界面的已知键合技术将裸片108耦接(例如，附接)到插入层102。在某些实施例中，利用粘合剂层110将裸片耦接到插入层102。粘合剂层110可以是例如可固化环氧树脂或另一种合适的裸片附接膜。
在将裸片108耦接到插入层102之后，将裸片和端子104至少部分地封装于耦接到插入层的封装剂中。图1C示出了封装于封装剂112中的裸片110和端子104的实施例的横截面图。封装剂112可以是例如聚合物或模塑化合物。在一些实施例中，将插入层102、端子104和裸片108置于重建器上，在其上形成封装剂(模具)并封装端子和裸片。可由封装剂112暴露出端子104和裸片108的底表面的至少某个部分，以允许将端子和裸片耦接(例如，键合)到PoP封装件中的稍后形成的层。
在封装裸片108和端子104之后，可形成再分布层(RDL)并将其耦接到裸片和/或端子以形成底部封装件。图1D示出了耦接到裸片108和端子104以形成底部封装件120的再分布层(RDL)114的实施例的横截面图。RDL 114也可耦接到封装剂112。RDL 114可包括材料，诸如但不限于PI(聚酰亚胺)、PBO(聚苯并唑)、BCB(苯并环丁烯)和WPR(晶片光致抗蚀剂，诸如能够以商标名WPR商购获得的酚醛树脂和聚(羟基苯乙烯)(PHS)，WPR包括WPR-1020、WPR-1050和WPR-1201(WPR是JSR Corporation,Tokyo,Japan的注册商标))。可使用本领域中已知的技术(例如，用于聚合物沉积的技术)在裸片108、端子104和封装剂112上形成RDL 114。在某些实施例中，RDL 114包括用于耦接到端子104的一个或多个着陆焊盘。例如，RDL 114可包括用于耦接到端子104的铝着陆焊盘或涂布有焊料或涂布有Sn的铝着陆焊盘。
在形成RDL 114之后，可将端子116耦接到RDL，如图1D所示。端子116可用于将底部封装件120耦接到母板或印刷电路板(PCB)。端子116可包括铝或另一种合适的导电材料。在一些实施例中，端子116涂布有焊料或涂布有Sn。
在某些实施例中，RDL 114包括裸片108和端子116中的一个或多个端子之间的布线(例如，线路或连接)和/或端子104和端子116中的一个或多个端子之间的布线。因此，RDL 114在远离裸片和端子的位置处允许将裸片108和/或端子104通过端子116键合到和电耦接到母板或PCB。
与通常用于SoC封装件的衬底(例如，PoP封装件中的底部封装件)相比，RDL 114可以是相对薄的层。例如，RDL 114可具有小于约50μm(例如，约25μm)的厚度，而典型的薄衬底具有约300μm-400μm的厚度，并且无核衬底具有在约200μm的范围中的厚度。因此，在底部封装件120中使用RDL 114减小了底部封装件和包含底部封装件的PoP封装件的总厚度。例如，底部封装件120可具有约350μm或更小的厚度。
此外，在底部封装件102的顶部上使用插入层102并在底部封装件的底部上使用RDL 114可以减轻底部封装件中的翘曲问题。例如，插入层102和RDL 114可具有相似的热学性质(例如，热膨胀系数(“CTE”)和/或收缩率)，使得插入层和RDL以相对类似的速率膨胀/收缩以抑制底部封装件120中的翘曲。在一些实施例中，底部封装件120可因为使用插入层102和RDL 114而被压平(例如，使用压缩力)。压平底部封装件120可减小或消除底部封装件中的翘曲。减轻底部封装件120中的翘曲问题可产生PoP封装件的更高良率(例如，减少由于翘曲问题而废弃的封装件的数量)，由此提高了可靠性并降低了制造成本。
在某些实施例中，将顶部封装件130耦接到底部封装件120以形成PoP封装件100，如图1E所示。可使用一个或多个端子132将顶部封装件130耦接到底部封装件120。端子132可与插入层102中的开口(例如，通往插入层中的有源层106的开口)耦接。插入层102可预形成有开口，以用于将端子132耦接到有源层106(例如，如图1A所示，插入层102可能已经具有开口)。端子132可以是例如焊料球、铜柱或用于顶部封装件130和插入层102之间的接触的其他合适的端子。
典型的PoP封装件中的顶部封装件具有位于顶部封装件的周边附近的端子(例如，用于端子从裸片扇出的端子的线路)。端子向外扇出，使得可在底部封装件中的裸片的周边上进行连接，因为底部封装件中的裸片通常暴露于底部封装件中的封装剂的上方。因为顶部封装件130中的端子132耦接到插入层102并且插入层基本覆盖底部封装件120的顶表面并覆盖裸片108，所以端子132不限于仅位于周边上(例如，端子可位于插入层的表面上的任何地方)。因此，PoP封装件100可使用比典型PoP封装件更大数量的端子132来将顶部封装件130耦接到底部封装件120。使用多很多的端子132并增大端子的位置可用性允许顶部封装件130的更大的设计灵活性，从而允许PoP封装件100的更好的集成度。例如，顶部封装件130可具有与典型的PoP封装件不同尺寸的存储器裸片和/或顶部封装件可具有扇入引线键合图案而不是扇出引线键合图案。
顶部封装件130可包括衬底以及包封于封装剂中的一个或多个裸片。可使用例如一个或多个引线键合将顶部封装件130中的裸片耦接(例如，连接)到衬底。顶部封装件130中的裸片可以是例如半导体芯片诸如引线键合裸片或倒装芯片裸片。在某些实施例中，顶部封装件130中的裸片为存储器裸片(例如，DRAM裸片)。
在某些实施例中，顶部封装件130包括具有最小层数的存储器裸片。例如，顶部封装件130可包括层数为两层(2L)的存储器裸片。在顶部封装件130中具有最小层数使得PoP封装件100的总厚度最小化。在某些实施例中，顶部封装件130具有约450μm的厚度。因此，如果底部封装件120具有约350μm的厚度，则PoP封装件可具有约800μm的总厚度。可通过例如压平顶部封装件130或底部封装件120来进一步减小PoP封装件的厚度。
在某些实施例中，顶部封装件130和插入层102是共同设计的(例如，彼此连接地设计每一者中的布局/布线)。共同设计的顶部封装件130和插入层102可改善和/或最大化顶部封装件和插入层之间的信号完整性，从而改善PoP封装件100的性能。
根据本说明书，本发明的各个方面的其他修改和替代实施例对于本领域的技术人员而言将是显而易见的。因此，本说明书应被理解为仅是示例性的，并且其目的是用于教导本领域的技术人员执行本发明的一般方式。应当理解，本文所示和所述的本发明的形式将被视为目前优选的实施例。元件与材料可被本文所示和所述的那些元素与材料所替代，可反向部件和工艺并且可独立地利用本发明的某些特征，在受益于本发明的本说明书之后，所有这些对于本领域的技术人员而言都将是显而易见的。可在不脱离以下权利要求书中所描述的本发明的实质和范围的情况下对本文所述的元素作出修改。

Claims (14)

1.一种半导体器件封装件，包括：
再分布层；
所述再分布层之上的封装剂；
所述封装剂之上的插入层；
至少部分地包封于所述封装剂中的裸片，其中所述裸片耦接到所述再分布层的上表面和所述插入层的下表面；和
将所述插入层的至少一部分耦接到所述再分布层的至少一部分的一个或多个端子，其中所述端子位于所述裸片的周边上的所述封装剂中。
2.根据权利要求1所述的封装件，其中利用粘合剂层将所述裸片耦接到所述插入层的所述下表面。
3.根据权利要求1所述的封装件，还包括存储器封装件，所述存储器封装件通过位于所述插入层的与所述裸片相对侧上的一个或多个附加端子耦接到所述插入层。
4.根据权利要求3所述的封装件，其中所述附加端子定位在所述裸片的所述周边上和所述裸片之上。
5.根据权利要求3所述的封装件，其中所述插入层包括布线，所述布线对应于将所述插入层的至少一部分耦接到所述再分布层的至少一部分的所述一个或多个端子的位置以及位于所述插入层的与所述裸片相对侧上的所述一个或多个附加端子的位置。
6.一种用于形成半导体器件封装件的方法，包括：
提供插入层，其中一个或多个第一端子耦接到所述插入层的第一侧；
利用位于所述裸片的周边上的所述端子将所述裸片耦接到所述插入层的所述第一侧；
将所述裸片和所述端子至少部分地封装在封装剂中；以及
将再分布层耦接到所述裸片和所述端子。
7.根据权利要求6所述的方法，还包括利用粘合剂层将所述裸片耦接到所述插入层。
8.根据权利要求6所述的方法，还包括使用位于所述插入层的与所述第一侧相对的第二侧上的一个或多个附加端子将存储器封装件耦接到所述插入层。
9.根据权利要求6所述的方法，还包括将一个或多个附加端子耦接到所述再分布层的下表面，并且将所述附加端子耦接到母板或印刷电路板。
10.一种半导体器件封装件，包括：
定位在插入层和再分布层之间的模塑材料；
至少部分地包封于所述模塑材料中的裸片，其中所述裸片耦接到所述插入层和所述再分布层；和
将所述插入层耦接到所述再分布层的一个或多个端子，其中所述端子位于所述裸片的周边上的所述模塑材料中。
11.根据权利要求10所述的封装件，其中利用粘合剂层将所述裸片耦接到所述插入层。
12.根据权利要求10所述的封装件，还包括位于所述插入层的与所述裸片相对侧上的一个或多个附加端子，其中所述附加端子被配置为将所述封装件耦接到存储器封装件。
13.根据权利要求10所述的封装件，其中所述再分布层包括将所述裸片耦接到位于所述裸片的所述周边上的一个或多个附加端子的电布线。
14.根据权利要求10所述的封装件，其中所述插入层包括两层插入层。
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US20140210106A1 (en) 2014-07-31
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JP2016504774A (ja) 2016-02-12
KR20150109477A (ko) 2015-10-01

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