US20210375642A1 - Semiconductor package method of fabricating semiconductor package and method of fabricating re-distribution structure - Google Patents

Semiconductor package method of fabricating semiconductor package and method of fabricating re-distribution structure Download PDF

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Publication number
US20210375642A1
US20210375642A1 US17/399,941 US202117399941A US2021375642A1 US 20210375642 A1 US20210375642 A1 US 20210375642A1 US 202117399941 A US202117399941 A US 202117399941A US 2021375642 A1 US2021375642 A1 US 2021375642A1
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Prior art keywords
layer
stack
semiconductor package
insulating layer
distribution layer
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US17/399,941
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Kyoung Lim SUK
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to US17/399,941 priority Critical patent/US20210375642A1/en
Publication of US20210375642A1 publication Critical patent/US20210375642A1/en
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    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present disclosure relates to a semiconductor package, and in particular, to a semiconductor package including a re-distribution layer.
  • the semiconductor package includes a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and is electrically connected to the PCB by bonding wires or bumps.
  • PCB printed circuit board
  • a semiconductor package device may include a plurality of semiconductor chips mounted on a package substrate or a semiconductor device package may be stacked on another package to meet such a demand.
  • Some embodiments of the inventive concept provide a method of fabricating a semiconductor package with a re-distribution layer, using a chip-last process.
  • Some embodiments of the inventive concept provide a method capable of reducing a size of vias in a semiconductor package.
  • a semiconductor package may include a lower re-distribution layer, a stack provided on a first region of a top surface of the lower re-distribution layer, a semiconductor chip provided on a second region of the top surface of the lower re-distribution layer, and an upper re-distribution layer on the semiconductor chip and the stack.
  • the upper re-distribution layer may be electrically connected to the lower re-distribution layer via the stack.
  • a method of fabricating a semiconductor package may include forming a lower re-distribution layer, forming a stack, bonding the stack to a portion of the lower re-distribution layer, stacking a semiconductor chip on a top surface of the lower re-distribution layer after bonding the stack, and forming an upper re-distribution layer on the semiconductor chip and the stack.
  • a method of fabricating a re-distribution structure may include forming a lower re-distribution layer, forming a stack, and bonding the stack to a top surface of the lower re-distribution layer.
  • the stack may include a first insulating layer disposed on the top surface of the lower re-distribution layer, a second insulating layer disposed on a top surface of the first insulating layer, a first via penetrating the first insulating layer, and a second via penetrating the second insulating layer.
  • FIG. 1 is a flow chart illustrating a method of fabricating a semiconductor device, according to an embodiment of the inventive concept.
  • FIG. 2 is a sectional view illustrating a first carrier substrate according to an embodiment of the inventive concept.
  • FIG. 3 is a sectional view illustrating a step of forming a lower re-distribution layer, according to the flow chart of FIG. 1 .
  • FIGS. 4A to 4C are sectional views illustrating steps of forming stack structures, according to the flow chart of FIG. 1 .
  • FIG. 5 is a sectional view illustrating a step of bonding a stack to a lower re-distribution layer, according to the flow chart of FIG. 1 .
  • FIG. 6 is a sectional view illustrating a step of stacking a semiconductor chip, according to the flow chart of FIG. 1 .
  • FIG. 7 is a sectional view illustrating a molding step, according to the flow chart of FIG. 1 .
  • FIG. 8 is a sectional view illustrating a step of forming an upper re-distribution layer, according to the flow chart of FIG. 1 .
  • FIG. 9 is a sectional view illustrating a step of removing the first carrier substrate, according to an embodiment of the inventive concept.
  • FIG. 10A is a sectional view illustrating a step of stacking an upper package, according to the flow chart of FIG. 1 .
  • FIG. 10B is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 11 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 12 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 13 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 14 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 1 is a flow chart illustrating a method of fabricating a semiconductor package
  • FIGS. 2 to 9 are sectional views illustrating a process of fabricating a semiconductor package, according to the flow chart of FIG. 1 .
  • a direction D 1 of FIG. 2 will be referred to as a first or upward direction and a direction D 2 will be referred to as a second or rightward direction.
  • a method S of fabricating a semiconductor package may include forming a lower re-distribution layer (in 51 ), forming a stack (in S 1 ′), bonding the stack to the lower re-distribution layer (in S 2 ), stacking a semiconductor chip (in S 3 ), performing a molding process (in S 4 ), forming an upper re-distribution layer (in S 5 ), and stacking an upper package (in S 6 ).
  • a first carrier substrate 8 may be provided for the forming of the lower re-distribution layer (in S 1 ).
  • a lower re-distribution layer 1 may be formed on a top surface of the first carrier substrate 8 .
  • the lower re-distribution layer 1 may be formed by depositing or coating a photosensitive material on the first carrier substrate 8 , forming holes in the photosensitive material by an exposure and develop process, and filling the holes with a conductive material.
  • the lower re-distribution layer 1 may include a lower redistribution insulator 11 , a lower redistribution outer terminal 131 , a lower redistribution pattern 133 , a lower redistribution connection terminal 135 , and a lower redistribution via 15 .
  • a lower redistribution hole 17 may be provided in a bottom surface of the lower redistribution insulator 11 .
  • the lower redistribution layer 1 may be a layer configured to redistribute in/out pads of a semiconductor chip into different spatial positions and/or shapes, e.g., into a wider distribution than the original one on the semiconductor chip and/or into bigger pads than the original ones formed on the semiconductor chip.
  • the lower redistribution layer 1 may electrically connect two or more pads formed on the semiconductor chip.
  • the lower redistribution insulator 11 may include a photosensitive material.
  • the photosensitive material may include a photosensitive polymer.
  • the photosensitive polymer may include at least one of photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, benzocyclobutene (BCB) polymer, or a photo imageable dielectric (PID) material.
  • PSPI photosensitive polyimide
  • PBO polybenzoxazole
  • BCB benzocyclobutene
  • PID photo imageable dielectric
  • the inventive concept is not limited to the example materials for the lower redistribution insulator 11 .
  • the lower redistribution insulator 11 may be used as a main body of the lower re-distribution layer 1 .
  • the lower redistribution insulator 11 may protect the lower redistribution pattern 133 .
  • the lower redistribution insulator 11 may have a multi-layered structure.
  • a plurality of the lower redistribution patterns 133 may be provided in the first and second directions D 1 and D 2 .
  • the lower redistribution patterns 133 which are spaced apart from each other in the first direction D 1 , may be provided to form a plurality of layers, e.g., a plurality of layers of lower redistribution patterns 133 .
  • the lower redistribution patterns 133 may be spaced apart from each other in the second direction D 2 as shown in FIG. 3 .
  • the lower redistribution via 15 may be used to electrically connect the lower redistribution patterns 133 , which are spaced apart from each other in the first direction D 1 , to each other.
  • the expression “electrically connect elements” may mean a direct connection between the elements or an indirect connection between the elements through another conductive element.
  • the lower redistribution via 15 may have an increasing width in a direction along the first direction D 1 , e.g., in a cross-sectional view.
  • the inventive concept is not limited to this example, and in an embodiment, the width of the lower redistribution via 15 may be constant in the first direction D 1 or may vary in various other manners.
  • the lower redistribution outer terminal 131 may be placed on a first region of a top surface of the lower redistribution insulator 11 .
  • the first region may be an edge region of the top surface of the lower redistribution insulator 11 .
  • the lower redistribution outer terminal 131 may be a pad.
  • the lower redistribution outer terminal 131 may be a contact pad configured to be electrically connected to (e.g., contact) a solder ball.
  • a plurality of the lower redistribution outer terminals 131 may be provided.
  • the lower redistribution outer terminal 131 may be used to electrically connect at least one of the lower redistribution patterns 133 to integrated circuits (not shown) of a semiconductor chip 5 (e.g., see FIG. 9 ).
  • the lower redistribution connection terminal 135 may be placed on a second region of the top surface of the lower redistribution insulator 11 .
  • the second region may be a center region of the top surface of the lower redistribution insulator 11 .
  • the second region may be positioned within a region enclosed by the first region, e.g., in a plan view.
  • the first region may be closer to the side surface of the lower redistribution insulator 11 than the second region.
  • the lower redistribution connection terminal 135 may be a pad.
  • the lower redistribution connection terminal 135 may be a contact pad configured to be electrically connected to (e.g., contact) a solder ball.
  • a plurality of the lower redistribution connection terminals 135 may be provided.
  • the lower redistribution connection terminal 135 may be used to electrically connect at least one of the lower redistribution patterns 133 to a stack 3 (e.g., see FIG. 9 ).
  • Each of the lower redistribution outer terminal 131 , the lower redistribution pattern 133 , the lower redistribution connection terminal 135 , and the lower redistribution via 15 may be formed of or include a conductive material.
  • the conductive material may include metallic materials such as copper or aluminum.
  • the lower redistribution hole 17 may be formed in a bottom surface of the lower re-distribution layer 1 to have a specific depth in the first direction D 1 , thereby exposing at least one of the lower redistribution patterns 133 .
  • a stack 3 may be formed on a top surface of a second carrier substrate 8 ′ during the forming of the stack (in S 1 ′).
  • the stack 3 may include a first via 331 , a second via 333 , a first terminal 311 , a first interconnection line 313 , a second terminal 315 , a first insulator 351 , and a second insulator 353 .
  • the first insulator 351 may be placed on the second insulator 353 .
  • the first via 331 may be provided to penetrate the first insulator 351 .
  • the second via 333 may be provided to penetrate the second insulator 353 .
  • the first via 331 and the second via 333 may be electrically connected to each other through the first interconnection line 313 .
  • the first terminal 311 may be connected to the first via 331 .
  • the stack 3 may be a stack of insulators and conductor patterns (e.g., conductor lines and/or contact vias).
  • the first via 331 and the second via 333 may be off-centered from each other, when viewed in a plan view.
  • a vertically extending central axis Cl extending along a geometric center of the first via 331 may be spaced apart from a vertically extending central axis C 2 extending along a geometric center of the second via 333 .
  • the first and second vias 331 and 333 which are off-centered from each other, may be connected to each other by the first interconnection line 313 .
  • This off-centered structure of the first and second vias 331 and 333 may be beneficial to electrically connect offset contact pads respectively formed on the first redistribution layer 1 and a second redistribution layer 7 which will be described below.
  • the stack 3 may be formed by depositing or coating a photosensitive material, forming holes in the photosensitive material by an exposure and develop process, and filling the holes with a conductive material.
  • the inventive concept is not limited to this example, and the stack 3 may be formed by other methods.
  • At least one of the first insulator 351 and the second insulator 353 may include a photosensitive material.
  • the photosensitive material may include a photosensitive polymer.
  • the photosensitive polymer may include at least one of photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, benzocyclobutene (BCB) polymer, or a photo imageable dielectric (PID) material.
  • PSPI photosensitive polyimide
  • PBO polybenzoxazole
  • BCB benzocyclobutene
  • PID photo imageable dielectric
  • the first via 331 , the second via 333 , the first interconnection line 313 , the second terminal 315 , and the first terminal 311 may be formed of or include at least one conductive material.
  • the conductive material may include aluminum or copper, but the inventive concept is not limited thereto.
  • the stack 3 may be vertically inverted on the second carrier substrate 8 ′.
  • the first terminal 311 may be exposed upwardly.
  • connection ball 24 may be formed on the first terminal 311 .
  • the connection ball 24 may be a solder ball, but the inventive concept is not limited thereto.
  • the order of forming the lower re-distribution layer (in Si) and the stack (in Si′) in FIG. 1 may be changed.
  • the forming of the lower re-distribution layer (in Si) may be performed before the forming of the stack (in Si′), or the forming of the stack (in Si′) may be performed before the forming of the lower re-distribution layer (in Si).
  • the forming of the lower re-distribution layer (in Si) and the forming of the stack (in Si′) may be performed at the same time.
  • the lower redistribution layer 1 and the stack 3 may be formed at the same time from different manufacturing apparatuses, and then may be combined as shown in FIG. 5 .
  • the bonding of the stack 3 to the lower re-distribution layer may include boding the stack 3 on the lower re-distribution layer 1 .
  • the stack 3 of FIG. 3B may be inverted in such a way that the connection ball 24 is in contact with the lower redistribution outer terminal 131 of the lower re-distribution layer 1 .
  • a bonding process may be performed.
  • the bonding process may be a reflow process or a thermo-compression process, but the inventive concept is not limited thereto.
  • connection ball 24 and the lower redistribution outer terminal 131 may be bonded to each other by the bonding process.
  • the second terminal 315 , the second via 333 , the first interconnection line 313 , the first via 331 , the first terminal 311 , and the connection ball 24 may be electrically connected to the lower redistribution pattern 133 through the lower redistribution outer terminal 131 .
  • the stack 3 and the lower re-distribution layer 1 bonded to each other may be referred to as a re-distribution structure.
  • the first insulator 351 may be thicker than one of the layers constituting the lower redistribution insulator 11 .
  • the first via 331 may have a decreasing or constant width in a direction from the top surface of the first insulator 351 toward the lower re-distribution layer 1 , e.g., in a cross-sectional view.
  • the second via 333 may have a decreasing or constant width in a direction from a top surface of the second insulating layer 353 toward the first insulator 351 , e.g., in a cross-sectional view.
  • the stacking of the semiconductor chip may include stacking a semiconductor chip 5 on a top surface of the lower re-distribution layer 1 .
  • the semiconductor chip 5 may include at least one of a memory chip, a logic chip, or a combination thereof.
  • the semiconductor chip 5 may be electrically connected to the lower redistribution connection terminal 135 of the lower re-distribution layer 1 via an intermediate ball 22 .
  • the semiconductor chip 5 may be electrically connected to the lower redistribution pattern 133 .
  • the semiconductor chip 5 may be provided in such a way that a bottom surface 53 thereof faces the top surface of the lower re-distribution layer 1 .
  • the intermediate ball 22 may be a solder ball, but the inventive concept is not limited thereto.
  • the bonding process may be performed.
  • the intermediate ball 22 may reflow to bond the lower redistribution pad 135 to the semiconductor chip 5 .
  • heat and pressure may be applied to the intermediate ball 22 so that the intermediate ball 22 may be bonded to the semiconductor chip 5 .
  • the bonding process may be a reflow process or a thermo-compression process, but the inventive concept is not limited thereto.
  • the intermediate ball 22 and the lower redistribution connection terminal 135 may be bonded to each other by the bonding process.
  • the molding process may include forming a mold layer 4 to cover at least one of surfaces of the semiconductor chip 5 .
  • the mold layer 4 may protect the semiconductor chip 5 from external attack. For example, owing to the mold layer 4 , the semiconductor chip 5 may be protected from external heat, moisture, and/or impact.
  • the mold layer 4 may be configured to exhaust (e.g., release) heat, which is generated from the semiconductor chip 5 , the lower re-distribution layer 1 , and/or the stack 3 , to the outside.
  • the mold layer 4 may cover a top surface 51 of the semiconductor chip 5 .
  • the mold layer 4 may cover an outer side surface (not shown) of the stack 3 .
  • the mold layer 4 may be provided to fill a gap region between a side surface of the semiconductor chip 5 and a first inner side surface 351 c and/or a second inner side surface 353 c of the stack 3 .
  • the side surface of the semiconductor chip 5 is parallel to the first and second inner side surfaces 351 c and 353 c of respective first and second insulators of the stack 3 .
  • An underfill layer may be further provided around the lower redistribution connection terminal 135 .
  • the mold layer 4 may be formed of or include an epoxy molding compound (EMC) material.
  • EMC epoxy molding compound
  • the mold layer may be formed of a different material from the first and second insulators 351 and 353 of the stack 3 .
  • the molding process may include placing the lower re-distribution layer 1 , on which the semiconductor chip 5 and the stack 3 are stacked, in a mold and then injecting a material for the mold layer 4 into the mold.
  • the mold layer 4 may include an Ajinomoto build-up film (ABF).
  • ABSF Ajinomoto build-up film
  • the inventive concept is not limited thereto, and other insulator may be used for the mold layer 4 .
  • the forming of the upper re-distribution layer may include forming an upper re-distribution layer 7 on the top surface of the mold layer 4 and/or on a top portion of the stack 3 , after the molding process.
  • the upper re-distribution layer 7 may be formed by depositing or coating a photosensitive material on the top surface of the mold layer 4 and/or the top portion of the stack 3 , forming holes in the photosensitive material by an exposure and develop process, and filling the holes with a conductive material.
  • the upper re-distribution layer 7 may include a first upper redistribution insulating layer 711 , a second upper redistribution insulating layer 713 , an upper redistribution pattern 731 , a first upper redistribution via 751 , a second upper redistribution via 753 , and an upper redistribution terminal 733 .
  • the upper redistribution layer 7 may be a layer configured to redistribute in/out pads of a semiconductor chip into different spatial positions and/or shapes, e.g., into a wider distribution than the original one formed on the semiconductor chip and/or into bigger pads than the original ones formed on the semiconductor chip.
  • the upper redistribution layer 7 may electrically connect two or more pads formed on the semiconductor chip.
  • the first upper redistribution insulating layer 711 may be provided on the mold layer 4 and the stack 3 .
  • the first upper redistribution insulating layer 711 may contact the mold layer 4 and the stack 3 , e.g., the second terminal 315 and/or an insulating layer of the stack 3 .
  • the second upper redistribution insulating layer 713 may be provided on the first upper redistribution insulating layer 711 .
  • the first upper redistribution insulating layer 711 and the second upper redistribution insulating layer 713 may include a photosensitive material.
  • the photosensitive material may include a photo imageable dielectric (PID) material.
  • PID photo imageable dielectric
  • the first upper redistribution insulating layer 711 and the second upper redistribution insulating layer 713 may protect the upper redistribution pattern 731 , the first upper redistribution via 751 , and the second upper redistribution via 753 .
  • the first upper redistribution via 751 may be provided to penetrate the first upper redistribution insulating layer 711 .
  • a plurality of the first upper redistribution vias 751 may be arranged in the second direction D 2 .
  • At least one of the first upper redistribution vias 751 may be electrically connected to the upper redistribution terminal 733 .
  • the upper redistribution pattern 731 may be provided on the first upper redistribution via 751 . In an embodiment, a plurality of the upper redistribution patterns 731 may be provided. At least one of the upper redistribution patterns 731 may extend in the second direction D 2 . The upper redistribution pattern 731 may be electrically connected to the first upper redistribution via 751 .
  • the second upper redistribution via 753 may be provided to penetrate the second upper redistribution insulating layer 713 .
  • a plurality of the second upper redistribution vias 753 may be arranged in the second direction D 2 .
  • the second upper redistribution vias 753 may be electrically connected to the upper redistribution pattern 731 .
  • the upper redistribution terminal 733 may be provided on the second upper redistribution via 753 . In an embodiment, a plurality of the upper redistribution terminals 733 may be provided. The upper redistribution terminal 733 may be electrically connected to the second upper redistribution via 753 . In an embodiment, the upper redistribution terminal 733 may be a pad. For example, the upper redistribution terminal 733 may be a contact pad configured to be electrically connected to (e.g., contact) a solder ball.
  • Each of the upper redistribution pattern 731 , the first upper redistribution via 751 , the second upper redistribution via 753 , and the upper redistribution terminal 733 may be formed of or include a conductive material.
  • the conductive material may include metallic materials such as copper or aluminum.
  • the upper re-distribution layer 7 is provided on the semiconductor chip 5 , terminals of an upper package 9 (e.g., see FIG. 10A ) may be freely disposed.
  • the upper re-distribution layer 7 may reduce difficulty/restriction in designing the upper package 9 .
  • the first carrier substrate 8 may be removed from the bottom surface of the lower re-distribution layer 1 .
  • lower balls 21 may be formed on the lower redistribution patterns 133 exposed by the lower redistribution hole 17 .
  • the lower redistribution patterns 133 may be electrically connected to another package or board through the lower balls 21 .
  • the stacking of the upper package may include stacking the upper package 9 on the upper re-distribution layer 7 .
  • the upper package 9 may include an upper substrate 91 , an upper semiconductor chip 93 , an upper mold layer 95 , an upper wire 97 , and so forth.
  • the upper package 9 and the upper redistribution terminal 733 may be electrically connected to each other through upper balls 23 .
  • the upper balls 23 may be solder balls, but the inventive concept is not limited thereto.
  • the upper ball 23 and the upper redistribution terminal 733 may be bonded to each other, e.g., by a bonding process.
  • the bonding process may be a reflow process or a thermo-compression process.
  • the bonding process according to the inventive concept is not limited to the reflow process or a thermo-compression process.
  • the upper semiconductor chip 93 may be electrically connected to the upper wire 97 , the upper substrate 91 , and the upper ball 23 .
  • the upper package 9 may be electrically connected to the lower re-distribution layer 1 through the upper re-distribution layer 7 and the stack 3 .
  • FIG. 10B is a plan view of a semiconductor package according to an embodiment illustrated in FIG. 10A .
  • FIG. 10A is a sectional view taken along a line I-I′ of FIG. 10B .
  • the semiconductor package may be configured in such a way that an area of the semiconductor chip 5 is smaller than an area enclosed by an outer line of the stack 3 , when viewed in a plan view.
  • the semiconductor chip 5 may be located inside the stack 3 , when viewed in a plan view.
  • FIG. 10B illustrates an example, in which a boundary of the stack 3 is located outside a boundary of the semiconductor chip 5 in all directions, but the inventive concept is not limited thereto.
  • the boundary of the stack 3 may be located outside the boundary of the semiconductor chip 5 in the second direction D 2 , but the boundary of the semiconductor chip 5 may coincide with the boundary of the stack 3 in a third direction, which is perpendicular to the first and second directions D 1 and D 2 .
  • an area of the lower re-distribution layer 1 may be larger than an area of the stack 3 , e.g., an area enclosed by an outer line of the stack 3 when viewed in a plan view.
  • the inventive concept is not limited thereto, and the area enclosed by an outer line of the stack 3 may be substantially equal to the area of the lower re-distribution layer 1 .
  • the lower re-distribution layer and the stack may be formed in advance and then the semiconductor chip may be stacked thereon. This may be beneficial to use the lower re-distribution layer, the stack, and the semiconductor chip, which have been qualified as good products, for the semiconductor package, and consequently to improve a total production yield of the semiconductor package. Furthermore, the lower re-distribution layer and the stack may be formed by an independent process, which may be performed concurrently with the formation of the semiconductor chip. Accordingly, it may be beneficial to reduce a total process time for fabricating the semiconductor package.
  • the upper re-distribution layer since the upper re-distribution layer is provided, it may be beneficial to reduce technical restrictions in disposing the connection terminals of the lower re-distribution layer and/or the stack and in designing an overall structure of the semiconductor package.
  • the upper redistribution layer rearrange in/out contact pads of a semiconductor device disposed on the upper redistribution layer to fit with contact pads of the lower redistribution layer and/or the stack structure.
  • a photolithography process may be beneficial to form a reduced size of a via hole.
  • an overall size of the semiconductor package may be decreased.
  • various embodiments of the present disclosure may be beneficial to stack multiple semiconductor chips in a semiconductor package.
  • the vias may be arranged to form various paths in the stack.
  • FIG. 11 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • the stack 3 may include a first insulating layer 311 ′, a second insulating layer 331 ′, a third insulating layer 351 ′, a first via 315 ′, a second via 335 ′, a third via 355 ′, a first interconnection line 313 ′, a second interconnection line 333 ′, an upper terminal 353 ′, and a connection terminal 303 .
  • the first insulating layer 311 ′ may be placed on the top surface of the lower re-distribution layer 1 .
  • the first insulating layer 311 ′ may be disposed on the top surface of the lower redistribution layer 1 with an underfill layer and the connection ball 24 therebetween.
  • the first via 315 ′ may be provided to penetrate the first insulating layer 311 ′.
  • the first interconnection line 313 ′ may be provided on a first top surface 311 ′ b of the first insulating layer 311 ′.
  • the first interconnection line 313 ′ may be connected to (e.g., contact) the first via 315 ′.
  • the second insulating layer 331 ′ may be placed on the first top surface 311 ′ b of the first insulating layer 311 ′.
  • the second via 335 ′ may be provided to penetrate the second insulating layer 331 ′.
  • the second via 335 ′ may be connected to (e.g., contact) the first interconnection line 313 ′.
  • the second via 335 ′ may be electrically connected to the first via 315 ′ through the first interconnection line 313 ′.
  • the second interconnection line 333 ′ may be placed on a second top surface 331 ′ b of the second insulating layer 331 ′.
  • the second interconnection line 333 ′ may be connected to (e.g., contact) the second via 335 ′.
  • the first insulating layer 311 ′ and the second insulating layer 331 ′ may form a staircase structure in a direction toward the semiconductor chip 5 .
  • the first and second insulating layers 311 ′ and 331 ′ of the stack 3 may have a step structure in a side facing the semiconductor chip 5 .
  • a first inner side surface 311 ′ c of the first insulating layer 311 ′ may be positioned so as not to be aligned to a second inner side surface 331 ′ c of the second insulating layer 331 ′, when viewed in a plan view.
  • side surfaces of the first and second insulating layers 311 ′ and 331 ′ may be positioned to be offset in a plan view.
  • the first inner side surface 311 ′c may be closer to the semiconductor chip 5 than the second inner side surface 331 ′ c .
  • An area of the second top surface 331 ′ b of the second insulating layer 331 ′ may be smaller than an area of the first top surface 311 ′ b of the first insulating layer 311 ′. While the second insulating layer 331 ′ is placed on the first insulating layer 311 ′, a portion 311 ′ b ′ of the first top surface 311 ′ b of the first insulating layer 311 ′ may be exposed by the second insulating layer 331 ′.
  • the third insulating layer 351 ′ may be placed on the second top surface 331 ′ b of the second insulating layer 331 ′.
  • the third via 355 ′ may be provided to penetrate the third insulating layer 351 ′.
  • the third via 355 ′ may be connected to (e.g., contact) the second interconnection line 333 ′.
  • the third via 355 ′ may be electrically connected to the second via 335 ′ through the second interconnection line 333 ′.
  • the upper terminal 353 ′ may be provided on a third top surface of the third insulating layer 351 ′.
  • the upper terminal 353 ′ may be connected to (e.g., contact) the third via 355 ′.
  • the second insulating layer 331 ′ and the third insulating layer 351 ′ may form a staircase structure in a direction toward the semiconductor chip 5 .
  • the second and third insulating layers 331 ′ and 351 ′ of the stack 3 may have a step structure in a side facing the semiconductor chip 5 .
  • the second inner side surface 331 ′ c of the second insulating layer 331 ′ and a third inner side surface 351 ′ c of the third insulating layer 351 ′ may be positioned so as not to be aligned to each other, when viewed in a plan view.
  • side surfaces of the second and third insulating layers 331 ′ and 351 ′ may be positioned to be offset in a plan view.
  • the second inner side surface 331 ′ c may be closer to the semiconductor chip 5 than the third inner side surface 351 ′ c .
  • An area of the third top surface 351 ′ b of the third insulating layer 351 ′ may be smaller than an area of the second top surface 331 ′ b of the second insulating layer 331 ′.
  • a portion 331 ′ b ′ of the second top surface 331 ′b of the second insulating layer 331 ′ may be exposed by the third insulating layer 351 ′.
  • FIG. 12 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • an outer side surface 3 a of the stack 3 may not be covered with the mold layer 4 .
  • the outer side surface 3 a of the stack 3 may be exposed to the outside.
  • FIG. 13 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • the stack 3 and the upper package 9 may be connected to each other, without the upper re-distribution layer therebetween.
  • the second terminal 315 may be in contact with the upper ball 23 .
  • the second terminal 315 may be electrically connected to the upper package 9 through the upper ball 23 .
  • FIG. 14 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • a top surface 4 b of the mold layer 4 may be substantially coplanar with a top surface 51 ′ of the semiconductor chip 5 .
  • the top surface 51 ′ of the semiconductor chip 5 may be exposed.
  • a chip-last process may be applied to fabricate a package structure including a re-distribution layer, and it may be beneficial to form the re-distribution layer and a semiconductor chip through separate respective processes.
  • a method of fabricating a semiconductor package it may be beneficial to reduce a size of a via, technical restrictions in constructing a path of the via, and a total volume of a semiconductor package.

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Abstract

A semiconductor package may include a lower re-distribution layer, a stack bonded to a portion of the lower re-distribution layer, a semiconductor chip on a top surface of the lower re-distribution layer, and an upper re-distribution layer on the semiconductor chip and the stack.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This U.S. non-provisional patent application is a divisional of U.S. patent application Ser. No. 16/415,272, filed May 17, 2019, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0119094, filed on Oct. 5, 2018, in the Korean Intellectual Property Office, the entire contents of both of these applications hereby being incorporated by reference.
    • BACKGROUND OF THE INVENTION
  • The present disclosure relates to a semiconductor package, and in particular, to a semiconductor package including a re-distribution layer.
  • In the case where an integrated circuit (IC) chip is provided in the form of a semiconductor package, it can be easily used as a part of an electronic product. In general, the semiconductor package includes a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and is electrically connected to the PCB by bonding wires or bumps.
  • With the recent advance in electronic industry, there is an increasing demand for high-performance, high-speed and compact electronic systems. Various semiconductor package techniques are being used to meet such a demand. For example, a semiconductor package device may include a plurality of semiconductor chips mounted on a package substrate or a semiconductor device package may be stacked on another package to meet such a demand.
    • SUMMARY
  • Some embodiments of the inventive concept provide a method of fabricating a semiconductor package with a re-distribution layer, using a chip-last process.
  • Some embodiments of the inventive concept provide a method capable of reducing a size of vias in a semiconductor package.
  • According to some embodiments of the inventive concept, a semiconductor package may include a lower re-distribution layer, a stack provided on a first region of a top surface of the lower re-distribution layer, a semiconductor chip provided on a second region of the top surface of the lower re-distribution layer, and an upper re-distribution layer on the semiconductor chip and the stack. The upper re-distribution layer may be electrically connected to the lower re-distribution layer via the stack.
  • According to some embodiments of the inventive concept, a method of fabricating a semiconductor package may include forming a lower re-distribution layer, forming a stack, bonding the stack to a portion of the lower re-distribution layer, stacking a semiconductor chip on a top surface of the lower re-distribution layer after bonding the stack, and forming an upper re-distribution layer on the semiconductor chip and the stack.
  • According to some embodiments of the inventive concept, a method of fabricating a re-distribution structure may include forming a lower re-distribution layer, forming a stack, and bonding the stack to a top surface of the lower re-distribution layer. The stack may include a first insulating layer disposed on the top surface of the lower re-distribution layer, a second insulating layer disposed on a top surface of the first insulating layer, a first via penetrating the first insulating layer, and a second via penetrating the second insulating layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.
  • FIG. 1 is a flow chart illustrating a method of fabricating a semiconductor device, according to an embodiment of the inventive concept.
  • FIG. 2 is a sectional view illustrating a first carrier substrate according to an embodiment of the inventive concept.
  • FIG. 3 is a sectional view illustrating a step of forming a lower re-distribution layer, according to the flow chart of FIG. 1.
  • FIGS. 4A to 4C are sectional views illustrating steps of forming stack structures, according to the flow chart of FIG. 1.
  • FIG. 5 is a sectional view illustrating a step of bonding a stack to a lower re-distribution layer, according to the flow chart of FIG. 1.
  • FIG. 6 is a sectional view illustrating a step of stacking a semiconductor chip, according to the flow chart of FIG. 1.
  • FIG. 7 is a sectional view illustrating a molding step, according to the flow chart of FIG. 1.
  • FIG. 8 is a sectional view illustrating a step of forming an upper re-distribution layer, according to the flow chart of FIG. 1.
  • FIG. 9 is a sectional view illustrating a step of removing the first carrier substrate, according to an embodiment of the inventive concept.
  • FIG. 10A is a sectional view illustrating a step of stacking an upper package, according to the flow chart of FIG. 1.
  • FIG. 10B is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 11 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 12 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 13 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • FIG. 14 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
    •
  • It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.
    • DETAILED DESCRIPTION
  • Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
  • FIG. 1 is a flow chart illustrating a method of fabricating a semiconductor package, and FIGS. 2 to 9 are sectional views illustrating a process of fabricating a semiconductor package, according to the flow chart of FIG. 1.
  • Hereinafter, a direction D1 of FIG. 2 will be referred to as a first or upward direction and a direction D2 will be referred to as a second or rightward direction.
  • Referring to FIG. 1, a method S of fabricating a semiconductor package may include forming a lower re-distribution layer (in 51), forming a stack (in S1′), bonding the stack to the lower re-distribution layer (in S2), stacking a semiconductor chip (in S3), performing a molding process (in S4), forming an upper re-distribution layer (in S5), and stacking an upper package (in S6).
  • Referring to FIGS. 1 and 2, a first carrier substrate 8 may be provided for the forming of the lower re-distribution layer (in S1). Referring to FIG. 3, a lower re-distribution layer 1 may be formed on a top surface of the first carrier substrate 8. In an embodiment, the lower re-distribution layer 1 may be formed by depositing or coating a photosensitive material on the first carrier substrate 8, forming holes in the photosensitive material by an exposure and develop process, and filling the holes with a conductive material.
  • The lower re-distribution layer 1 may include a lower redistribution insulator 11, a lower redistribution outer terminal 131, a lower redistribution pattern 133, a lower redistribution connection terminal 135, and a lower redistribution via 15. A lower redistribution hole 17 may be provided in a bottom surface of the lower redistribution insulator 11. For example, the lower redistribution layer 1 may be a layer configured to redistribute in/out pads of a semiconductor chip into different spatial positions and/or shapes, e.g., into a wider distribution than the original one on the semiconductor chip and/or into bigger pads than the original ones formed on the semiconductor chip. In certain embodiments, the lower redistribution layer 1 may electrically connect two or more pads formed on the semiconductor chip.
  • The lower redistribution insulator 11 may include a photosensitive material. In an embodiment, the photosensitive material may include a photosensitive polymer. The photosensitive polymer may include at least one of photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, benzocyclobutene (BCB) polymer, or a photo imageable dielectric (PID) material. However, the inventive concept is not limited to the example materials for the lower redistribution insulator 11. The lower redistribution insulator 11 may be used as a main body of the lower re-distribution layer 1. The lower redistribution insulator 11 may protect the lower redistribution pattern 133. The lower redistribution insulator 11 may have a multi-layered structure.
  • In an embodiment, a plurality of the lower redistribution patterns 133 may be provided in the first and second directions D1 and D2. The lower redistribution patterns 133, which are spaced apart from each other in the first direction D1, may be provided to form a plurality of layers, e.g., a plurality of layers of lower redistribution patterns 133. For example, the lower redistribution patterns 133 may be spaced apart from each other in the second direction D2 as shown in FIG. 3.
  • The lower redistribution via 15 may be used to electrically connect the lower redistribution patterns 133, which are spaced apart from each other in the first direction D1, to each other. In the present specification, the expression “electrically connect elements” may mean a direct connection between the elements or an indirect connection between the elements through another conductive element. The lower redistribution via 15 may have an increasing width in a direction along the first direction D1, e.g., in a cross-sectional view. However, the inventive concept is not limited to this example, and in an embodiment, the width of the lower redistribution via 15 may be constant in the first direction D1 or may vary in various other manners.
  • The lower redistribution outer terminal 131 may be placed on a first region of a top surface of the lower redistribution insulator 11. The first region may be an edge region of the top surface of the lower redistribution insulator 11. In an embodiment, the lower redistribution outer terminal 131 may be a pad. For example, the lower redistribution outer terminal 131 may be a contact pad configured to be electrically connected to (e.g., contact) a solder ball. In an embodiment, a plurality of the lower redistribution outer terminals 131 may be provided. The lower redistribution outer terminal 131 may be used to electrically connect at least one of the lower redistribution patterns 133 to integrated circuits (not shown) of a semiconductor chip 5 (e.g., see FIG. 9).
  • The lower redistribution connection terminal 135 may be placed on a second region of the top surface of the lower redistribution insulator 11. The second region may be a center region of the top surface of the lower redistribution insulator 11. For example, the second region may be positioned within a region enclosed by the first region, e.g., in a plan view. For example, the first region may be closer to the side surface of the lower redistribution insulator 11 than the second region. In an embodiment, the lower redistribution connection terminal 135 may be a pad. For example, the lower redistribution connection terminal 135 may be a contact pad configured to be electrically connected to (e.g., contact) a solder ball. In an embodiment, a plurality of the lower redistribution connection terminals 135 may be provided. The lower redistribution connection terminal 135 may be used to electrically connect at least one of the lower redistribution patterns 133 to a stack 3 (e.g., see FIG. 9).
  • Each of the lower redistribution outer terminal 131, the lower redistribution pattern 133, the lower redistribution connection terminal 135, and the lower redistribution via 15 may be formed of or include a conductive material. In an embodiment, the conductive material may include metallic materials such as copper or aluminum. The lower redistribution hole 17 may be formed in a bottom surface of the lower re-distribution layer 1 to have a specific depth in the first direction D1, thereby exposing at least one of the lower redistribution patterns 133.
  • Referring to FIGS. 1 and 4A, a stack 3 may be formed on a top surface of a second carrier substrate 8′ during the forming of the stack (in S1′). The stack 3 may include a first via 331, a second via 333, a first terminal 311, a first interconnection line 313, a second terminal 315, a first insulator 351, and a second insulator 353. The first insulator 351 may be placed on the second insulator 353. The first via 331 may be provided to penetrate the first insulator 351. The second via 333 may be provided to penetrate the second insulator 353. The first via 331 and the second via 333 may be electrically connected to each other through the first interconnection line 313. The first terminal 311 may be connected to the first via 331. For example, the stack 3 may be a stack of insulators and conductor patterns (e.g., conductor lines and/or contact vias).
  • In an embodiment, the first via 331 and the second via 333 may be off-centered from each other, when viewed in a plan view. For example, a vertically extending central axis Cl extending along a geometric center of the first via 331 may be spaced apart from a vertically extending central axis C2 extending along a geometric center of the second via 333. The first and second vias 331 and 333, which are off-centered from each other, may be connected to each other by the first interconnection line 313. This off-centered structure of the first and second vias 331 and 333 may be beneficial to electrically connect offset contact pads respectively formed on the first redistribution layer 1 and a second redistribution layer 7 which will be described below.
  • The stack 3 may be formed by depositing or coating a photosensitive material, forming holes in the photosensitive material by an exposure and develop process, and filling the holes with a conductive material. However, the inventive concept is not limited to this example, and the stack 3 may be formed by other methods.
  • At least one of the first insulator 351 and the second insulator 353 may include a photosensitive material. In an embodiment, the photosensitive material may include a photosensitive polymer. The photosensitive polymer may include at least one of photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenolic polymer, benzocyclobutene (BCB) polymer, or a photo imageable dielectric (PID) material. However, the inventive concept is not limited to the example materials for the photosensitive material.
  • The first via 331, the second via 333, the first interconnection line 313, the second terminal 315, and the first terminal 311 may be formed of or include at least one conductive material. In an embodiment, the conductive material may include aluminum or copper, but the inventive concept is not limited thereto.
  • Referring to FIG. 4B, the stack 3 may be vertically inverted on the second carrier substrate 8′. As a result of the vertical inversion of the stack 3, the first terminal 311 may be exposed upwardly.
  • Referring to FIG. 4C, a connection ball 24 may be formed on the first terminal 311. In an embodiment, the connection ball 24 may be a solder ball, but the inventive concept is not limited thereto.
  • The order of forming the lower re-distribution layer (in Si) and the stack (in Si′) in FIG. 1 may be changed. For example, the forming of the lower re-distribution layer (in Si) may be performed before the forming of the stack (in Si′), or the forming of the stack (in Si′) may be performed before the forming of the lower re-distribution layer (in Si). Alternatively, the forming of the lower re-distribution layer (in Si) and the forming of the stack (in Si′) may be performed at the same time. For example, the lower redistribution layer 1 and the stack 3 may be formed at the same time from different manufacturing apparatuses, and then may be combined as shown in FIG. 5.
  • Referring to FIGS. 1 and 5, the bonding of the stack 3 to the lower re-distribution layer (in S2) may include boding the stack 3 on the lower re-distribution layer 1. For example, the stack 3 of FIG. 3B may be inverted in such a way that the connection ball 24 is in contact with the lower redistribution outer terminal 131 of the lower re-distribution layer 1. When the connection ball 24 is disposed on a top surface of the lower redistribution outer terminal 131, a bonding process may be performed. The bonding process may be a reflow process or a thermo-compression process, but the inventive concept is not limited thereto. The connection ball 24 and the lower redistribution outer terminal 131 may be bonded to each other by the bonding process. The second terminal 315, the second via 333, the first interconnection line 313, the first via 331, the first terminal 311, and the connection ball 24 may be electrically connected to the lower redistribution pattern 133 through the lower redistribution outer terminal 131. The stack 3 and the lower re-distribution layer 1 bonded to each other may be referred to as a re-distribution structure. In an embodiment, in the case where the lower redistribution insulator 11 is a multi-layered structure, the first insulator 351 may be thicker than one of the layers constituting the lower redistribution insulator 11. In an embodiment, the first via 331 may have a decreasing or constant width in a direction from the top surface of the first insulator 351 toward the lower re-distribution layer 1, e.g., in a cross-sectional view. The second via 333 may have a decreasing or constant width in a direction from a top surface of the second insulating layer 353 toward the first insulator 351, e.g., in a cross-sectional view.
  • Referring to FIGS. 1 and 6, the stacking of the semiconductor chip (in S3) may include stacking a semiconductor chip 5 on a top surface of the lower re-distribution layer 1. The semiconductor chip 5 may include at least one of a memory chip, a logic chip, or a combination thereof. The semiconductor chip 5 may be electrically connected to the lower redistribution connection terminal 135 of the lower re-distribution layer 1 via an intermediate ball 22. Thus, the semiconductor chip 5 may be electrically connected to the lower redistribution pattern 133. The semiconductor chip 5 may be provided in such a way that a bottom surface 53 thereof faces the top surface of the lower re-distribution layer 1. The intermediate ball 22 may be a solder ball, but the inventive concept is not limited thereto.
  • When the semiconductor chip 5 is stacked on the top surface of the lower re-distribution layer 1 with the intermediate ball 22 interposed therebetween, the bonding process may be performed. During the bonding process, the intermediate ball 22 may reflow to bond the lower redistribution pad 135 to the semiconductor chip 5. During the bonding process, heat and pressure may be applied to the intermediate ball 22 so that the intermediate ball 22 may be bonded to the semiconductor chip 5. For example, the bonding process may be a reflow process or a thermo-compression process, but the inventive concept is not limited thereto. The intermediate ball 22 and the lower redistribution connection terminal 135 may be bonded to each other by the bonding process.
  • Referring to FIGS. 1 and 7, the molding process (in S4) may include forming a mold layer 4 to cover at least one of surfaces of the semiconductor chip 5. The mold layer 4 may protect the semiconductor chip 5 from external attack. For example, owing to the mold layer 4, the semiconductor chip 5 may be protected from external heat, moisture, and/or impact. The mold layer 4 may be configured to exhaust (e.g., release) heat, which is generated from the semiconductor chip 5, the lower re-distribution layer 1, and/or the stack 3, to the outside. In an embodiment, the mold layer 4 may cover a top surface 51 of the semiconductor chip 5. In an embodiment, the mold layer 4 may cover an outer side surface (not shown) of the stack 3. The mold layer 4 may be provided to fill a gap region between a side surface of the semiconductor chip 5 and a first inner side surface 351 c and/or a second inner side surface 353 c of the stack 3. For example, the side surface of the semiconductor chip 5 is parallel to the first and second inner side surfaces 351 c and 353 c of respective first and second insulators of the stack 3. An underfill layer may be further provided around the lower redistribution connection terminal 135. In an embodiment, the mold layer 4 may be formed of or include an epoxy molding compound (EMC) material. For example, the mold layer may be formed of a different material from the first and second insulators 351 and 353 of the stack 3. The molding process may include placing the lower re-distribution layer 1, on which the semiconductor chip 5 and the stack 3 are stacked, in a mold and then injecting a material for the mold layer 4 into the mold. In an embodiment, the mold layer 4 may include an Ajinomoto build-up film (ABF). However, the inventive concept is not limited thereto, and other insulator may be used for the mold layer 4.
  • Referring to FIGS. 1 and 8, the forming of the upper re-distribution layer (in S5) may include forming an upper re-distribution layer 7 on the top surface of the mold layer 4 and/or on a top portion of the stack 3, after the molding process. In an embodiment, the upper re-distribution layer 7 may be formed by depositing or coating a photosensitive material on the top surface of the mold layer 4 and/or the top portion of the stack 3, forming holes in the photosensitive material by an exposure and develop process, and filling the holes with a conductive material. The upper re-distribution layer 7 may include a first upper redistribution insulating layer 711, a second upper redistribution insulating layer 713, an upper redistribution pattern 731, a first upper redistribution via 751, a second upper redistribution via 753, and an upper redistribution terminal 733. For example, the upper redistribution layer 7 may be a layer configured to redistribute in/out pads of a semiconductor chip into different spatial positions and/or shapes, e.g., into a wider distribution than the original one formed on the semiconductor chip and/or into bigger pads than the original ones formed on the semiconductor chip. In certain embodiments, the upper redistribution layer 7 may electrically connect two or more pads formed on the semiconductor chip.
  • The first upper redistribution insulating layer 711 may be provided on the mold layer 4 and the stack 3. For example, the first upper redistribution insulating layer 711 may contact the mold layer 4 and the stack 3, e.g., the second terminal 315 and/or an insulating layer of the stack 3. The second upper redistribution insulating layer 713 may be provided on the first upper redistribution insulating layer 711. The first upper redistribution insulating layer 711 and the second upper redistribution insulating layer 713 may include a photosensitive material. In an embodiment, the photosensitive material may include a photo imageable dielectric (PID) material. However, the inventive concept is not limited to this photosensitive material. The first upper redistribution insulating layer 711 and the second upper redistribution insulating layer 713 may protect the upper redistribution pattern 731, the first upper redistribution via 751, and the second upper redistribution via 753.
  • The first upper redistribution via 751 may be provided to penetrate the first upper redistribution insulating layer 711. In an embodiment, a plurality of the first upper redistribution vias 751 may be arranged in the second direction D2. At least one of the first upper redistribution vias 751 may be electrically connected to the upper redistribution terminal 733.
  • The upper redistribution pattern 731 may be provided on the first upper redistribution via 751. In an embodiment, a plurality of the upper redistribution patterns 731 may be provided. At least one of the upper redistribution patterns 731 may extend in the second direction D2. The upper redistribution pattern 731 may be electrically connected to the first upper redistribution via 751.
  • The second upper redistribution via 753 may be provided to penetrate the second upper redistribution insulating layer 713. In an embodiment, a plurality of the second upper redistribution vias 753 may be arranged in the second direction D2. The second upper redistribution vias 753 may be electrically connected to the upper redistribution pattern 731.
  • The upper redistribution terminal 733 may be provided on the second upper redistribution via 753. In an embodiment, a plurality of the upper redistribution terminals 733 may be provided. The upper redistribution terminal 733 may be electrically connected to the second upper redistribution via 753. In an embodiment, the upper redistribution terminal 733 may be a pad. For example, the upper redistribution terminal 733 may be a contact pad configured to be electrically connected to (e.g., contact) a solder ball.
  • Each of the upper redistribution pattern 731, the first upper redistribution via 751, the second upper redistribution via 753, and the upper redistribution terminal 733 may be formed of or include a conductive material. In an embodiment, the conductive material may include metallic materials such as copper or aluminum.
  • Since the upper re-distribution layer 7 is provided on the semiconductor chip 5, terminals of an upper package 9 (e.g., see FIG. 10A) may be freely disposed. For example, the upper re-distribution layer 7 may reduce difficulty/restriction in designing the upper package 9.
  • Referring to FIG. 9, the first carrier substrate 8 may be removed from the bottom surface of the lower re-distribution layer 1. After the removal of the first carrier substrate 8, lower balls 21 may be formed on the lower redistribution patterns 133 exposed by the lower redistribution hole 17. The lower redistribution patterns 133 may be electrically connected to another package or board through the lower balls 21.
  • Referring to FIGS. 1 and 10A, the stacking of the upper package (in S6) may include stacking the upper package 9 on the upper re-distribution layer 7. The upper package 9 may include an upper substrate 91, an upper semiconductor chip 93, an upper mold layer 95, an upper wire 97, and so forth. The upper package 9 and the upper redistribution terminal 733 may be electrically connected to each other through upper balls 23. The upper balls 23 may be solder balls, but the inventive concept is not limited thereto. The upper ball 23 and the upper redistribution terminal 733 may be bonded to each other, e.g., by a bonding process. The bonding process may be a reflow process or a thermo-compression process. However, the bonding process according to the inventive concept is not limited to the reflow process or a thermo-compression process. The upper semiconductor chip 93 may be electrically connected to the upper wire 97, the upper substrate 91, and the upper ball 23. Thus, the upper package 9 may be electrically connected to the lower re-distribution layer 1 through the upper re-distribution layer 7 and the stack 3.
  • FIG. 10B is a plan view of a semiconductor package according to an embodiment illustrated in FIG. 10A. FIG. 10A is a sectional view taken along a line I-I′ of FIG. 10B.
  • Referring to FIG. 10B, the semiconductor package may be configured in such a way that an area of the semiconductor chip 5 is smaller than an area enclosed by an outer line of the stack 3, when viewed in a plan view. The semiconductor chip 5 may be located inside the stack 3, when viewed in a plan view. FIG. 10B illustrates an example, in which a boundary of the stack 3 is located outside a boundary of the semiconductor chip 5 in all directions, but the inventive concept is not limited thereto. For example, the boundary of the stack 3 may be located outside the boundary of the semiconductor chip 5 in the second direction D2, but the boundary of the semiconductor chip 5 may coincide with the boundary of the stack 3 in a third direction, which is perpendicular to the first and second directions D1 and D2.
  • In an embodiment, an area of the lower re-distribution layer 1 may be larger than an area of the stack 3, e.g., an area enclosed by an outer line of the stack 3 when viewed in a plan view. However, the inventive concept is not limited thereto, and the area enclosed by an outer line of the stack 3 may be substantially equal to the area of the lower re-distribution layer 1.
  • In a method of fabricating a semiconductor package according to an example embodiment of the inventive concept, the lower re-distribution layer and the stack may be formed in advance and then the semiconductor chip may be stacked thereon. This may be beneficial to use the lower re-distribution layer, the stack, and the semiconductor chip, which have been qualified as good products, for the semiconductor package, and consequently to improve a total production yield of the semiconductor package. Furthermore, the lower re-distribution layer and the stack may be formed by an independent process, which may be performed concurrently with the formation of the semiconductor chip. Accordingly, it may be beneficial to reduce a total process time for fabricating the semiconductor package.
  • In a semiconductor package according to an example embodiment of the inventive concept, since the upper re-distribution layer is provided, it may be beneficial to reduce technical restrictions in disposing the connection terminals of the lower re-distribution layer and/or the stack and in designing an overall structure of the semiconductor package. For example, the upper redistribution layer rearrange in/out contact pads of a semiconductor device disposed on the upper redistribution layer to fit with contact pads of the lower redistribution layer and/or the stack structure.
  • In a semiconductor package according to an example embodiment of the inventive concept, since deposition, coating, exposure, and develop processes are used to form the stack, it may be beneficial to reduce a size of a via hole. For example, a photolithography process may be beneficial to form a reduced size of a via hole. Thus, an overall size of the semiconductor package may be decreased. Furthermore, it may be beneficial to reduce technical restrictions associated with a height of the stack and with a size of a semiconductor chip allowed for the semiconductor package. For example, various embodiments of the present disclosure may be beneficial to stack multiple semiconductor chips in a semiconductor package.
  • In a semiconductor package according to an example embodiment of the inventive concept, the vias may be arranged to form various paths in the stack. Thus, it may be beneficial to reduce technical restrictions in disposing the connection terminals of the lower re-distribution layer, the upper re-distribution layer, and/or the upper package and in designing an overall structure of the semiconductor package.
  • FIG. 11 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • In the following description, for concise description, a similar element to or the same element as that of the previously embodiments will be identified by the same reference number as that of the previously embodiment, without repeating an overlapping description thereof
  • Referring to FIG. 11, the stack 3 may include a first insulating layer 311′, a second insulating layer 331′, a third insulating layer 351′, a first via 315′, a second via 335′, a third via 355′, a first interconnection line 313′, a second interconnection line 333′, an upper terminal 353′, and a connection terminal 303.
  • The first insulating layer 311′ may be placed on the top surface of the lower re-distribution layer 1. For example, the first insulating layer 311′ may be disposed on the top surface of the lower redistribution layer 1 with an underfill layer and the connection ball 24 therebetween. The first via 315′ may be provided to penetrate the first insulating layer 311′. The first interconnection line 313′ may be provided on a first top surface 311′b of the first insulating layer 311′. The first interconnection line 313′ may be connected to (e.g., contact) the first via 315′.
  • The second insulating layer 331′ may be placed on the first top surface 311′b of the first insulating layer 311′. The second via 335′ may be provided to penetrate the second insulating layer 331′. The second via 335′ may be connected to (e.g., contact) the first interconnection line 313′. The second via 335′ may be electrically connected to the first via 315′ through the first interconnection line 313′. The second interconnection line 333′ may be placed on a second top surface 331′b of the second insulating layer 331′. The second interconnection line 333′ may be connected to (e.g., contact) the second via 335′.
  • In an embodiment, the first insulating layer 311′ and the second insulating layer 331′ may form a staircase structure in a direction toward the semiconductor chip 5. For example, the first and second insulating layers 311′ and 331′ of the stack 3 may have a step structure in a side facing the semiconductor chip 5. For example, a first inner side surface 311′c of the first insulating layer 311′ may be positioned so as not to be aligned to a second inner side surface 331′c of the second insulating layer 331′, when viewed in a plan view. For example, side surfaces of the first and second insulating layers 311′ and 331′ may be positioned to be offset in a plan view. The first inner side surface 311′c may be closer to the semiconductor chip 5 than the second inner side surface 331′c. An area of the second top surface 331′b of the second insulating layer 331′ may be smaller than an area of the first top surface 311′b of the first insulating layer 311′. While the second insulating layer 331′ is placed on the first insulating layer 311′, a portion 311′b′ of the first top surface 311′b of the first insulating layer 311′ may be exposed by the second insulating layer 331′.
  • The third insulating layer 351′ may be placed on the second top surface 331′b of the second insulating layer 331′. The third via 355′ may be provided to penetrate the third insulating layer 351′. The third via 355′ may be connected to (e.g., contact) the second interconnection line 333′. The third via 355′ may be electrically connected to the second via 335′ through the second interconnection line 333′. The upper terminal 353′ may be provided on a third top surface of the third insulating layer 351′. The upper terminal 353′ may be connected to (e.g., contact) the third via 355′.
  • In an embodiment, the second insulating layer 331′ and the third insulating layer 351′ may form a staircase structure in a direction toward the semiconductor chip 5. For example, the second and third insulating layers 331′ and 351′ of the stack 3 may have a step structure in a side facing the semiconductor chip 5. For example, the second inner side surface 331′c of the second insulating layer 331′ and a third inner side surface 351′c of the third insulating layer 351′ may be positioned so as not to be aligned to each other, when viewed in a plan view. For example, side surfaces of the second and third insulating layers 331′ and 351′ may be positioned to be offset in a plan view. The second inner side surface 331′c may be closer to the semiconductor chip 5 than the third inner side surface 351′c. An area of the third top surface 351′b of the third insulating layer 351′ may be smaller than an area of the second top surface 331′b of the second insulating layer 331′. While the third insulating layer 351′ is placed on the second insulating layer 331′, a portion 331′b′ of the second top surface 331′b of the second insulating layer 331′ may be exposed by the third insulating layer 351′.
  • FIG. 12 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • In the following description, for concise description, a similar element to or the same element as that of the previously embodiments will be identified by the same reference number as that of the previously embodiments, without repeating an overlapping description thereof.
  • Referring to FIG. 12, an outer side surface 3 a of the stack 3 may not be covered with the mold layer 4. For example, the outer side surface 3 a of the stack 3 may be exposed to the outside.
  • FIG. 13 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • In the following description, for concise description, a similar element to or the same element as that of the previously embodiments will be identified by the same reference number as that of the previously embodiments, without repeating an overlapping description thereof.
  • Referring to FIG. 13, the stack 3 and the upper package 9 may be connected to each other, without the upper re-distribution layer therebetween. The second terminal 315 may be in contact with the upper ball 23. The second terminal 315 may be electrically connected to the upper package 9 through the upper ball 23.
  • FIG. 14 is a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.
  • In the following description, for concise description, a similar element to or the same element as that of the previously embodiments will be identified by the same reference number as that of the previously embodiments, without repeating an overlapping description thereof.
  • Referring to FIG. 14, a top surface 4 b of the mold layer 4 may be substantially coplanar with a top surface 51′ of the semiconductor chip 5. Thus, even after the molding process forming the mold layer 4, the top surface 51′ of the semiconductor chip 5 may be exposed.
  • In a method of fabricating a semiconductor package according to an embodiment of the inventive concept, a chip-last process may be applied to fabricate a package structure including a re-distribution layer, and it may be beneficial to form the re-distribution layer and a semiconductor chip through separate respective processes.
  • In a method of fabricating a semiconductor package according to an embodiment of the inventive concept, it may be beneficial to reduce a fabrication time and to improve a production yield.
  • In a method of fabricating a semiconductor package according to an embodiment of the inventive concept, it may be beneficial to reduce a size of a via, technical restrictions in constructing a path of the via, and a total volume of a semiconductor package.
  • While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.

Claims (20)

What is claimed is:
1. A semiconductor package, comprising:
a lower re-distribution layer;
a stack provided on a first region of a top surface of the lower re-distribution layer;
a semiconductor chip provided on a second region of the top surface of the lower re-distribution layer; and
an upper re-distribution layer on the semiconductor chip and the stack,
wherein the upper re-distribution layer is electrically connected to the lower re-distribution layer via the stack.
2. The semiconductor package of claim 1, wherein the lower re-distribution layer and the stack are electrically connected to each other via a connection ball.
3. The semiconductor package of claim 1, wherein the stack comprises:
a first insulating layer disposed on the top surface of the lower re-distribution layer;
a second insulating layer disposed on a top surface of the first insulating layer;
a first via penetrating the first insulating layer;
a second via penetrating the second insulating layer; and
a first interconnection line electrically connecting the first via to the second via.
4. The semiconductor package of claim 3, wherein a vertically extending central axis of the second via is spaced apart from a vertically extending central axis of the first via.
5. The semiconductor package of claim 3,
wherein the lower re-distribution layer comprises a lower redistribution insulator, and
wherein the lower redistribution insulator, the first insulating layer, and the second insulating layer comprise a photo imageable dielectric (PID) material.
6. The semiconductor package of claim 5, further comprising:
a mold layer provided to enclose an outer side surface of the stack and the semiconductor chip; and
an underfill layer interposed between the lower re-distribution layer and the stack,
wherein the mold layer comprises a material different from the PID material.
7. The semiconductor package of claim 3, wherein the first insulating layer and the second insulating layer are provided to form a step structure in a side facing the semiconductor chip.
8. The semiconductor package of claim 3, wherein the first via has an upwardly increasing width.
9. The semiconductor package of claim 2, wherein the lower re-distribution layer and the semiconductor chip are electrically connected to each other via an intermediate ball.
10. The semiconductor package of claim 9, further comprising:
an underfill layer on the lower re-distribution layer,
wherein the underfill layer is disposed beneath the stack and the semiconductor chip.
11. The semiconductor package of claim 10, wherein the underfill layer surrounds the connection ball and the intermediate ball.
12. A semiconductor package, comprising:
a lower re-distribution layer;
a stack on the lower re-distribution layer;
a semiconductor chip on the lower re-distribution layer; and
a connection ball between the lower re-distribution layer and the stack,
wherein the stack and the semiconductor chip are horizontally spaced apart from each other, and
wherein the stack comprises:
a first insulating layer;
a second insulating layer on the first insulating layer;
a first via penetrating the first insulating layer; and
a second via penetrating the second insulating layer.
13. The semiconductor package of claim 12, further comprising:
an upper re-distribution layer on the semiconductor chip and the stack,
wherein the upper re-distribution layer is electrically connected to the lower re-distribution layer via the stack.
14. The semiconductor package of claim 12, wherein a vertically extending central axis of the second via is spaced apart from a vertically extending central axis of the first via.
15. The semiconductor package of claim 12, wherein the first insulating layer and the second insulating layer comprise a photo imageable dielectric (PID) material.
16. The semiconductor package of claim 12, wherein the first via has an upwardly increasing width.
17. The semiconductor package of claim 12, wherein the lower re-distribution layer and the semiconductor chip are electrically connected to each other via an intermediate ball.
18. The semiconductor package of claim 17, further comprising:
an underfill layer on the lower re-distribution layer; and
a mold layer provided to enclose a side surface of the semiconductor chip,
wherein an upper surface of the underfill layer contacts a bottom surface of the molding layer.
19. The semiconductor package of claim 12, wherein the stack comprises:
a third insulating layer on the second insulating layer; and
a third via penetrating the third insulating layer.
20. The semiconductor package of claim 19, wherein the first insulating layer and the second insulating layer are provided to form a step structure in a side facing the semiconductor chip.
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