TWI566356B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

Info

Publication number
TWI566356B
TWI566356B TW104133820A TW104133820A TWI566356B TW I566356 B TWI566356 B TW I566356B TW 104133820 A TW104133820 A TW 104133820A TW 104133820 A TW104133820 A TW 104133820A TW I566356 B TWI566356 B TW I566356B
Authority
TW
Taiwan
Prior art keywords
pad
die
package structure
vertical
crystal grains
Prior art date
Application number
TW104133820A
Other languages
English (en)
Other versions
TW201714265A (zh
Inventor
袁家祥
張家維
林國鼎
莊詠程
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Priority to TW104133820A priority Critical patent/TWI566356B/zh
Priority to US14/970,558 priority patent/US9673178B2/en
Application granted granted Critical
Publication of TWI566356B publication Critical patent/TWI566356B/zh
Publication of TW201714265A publication Critical patent/TW201714265A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/065—Material
    • H01L2224/06505—Bonding areas having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts

Description

封裝結構及其製造方法
本發明是有關於一種半導體結構及其製造方法，且特別是有關於一種封裝結構及其製造方法。
近代電子設備大量依賴這些裝設有許多半導體晶粒或積體電路（Integrated Circuits，ICs）的電路板。在晶粒及基板之間的機械性及電性連接不斷地挑戰這些積體電路設計者。打線接合（wire bonding）是最常用來將積體電路及基板互連的技術之一。
圖1為習知的一種封裝結構的示意圖。此結構包括基板10、多晶粒堆疊結構12、多個第一銲墊14a~14h、垂直導線16a~16h以及第二銲墊18。多晶粒堆疊結構12包括由下至上垂直堆疊在基板10上的晶粒12a~12h，其中晶粒12a為底部晶粒，晶粒12h為頂部晶粒。第一銲墊14a~14h分別配置在對應的晶粒12a~12h的主動面上。垂直導線16a~16h分別配置在對應的第一銲墊14a~14h上。第二銲墊18配置在多晶粒堆疊結構12一側的基板10的表面上。
在形成垂直導線16a~16h的製程中，相較於底部晶粒12a，由於頂部晶粒12h距離第二銲墊18較遠，其所形成的垂直導線16h的長度亦大於垂直導線16a的長度。因此，當配置於頂部晶粒12h上的垂直導線16h愈高，其愈容易產生導線偏移（wire sweep）。為了避免較高的垂直導線16h被後續封膠模具所壓損，勢必要增加模穴（cavity）的深度，其導致研磨成本增加。
本發明提供一種封裝結構及其製造方法，其可減少垂直導線的長度，降低導線偏移的風險，以利後續模封製程，並降低研磨成本。
本發明提供一種封裝結構，包括：基板、N個晶粒、N個第一銲墊、N個垂直導線以及第二銲墊。N個晶粒相互堆疊在所述基板上，以形成多晶粒堆疊結構。所述N個晶粒包括由下至上的第一至第N晶粒，其中所述第一晶粒為底部晶粒，所述第N晶粒為頂部晶粒，N為大於1的整數。N個第一銲墊分別配置在所述晶粒的主動面上。N個垂直導線分別配置在所述第一銲墊上。第二銲墊配置在所述頂部晶粒上。
本發明提供一種封裝結構，包括：基板、多個第一晶粒、多個銲墊以及多個垂直導線。多個第一晶粒相互堆疊在所述基板上，以形成多晶粒堆疊結構。各所述第一晶粒具有第一區、第二區以及第三區，所述第二區配置於所述第一區與所述第三區之間，其中所述第一晶粒的所述第三區為切割道的一部分。多個銲墊分別配置在所述第一晶粒的所述第二區的主動面上。多個垂直導線分別配置在所述銲墊上。
本發明提供一種封裝結構的製造方法，其步驟如下。提供基板。形成多晶粒堆疊結構在所述基板上。所述多晶粒堆疊結構具有相互堆疊的N個晶粒。所述N個晶粒包括由下至上的第一至第N晶粒，其中所述第一晶粒為底部晶粒，所述第N晶粒為頂部晶粒，N為大於1的整數。分別形成N個第一銲墊在所述晶粒的主動面上。形成第二銲墊在所述頂部晶粒上。藉由垂直打線製程分別形成N個垂直導線在所述第一銲墊上。
基於上述，本發明藉由配置在頂部晶粒上的第二銲墊以及配置在任意晶粒上的至少一第三銲墊當作虛擬銲墊，以利於截線。如此一來，本發明便可減少所形成的垂直導線的長度，降低導線偏移的風險，以利後續模封製程並降低研磨成本。另外，本發明之第二銲墊以及第三銲墊還可保護其下方的晶粒，以承受多次的打線接合製程。此外，本發明還可藉由增加切割道寬度，將切割道的一部分當作虛擬銲墊，以利於截線。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖2為本發明之第一實施例的一種封裝結構的示意圖。
請參照圖2，本實施例之封裝結構包括：基板100、多晶粒堆疊結構102、多個第一銲墊104a~104h、多個垂直導線106a~106h以及第二銲墊108。多晶粒堆疊結構102包括多個晶粒102a~102h相互堆疊在基板100上。在一實施例中，基板100可例如是印刷電路板、矽基板或半導體基板。
晶粒102a~102h包括由下至上的第一晶粒102a至第八晶粒102h，其中第一晶粒102a可例如是底部晶粒，第八晶粒102h可例如是頂部晶粒。在一實施例中，多晶粒堆疊結構102可例如是階梯狀堆疊。在一實施例中，晶粒102a~102h可例如是具有相同功能（function）的晶粒或是具有不同功能的晶粒，但本發明不以此為限。雖然圖2中僅繪示8個晶粒、8個第一銲墊以及8個垂直導線，但本發明不以此為限，本發明之晶粒、第一銲墊以及垂直導線的數量可依照需求來進行調整。
第一銲墊104a~104h分別配置在晶粒102a~102h的主動面上。詳細地說，第一銲墊104a配置在晶粒102a的主動面上；第一銲墊104b配置在晶粒102b的主動面上，以此類推，於此便不再詳述。在一實施例中，第一銲墊104a~104h的材料包括金屬材料。所述金屬材料可例如是銅、鋁、金、銀、鎳、鈀或其組合。
垂直導線106a~106h分別配置在第一銲墊104a~104h上。詳細地說，垂直導線106a~106h包括由下至上的第一垂直導線106a至第八垂直導線106h。第一垂直導線106a配置在第一銲墊104a上；第二垂直導線106b配置在第一銲墊104b上，以此類推，於此便不再詳述。在一實施例中，垂直導線106a~106h的材料包括金屬材料。所述金屬材料可例如是銅、鋁、金、銀、鎳、鈀或其組合。在一實施例中，垂直導線106a~106h的材料與第一銲墊104a~104h的材料可以相同亦或不同。
值得注意的是，本實施例之第一垂直導線106a的長度大於第八垂直導線106h的長度。由於第一垂直導線106a配置在最下方的底部晶粒102a的第一銲墊104a上，而第八垂直導線106h配置在最上方的頂部晶粒102h的第一銲墊104h上。因此，相較於習知的垂直導線（如圖1所示），本實施例之垂直導線106a~106h的末端高度較為接近或一致。如此一來，本實施例之垂直導線106a~106h便不容易產生導線偏移，以利後續模封製程，並降低研磨成本。雖然圖2中所繪示垂直導線106a~106h的末端高度相同，但本發明不以此為限，垂直導線106a~106h彼此之間的末端高度亦可具有些許差異。
第二銲墊108配置在頂部晶粒102h上。在一實施例中，第二銲墊108的材料與第一銲墊104a~104h的材料不同。在一實施例中，第二銲墊108的材料包括矽材料、半導體材料、金屬材料、黏晶材料、絕緣材料、電阻材料或其組合。所述金屬材料可例如是銅、鋁、金、銀、鎳、鈀或其組合。所述黏晶材料可例如是晶粒貼附膠層（Die Attach Film，DAF）。所述絕緣材料可例如是聚醯亞胺（Polyimide，PI）。
圖3A至圖3C為圖2之封裝結構的製造流程示意圖。
請參照圖3A，本發明提供一種封裝結構的製造方法，其步驟如下。提供基板100。形成多晶粒堆疊結構102在基板100上。多晶粒堆疊結構102具有相互堆疊的多個晶粒102a~102h。晶粒102a~102h包括由下至上的第一晶粒102a至第八晶粒102h，其中第一晶粒102a可例如是底部晶粒，第八晶粒102h可例如是頂部晶粒。接著，分別形成第一銲墊104a~104h在晶粒102a~102h的主動面上。形成第二銲墊108在頂部晶粒102h上。之後，藉由垂直打線製程分別形成多個垂直導線106a~106h在第一銲墊104a~104h上。
詳細地說，以垂直導線106h為例，所述垂直打線製程的步驟如下。
請同時參照圖3A與圖3B，首先，藉由打線機200將垂直導線106h’的第一端E1接合在第一銲墊104h上。然後，藉由打線機200將垂直導線106h’的第二端E2拉至第二銲墊108上，並進行加壓。此時的垂直導線106h’的第二端E2具有些微形變，但並未被截斷。在本實施例中，第二銲墊108的材料與第一銲墊104a~104h的材料不同，上述垂直導線106h’與第二銲墊108以及第一銲墊104a~104h的附著力（adhesion）也不同。因此，垂直導線106h’的第一端E1可與第一銲墊104h接合，而垂直導線106h’的第二端E2不與第二銲墊108接合。在本實施例中，第二銲墊108可用以當作虛擬銲墊，以利於截線。
請同時參照圖3C，藉由打線機200將垂直導線106h’的第二端E2拉至遠離基板100的方向D1，以截斷垂直導線106h’。詳細地說，由於上述加壓，垂直導線106h’的第二端E2已經形變，再利用打線機200的拉力便可將垂直導線106h’截斷在第二端E2處。
值得注意的是，本實施例可藉由配置在頂部晶粒102h上的第二銲墊108當作虛擬銲墊，以利於截線。如此一來，本實施例便可減少所形成的垂直導線106a~106h的長度，降低導線偏移的風險，以利後續模封製程並降低研磨成本。另外，本發明之第二銲墊108還可保護其下方的頂部晶粒102h，以承受多次的打線接合製程。
在藉由垂直打線製程分別形成垂直導線106a~106h在第一銲墊104a~104h上之後，本實施例更包括進行模封製程，並將垂直導線106a~106h電性連接至重分佈層（Redistribution Layer，RDL）或封裝基板上，以形成一封裝結構（未繪示）。之後，再藉由凸塊或銲球與另一封裝結構（未繪示）電性連接。
圖4為本發明之第二實施例的一種封裝結構的示意圖。
請參照圖4，第二實施例的封裝結構與第一實施例的封裝結構基本上相似。上述兩者不同之處在於：第二實施例的封裝結構具有至少一第三銲墊110配置在晶粒102d上。第三銲墊110配置於晶粒102e的一側以及晶粒102d上的垂直導線106d之間。第三銲墊110亦可用以當作虛擬銲墊，以利於截線，並可保護其下方的晶粒102d，以承受多次的打線接合製程。雖然圖4中僅繪示一個第三銲墊110，但本發明不以此為限。在其他實施例中，其可包括一個或多個第三銲墊110分別配置在底部晶粒與頂部晶粒之間的任意晶粒上。在一實施例中，所述第三銲墊110的材料與第一銲墊104a~104h的材料不同。在一實施例中，第三銲墊110的材料包括矽材料、半導體材料、金屬材料、黏晶材料、絕緣材料、電阻材料或其組合。所述金屬材料可例如是銅、鋁、金、銀、鎳、鈀或其組合。所述黏晶材料可例如是晶粒貼附膠層（DAF）。所述絕緣材料可例如是聚醯亞胺（PI）。
圖5為本發明之第三實施例的一種封裝結構的示意圖。
請參照圖5，第三實施例的封裝結構與第一實施例的封裝結構基本上相似。上述兩者不同之處在於：第三實施例的封裝結構不具有配置在頂部晶粒102h上的第二銲墊108。詳細地說，第三實施例的晶粒102a~102h分別具有第一區R1、第二區R2以及第三區R3，第二區R2配置於第一區R1與第三區R3之間。上方晶粒可配置在下方晶粒的第一區上，以形成階梯狀堆疊。舉例來說，晶粒102b配置在晶粒102a的第一區R1上，以暴露出晶粒102a的第二區R2與第三區R3的表面，以此類推，於此便不再詳述。
值得注意的是，晶粒102a~102h的第三區R3可例如是切割道的一部分。由於第一銲墊104a~104h的材料與晶粒102a~102h的材料不同，第三實施例的垂直導線106a~106h與晶粒102a~102h以及第一銲墊104a~104h的附著力也不同。因此，第三實施例的晶粒102a~102h的第三區R3可用以當作虛擬銲墊，以利於截線。在一實施例中，晶粒102a~102h的材料可例如是矽材料、半導體材料、絕緣材料或其組合。在一實施例中，第三區R3的寬度可介於250 μm至500 μm之間。但本發明不以此為限，在其他實施例中，第三區R3的寬度亦可小於250 μm或大於500 μm。
圖6為本發明之第四實施例的一種封裝結構的示意圖。
請參照圖6，第四實施例的封裝結構與第一實施例的封裝結構基本上相似。上述兩者不同之處在於：第四實施例的封裝結構更包括晶粒208配置在晶粒102g以及晶粒102h之間。但本發明不以此為限，在其他實施例中，晶粒208可配置在任意相鄰的晶粒102a~102h之間或是晶粒（頂部晶粒）102h上。而配置在任意相鄰的晶粒102a~102h之間或是晶粒（頂部晶粒）102h上的晶粒208可用以當作虛擬銲墊，以利於截線。如此一來，本實施例便藉由不同高度的晶粒208來調整或控制垂直導線106a~106h的長度。在一實施例中，晶粒208的材料與第一銲墊104a~104h的材料不同。晶粒208的材料可例如是矽材料、半導體材料、絕緣材料或其組合。
綜上所述，本發明藉由配置在頂部晶粒上的第二銲墊以及配置在任意晶粒上的至少一第三銲墊當作虛擬銲墊，以利於截線。如此一來，本發明便可減少所形成的垂直導線的長度，降低導線偏移的風險，以利後續模封製程並降低研磨成本。另外，本發明之第二銲墊以及第三銲墊還可保護其下方的晶粒，以承受多次的打線接合製程。此外，本發明還可藉由增加切割道寬度，將切割道的一部分當作虛擬銲墊，以利於截線。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、100‧‧‧基板 12、102‧‧‧多晶粒堆疊結構 12a~12h、102a~102h、208‧‧‧晶粒 14a~14h、104a~104h‧‧‧第一銲墊 16a~16h、106a~106h、106h’‧‧‧垂直導線 18、108‧‧‧第二銲墊 110‧‧‧第三銲墊 200‧‧‧打線機 D1‧‧‧方向 E1‧‧‧第一端 E2‧‧‧第二端 R1‧‧‧第一區 R2‧‧‧第二區 R3‧‧‧第三區
圖1為習知的一種封裝結構的示意圖。 圖2為本發明之第一實施例的一種封裝結構的示意圖。 圖3A至圖3C為圖2之封裝結構的製造流程示意圖。 圖4為本發明之第二實施例的一種封裝結構的示意圖。 圖5為本發明之第三實施例的一種封裝結構的示意圖。 圖6為本發明之第四實施例的一種封裝結構的示意圖。
100‧‧‧基板
102‧‧‧多晶粒堆疊結構
102a~102h‧‧‧晶粒
104a~104h‧‧‧第一銲墊
106a~106h‧‧‧垂直導線
108‧‧‧第二銲墊

Claims (16)

  1. 一種封裝結構，包括：基板；N個晶粒，相互堆疊在所述基板上，以形成多晶粒堆疊結構，所述N個晶粒包括由下至上的第一至第N晶粒，其中所述第一晶粒為底部晶粒，所述第N晶粒為頂部晶粒，其中N為大於1的整數；N個第一銲墊，分別配置在所述晶粒的主動面上；N個垂直導線，分別配置在所述第一銲墊上；以及第二銲墊，配置在所述頂部晶粒上。
  2. 如申請專利範圍第1項所述的封裝結構，其中所述多晶粒堆疊結構為階梯狀堆疊。
  3. 如申請專利範圍第1項所述的封裝結構，更包括至少一第三銲墊配置在第i晶粒上，其中1<i<N，N為大於2的整數。
  4. 如申請專利範圍第3項所述的封裝結構，其中所述至少一第三銲墊配置於所述第i+1晶粒的一側以及所述第i晶粒上的所述垂直導線之間。
  5. 如申請專利範圍第3項所述的封裝結構，其中所述第一銲墊的材料與所述至少一第三銲墊的材料不同。
  6. 如申請專利範圍第3項所述的封裝結構，其中所述至少一第三銲墊的材料包括矽材料、半導體材料、金屬材料、黏晶材料、絕緣材料、電阻材料或其組合。
  7. 如申請專利範圍第1項所述的封裝結構，其中所述第一銲墊的材料與所述第二銲墊的材料不同。
  8. 如申請專利範圍第1項所述的封裝結構，其中所述第二銲墊的材料包括矽材料、半導體材料、金屬材料、黏晶材料、絕緣材料、電阻材料或其組合。
  9. 如申請專利範圍第1項所述的封裝結構，其中所述N個垂直導線包括由下至上的第一至第N垂直導線，其中所述第一垂直導線的長度大於所述第N垂直導線的長度。
  10. 如申請專利範圍第1項所述的封裝結構，其中所述第一銲墊的材料與所述晶粒的材料不同。
  11. 如申請專利範圍第1項所述的封裝結構，更包括一截線晶粒配置在所述第一與第N晶粒之間或是所述第N晶粒上。
  12. 一種封裝結構的製造方法，包括：提供基板：形成多晶粒堆疊結構在所述基板上，所述多晶粒堆疊結構具有相互堆疊的N個晶粒，所述N個晶粒包括由下至上的第一至第N晶粒，其中所述第一晶粒為底部晶粒，所述第N晶粒為頂部晶粒，其中N為大於1的整數；分別形成N個第一銲墊在所述晶粒的主動面上；形成第二銲墊在所述頂部晶粒上；以及藉由垂直打線製程分別形成N個垂直導線在所述第一銲墊上。
  13. 如申請專利範圍第12項所述的封裝結構的製造方法，其中所述垂直打線製程包括：藉由打線機將所述垂直導線的第一端分別接合在所述第一銲墊上； 藉由所述打線機將所述垂直導線的第二端分別拉至所述第二銲墊上，並進行加壓；以及藉由所述打線機將所述垂直導線的所述第二端分別拉至遠離所述基板的方向，以截斷所述垂直導線。
  14. 如申請專利範圍第12項所述的封裝結構的製造方法，其中所述第一銲墊的材料與所述第二銲墊的材料不同。
  15. 如申請專利範圍第12項所述的封裝結構的製造方法，其中所述第二銲墊的材料包括矽材料、半導體材料、金屬材料、黏晶材料、絕緣材料、電阻材料或其組合。
  16. 如申請專利範圍第12項所述的封裝結構的製造方法，其中所述N個垂直導線包括由下至上的第一至第N垂直導線，其中所述第一垂直導線的長度大於所述第N垂直導線的長度。
TW104133820A 2015-10-15 2015-10-15 封裝結構及其製造方法 TWI566356B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW104133820A TWI566356B (zh) 2015-10-15 2015-10-15 封裝結構及其製造方法
US14/970,558 US9673178B2 (en) 2015-10-15 2015-12-16 Method of forming package structure with dummy pads for bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104133820A TWI566356B (zh) 2015-10-15 2015-10-15 封裝結構及其製造方法

Publications (2)

Publication Number Publication Date
TWI566356B true TWI566356B (zh) 2017-01-11
TW201714265A TW201714265A (zh) 2017-04-16

Family

ID=58408118

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104133820A TWI566356B (zh) 2015-10-15 2015-10-15 封裝結構及其製造方法

Country Status (2)

Country Link
US (1) US9673178B2 (zh)
TW (1) TWI566356B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI582919B (zh) * 2015-12-31 2017-05-11 力成科技股份有限公司 無基板扇出型多晶片封裝構造及其製造方法
CN107611099B (zh) * 2016-07-12 2020-03-24 晟碟信息科技（上海）有限公司 包括多个半导体裸芯的扇出半导体装置
US20190164948A1 (en) * 2017-11-27 2019-05-30 Powertech Technology Inc. Package structure and manufacturing method thereof
CN110444528B (zh) 2018-05-04 2021-04-20 晟碟信息科技（上海）有限公司 包含虚设下拉式引线键合体的半导体装置
KR20210022321A (ko) * 2019-08-20 2021-03-03 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
JP2022002249A (ja) * 2020-06-19 2022-01-06 キオクシア株式会社 半導体装置およびその製造方法
KR20230088502A (ko) 2020-11-25 2023-06-19 가부시키가이샤 신가와 반도체 장치의 제조 방법 및 반도체 장치의 제조 장치

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200913208A (en) * 2007-06-11 2009-03-16 Vertical Circuits Inc Electrically interconnected stacked die assemblies

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789816A (en) * 1996-10-04 1998-08-04 United Microelectronics Corporation Multiple-chip integrated circuit package including a dummy chip
US6418029B1 (en) 2000-02-28 2002-07-09 Mckee James S. Interconnect system having vertically mounted passive components on an underside of a substrate
US6321976B1 (en) * 2000-05-22 2001-11-27 Siliconware Precision Industries Co., Ltd. Method of wire bonding for small clearance
KR100400032B1 (ko) * 2001-02-07 2003-09-29 삼성전자주식회사 와이어 본딩을 통해 기판 디자인을 변경하는 반도체 패키지
JP3825753B2 (ja) * 2003-01-14 2006-09-27 株式会社東芝 半導体装置の製造方法
TWI240392B (en) 2004-03-31 2005-09-21 Advanced Semiconductor Eng Process for packaging and stacking multiple chips with the same size
US20050258545A1 (en) 2004-05-24 2005-11-24 Chippac, Inc. Multiple die package with adhesive/spacer structure and insulated die surface
US8300423B1 (en) 2010-05-25 2012-10-30 Amkor Technology, Inc. Stackable treated via package and method
JP2013528324A (ja) 2010-06-08 2013-07-08 モサイド・テクノロジーズ・インコーポレーテッド ピラー接続を有するマルチチップパッケージ
KR20120035297A (ko) * 2010-10-05 2012-04-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR20120129286A (ko) 2011-05-19 2012-11-28 에스케이하이닉스 주식회사 적층 반도체 패키지
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
KR101774938B1 (ko) 2011-08-31 2017-09-06 삼성전자 주식회사 지지대를 갖는 반도체 패키지 및 그 형성 방법
US8922005B2 (en) 2012-04-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices with reversed stud bump through via interconnections
TW201347139A (zh) 2012-05-03 2013-11-16 矽品精密工業股份有限公司 半導體封裝件及其製法
KR102012505B1 (ko) 2012-12-20 2019-08-20 에스케이하이닉스 주식회사 토큰 링 루프를 갖는 스택 패키지
US20140210106A1 (en) 2013-01-29 2014-07-31 Apple Inc. ULTRA THIN PoP PACKAGE
TWI499843B (zh) * 2013-06-14 2015-09-11 Au Optronics Corp 光源模組
CN103400819B (zh) 2013-08-14 2017-07-07 矽力杰半导体技术(杭州)有限公司 一种引线框架及其制备方法和应用其的封装结构
US20160148965A1 (en) * 2014-09-30 2016-05-26 James E. Clayton Detector assembly using vertical wire bonds and compression decals
US9490222B1 (en) * 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200913208A (en) * 2007-06-11 2009-03-16 Vertical Circuits Inc Electrically interconnected stacked die assemblies

Also Published As

Publication number Publication date
US20170110439A1 (en) 2017-04-20
TW201714265A (zh) 2017-04-16
US9673178B2 (en) 2017-06-06

Similar Documents

Publication Publication Date Title
TWI566356B (zh) 封裝結構及其製造方法
US20180337065A1 (en) Carrier warpage control for three dimensional integrated circuit (3dic) stacking
US11728252B2 (en) Semiconductor device package
US9012269B2 (en) Reducing warpage for fan-out wafer level packaging
US9379078B2 (en) 3D die stacking structure with fine pitches
CN108766940B (zh) 用于3d封装的应力补偿层
US10229892B2 (en) Semiconductor package and method for manufacturing a semiconductor package
TWI541954B (zh) 半導體封裝件及其製法
JP2011142264A5 (zh)
US8860215B2 (en) Semiconductor device and method of manufacturing the same
JP4635202B2 (ja) 両面電極パッケージの製造方法
US9502392B2 (en) Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects
JP2012054264A5 (zh)
US20200258802A1 (en) Method for manufacturing electronic package
TWI585940B (zh) 多晶片堆疊封裝結構及其製造方法
KR101590453B1 (ko) 휨 개선을 위한 반도체 칩 다이 구조 및 방법
JP6537815B2 (ja) 半導体パッケージ及びその製造方法
JP5557439B2 (ja) 半導体装置及びその製造方法
CN104051399A (zh) 晶圆级芯片尺寸封装中间结构装置和方法
TWI599007B (zh) 電子單體及其製法
TW201448163A (zh) 半導體封裝件及其製法
US8823170B2 (en) Apparatus and method for three dimensional integrated circuits
TWI628756B (zh) 封裝結構及其製作方法
JP5666211B2 (ja) 配線基板及び半導体装置の製造方法
CN112018093A (zh) 具有定位成减少模片开裂的顶部模片的半导体器件