TWI585940B - 多晶片堆疊封裝結構及其製造方法 - Google Patents

多晶片堆疊封裝結構及其製造方法 Download PDF

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TWI585940B
TWI585940B TW105101003A TW105101003A TWI585940B TW I585940 B TWI585940 B TW I585940B TW 105101003 A TW105101003 A TW 105101003A TW 105101003 A TW105101003 A TW 105101003A TW I585940 B TWI585940 B TW I585940B
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林殿方
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東琳精密股份有限公司
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Description

多晶片堆疊封裝結構及其製造方法
本發明係關於一種半導體晶片封裝結構及其製造方法，尤指一種適用於多晶片堆疊封裝結構及其製造方法。
多晶片封裝結構(Multi-chip package,MCP)係將複數個半導體晶片整合在單一封裝結構中，可提高電子元件的密度，縮短電子元件間的電性連接路徑，此種封裝體不僅可減少多個晶片使用上所佔用的體積，更可提高整體的性能。
已知多晶片封裝結構係將複數個晶片垂直對齊堆疊、交叉錯位堆疊或階梯狀堆疊，接著藉由打線與基板練性連接。多個半導體晶片堆疊封裝技術中，多個相同尺寸晶片之堆疊封裝技術是常見的封裝技術。
在已知技術中，請參閱圖1係習知之堆疊式多晶片封裝結構之剖面示意圖，其第一晶片13之下表面黏貼於基板11上，第二晶片14之下表面則以交叉錯位方式黏貼於 第一晶片13之上表面上；第三晶片15之下表面以交叉錯位方式黏貼於第二晶片14上，而第四晶片16之下表面則以交叉錯位方式黏貼於第三晶片15之上表面上。此外，每一晶片之上表面上之銲墊皆有一導線分別對應電連接於基板10上之複數電性連接墊11。此外，該些晶片相互間皆是藉由一黏晶膠17黏貼。由於該第三晶片15與第二晶片14的堆疊處產生了一空間，因此，在打線時由於晶片支撐力不夠，而產生晶片破裂的問題。因此，為了滿足打線所需受力，需增厚第三晶片15的厚度以避免晶片受損。
另一已知技術中，如中華民國專利公開號第487615201222737A1號，係揭示一種半導體晶粒封裝，該半導體封裝之一實例包含與一第二半導體晶粒群組穿插之一第一半導體晶粒群組。來自該第一及第二群組之晶粒沿一第一軸線彼此偏移，且沿與該第一軸線正交之一第二軸線相對於彼此交錯。該半導體封裝之一第二實例包含一形狀不規則之邊緣及一自該封裝中之最下部半導體晶粒上方的一半導體晶粒至該基板的線接合。
然而，如圖1所示，此種堆疊式多晶片封裝結構1需增加晶片厚度以避免晶片受損，然而，在增加晶片厚度時，亦增加材料備制的複雜度，因而產生不易掌握晶片的厚度之問題。此外，在另一已知技術中，藉由打線方式將晶片電性連接於基板，但經由打線方式來電性連接容易造成晶片破裂。因此，目前亟需要一種多晶片堆疊封裝結構及其製造方法，藉由改變打線位置以提供較佳支撐，以及提供不經 打線之間隔件，以避免晶片受損，以及提供相同厚度的晶片以簡化製程步驟並控制製造成本。
本發明之主要目的係在提供一種堆疊式多晶片封裝結構，俾能利用晶片與間隔件交叉錯位之堆疊方式，藉由改變打線位置，因而，可降低打線時晶片斷裂之風險，並且達到輕薄短小之需求。
為達成上述目的，本發明提供一種多晶片堆疊封裝結構，包括：一基板，可包括複數個電性連接墊；一第一晶片，包括有一第一銲墊之一上表面及相對之一下表面，該第一晶片之該下表面黏貼於該基板上；一第二晶片，包括有一第二銲墊之一上表面及相對之一下表面，該第二晶片之該下表面可以交叉錯位方式黏貼於該第一晶片之該上表面；一間隔件，包括有一上表面及相對之一下表面，並且可以與該第二晶片交叉錯位方式設置於該第二晶片上表面上；以及一第三晶片，包括有一第三銲墊之一上表面及相對之一下表面，並且可以與該間隔件交叉錯位方式設置於該間隔件的上表面上，使得該第三晶片之一端與該間隔件之一端可形成一第一間距。
於本發明之多晶片堆疊封裝結構中，可更包括一第四晶片，該第四晶片可包括有一第四銲墊之一上表面及相對之一下表面，該第四晶片可以交叉錯位方式黏貼於該第三晶片之該上表面上。此外，於本發明之多晶片堆疊封裝結 構中，該第三銲墊可緊鄰於該第四晶片而設置以提供最佳的支撐，進而避免晶片破裂。
於本發明之多晶片堆疊封裝結構中，可更包括複數條導線，用於將該些電性連接墊與該第一銲墊、第二銲墊、第三銲墊及第四銲墊電性連接，或將該些銲墊彼此電性連接，以輸入或輸出信號。於本發明之多晶片堆疊封裝結構中，該間隔件不與導線連結，因此該間隔件不會因為打線而破裂。
於本發明之多晶片堆疊封裝結構中，該第四晶片之一端與該間隔件之一端可形成一第二間距；其中，該第二間距之距離與第一間距之距離可依據使用者需求而任意變化，在本發明一態樣中，該第二間距之距離可為該第一間距之距離的兩倍，但本發明並未侷限於此。於本發明之多晶片堆疊封裝結構中，將該第一間距的距離、第二間距的距離與該晶片的寬度相加所獲得的數值需小於該基板的長度，以利於封裝該多晶片堆疊封裝結構。
於本發明之多晶片堆疊封裝結構中，所堆疊的晶片數量及間隔件的數量可依據使用者需求而任意變化，在本發明一態樣中，所堆疊的晶片數量為4且間隔件數量為1，此外，該間隔件堆疊的位置較佳為該些晶片中間，以提供較佳的支撐避免晶片破裂。
於本發明之多晶片堆疊封裝結構中，該第一晶片、該第二晶片、該第三晶片及該第四晶片可藉由一黏膠層彼此黏貼，此外，該第一晶片之下表面可藉由一黏晶膠黏貼 於該基板上；本發明之該黏膠層或該黏晶膠可為一薄膜覆蓋導線膠層(Film On Wier Tape)或其他等效結構之黏膠層；在本發明一態樣中，該黏晶膠可為薄膜覆蓋導線膠層。
除此之外，本發明另一目的係提供一種多晶片堆疊封裝結構之製造方法，包括：提供一基板，該基板可具有複數個電性連接墊；設置第一晶片於該基板上，該第一晶片可包括有一第一銲墊之一上表面及相對之一下表面，該第一晶片之該下表面黏貼於該基板；設置一第二晶片於該第一晶片上，該第二晶片可包括有一第二銲墊之一上表面及相對之一下表面，該第二晶片之該下表面可以交叉錯位方式黏貼於該第一晶片之該上表面；設置一間隔件於該第二晶片上，該間隔件可包括有一上表面及相對之一下表面，並且以與該第二晶片交叉錯位方式設置於該第二晶面之上表面上；以及設置一第三晶片於該間隔件上，該第三晶片可包括有一第三銲墊之一上表面及相對之一下表面，該第三晶片之該下表面設置於該間隔件之上表面上，使得該第三晶片之一端與該間隔件之一端形成一第一間距。
於本發明之多晶片堆疊封裝結構之製造方法中，可更包括設置一第四晶片於該第三晶片上，該第四晶片可包括有一第四銲墊之一上表面及相對之一下表面，該第四晶片可以交叉錯位方式黏貼於該第三晶片之該上表面上。於本發明之多晶片堆疊封裝結構之製造方法中，該第三銲墊係緊鄰於該第四晶片而設置以提供最佳的支撐，進而避免晶片破裂。。
於本發明之多晶片堆疊封裝結構之製造方法中，可更包括形成複數條導線，該些導線將該些電性連接墊與該第一銲墊、該第二銲墊、該第三銲墊及該第四銲墊電性連接，或將該些銲墊彼此電性連接。於本發明之多晶片堆疊封裝結構之製造方法中，該間隔件不與導線連結，因此該間隔件不會因為打線而破裂。
於本發明之多晶片堆疊封裝結構之製造方法中，該第四晶片之一端與該間隔件之一端可形成一第二間距；其中，該第二間距之距離與第一間距之距離可依據使用者需求而任意變化，在本發明一態樣中，該第二間距之距離可為該第一間距之距離的兩倍，但本發明並未侷限於此。
於本發明之多晶片堆疊封裝結構之製造方法中，該第一晶片、該第二晶片、該第三晶片及該第四晶片可藉由一黏膠層彼此黏貼，此外，該第一晶片之下表面可藉由一黏晶膠黏貼於該基板上。本發明之該黏膠層或該黏晶膠可為一薄膜覆蓋導線膠層或其他等效結構之黏膠層；在本發明一態樣中，該黏晶膠可為薄膜覆蓋導線膠層。
是以，本發明的功效在於改變打線位置以提供較佳支撐，進而避免晶片破裂，並且提供相同厚度的晶片以簡化晶片製程。綜上所述，本發明的特徵為在複數個晶片中具有至少一間隔件，可提供該些晶片較佳的支撐點，且該間隔件不具有導線連結，可避免因打線而造成晶片破裂。
1,2‧‧‧多晶片堆疊封裝結構
10,11‧‧‧基板
12,101‧‧‧電性連接墊
13,20‧‧‧第一晶片
201‧‧‧第一銲墊
14,30‧‧‧第二晶片
301‧‧‧第二銲墊
40‧‧‧間隔件
15,50‧‧‧第三晶片
17‧‧‧黏晶膠
501‧‧‧第三銲墊
16,60‧‧‧第四晶片
601‧‧‧第四銲墊
70‧‧‧導線
80‧‧‧黏膠層
圖1係為習知之堆疊式多晶片封裝結構之剖面示意圖。
圖2係本發明實施例1之堆疊式多晶片封裝結構之剖面示意圖。
圖3係本發明實施例1之打線受力點與先前技術打線受力點之剖面示意圖。
圖4係本發明實施例2之多晶片堆疊封裝結構之製造方法之流程圖。
以下係藉由具體實施例說明本發明之實施方式，熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本發明之其他優點與功效。此外，本發明亦可藉由其他不同具體實施例加以施行或應用，在不悖離本發明之精神下進行各種修飾與變更。
實施例1
請參照圖2所示，係本發明實施例1之剖面示意圖。於本發明之多晶片堆疊封裝結構2中，包括：一基板10，包括複數個電性連接墊101；一第一晶片20，包括有一第一銲墊201之一上表面及相對之一下表面，該第一晶片20之該下表面黏貼於該基板10上；一第二晶片30，包括有一第二銲墊301之一上表面及相對之一下表面，該第二晶片30之該下表面以交叉錯位方式黏貼於該第一晶片20之該上表面；一間隔件40，包括有一上表面及相對之一下表面，並且 以與該第二晶片30交叉錯位方式設置於該第二晶片30之上表面上；以及一第三晶片50，包括有一第三銲墊501之一上表面及相對之一下表面，並且以與該間隔件40交叉錯位方式設置於該間隔件40之上表面上，使得該第三晶片50之一端與該間隔件40之一端形成一第一間距。其次，本發明之多晶片堆疊封裝結構2更包括一第四晶片60，該第四晶片60包括有一第四銲墊601之一上表面及相對之一下表面，該第四晶片60以交叉錯位方式黏貼於該第三晶片50之該上表面上；此外，該第三銲墊501係緊鄰於該第四晶片60而設置以提供較佳支撐點，以避免第三晶片50破裂。接著，藉由導線70將該些電性連接墊101與該第一銲墊201、第二銲墊301、第三銲墊501及第四銲墊601電性連接，並將該些銲墊彼此電性連接，以輸入或輸出信號。再者，該第四晶片60之一端與該間隔件40之一端可形成一第二間距；且該第二間距之距離為該第二間距之距離的兩倍。
請參照圖3所示，係本發明實施例1之打線受力點與先前技術打線受力點之剖面示意圖。如圖3所示，該第三晶片50之一端與該間隔件40之一端可形成一第一間距(X)，以及該第四晶片60之一端與該間隔件40之一端可形成一第二間距(2X)，此外，該第一晶片20的一端與該第二晶片30的一端形成該第二間距(2X)。在圖3中，原打線受力點A與本發明的打線受力點B相比，本發明的受力點A較接近第三晶片50而受力點A較遠離第三晶片50。由於原打線受力點A下方並無較好的支撐，因此在打線時，容易造成晶片破 裂，因而需要較厚的晶片以滿足打線所需受力，進而避免晶片受損，然而，製造出較厚的晶片在材料備制上將增加製程的複雜度，因此，在理想厚度(即晶片及間隔件具有相同厚度)前提下，改變打線位置(如，受力點B)並增加間隔件的設置可提供較佳的支撐，進而避免晶片受損。請參照圖3，受力點A與受力點B具有相同支點，然而由於受力點A與受力點B的施力點位置不同，因此會產生不同的力矩，由圖3可知在受力點B具有較佳支撐，進而避免第三晶片50因打線而破裂。
實施例2
請參照圖4所示，係本發明實施例2之多晶片堆疊封裝結構之製造方法之流程圖。首先，如步驟401所示，提供一基板，該基板可有複數個電性連接墊。其次，如步驟402所示，設置第一晶片，將第一晶片設置於該基板上，該第一晶片包括有一第一銲墊之一上表面及相對之一下表面，該第一晶片之該下表面黏貼於該基板。再者，如步驟403所示，設置第二晶片，將該第二晶片設置於該第一晶片上，該第二晶片包括有一第二銲墊之一上表面及相對之一下表面，該第二晶片之該下表面可以交叉錯位方式黏貼於該第一晶片之該上表面。接著，如步驟404所示，設置間隔件，將該間隔件設置於該第二晶片上，該間隔件包括有一上表面及相對之一下表面，並且以與該第二晶片交叉錯位方式設置於該第二晶片之該上表面上。接著，如步驟405所示，設置第三晶片，將第三晶片設置於該間隔件上，該第三晶片包括有一第 三銲墊之一上表面及相對之一下表面，該第三晶片之該下表面設置於該間隔件上表面上，使得該第三晶片之一端與該間隔件之一端形成一第一間距。如步驟406所示，設置第四晶片，將第四晶片設置於該第三晶片上，該第四晶片包括有一第四銲墊之一上表面及相對之一下表面，該第四晶片以交叉錯位方式黏貼於該第三晶片之該上表面上，且該第三銲墊係緊鄰於該第四晶片而設置，以提供較佳支撐避免第三晶片破裂。在步驟401與步驟402之間，藉由黏貼黏晶膠使第一晶片黏貼於基板上；在步驟402、步驟403、步驟404、步驟405以及步驟406之間，藉由黏貼黏膠層使第一晶片、第二晶片、第三晶片以及第四晶片彼此黏貼。最後，如步驟407所示，提供導線，將該些電性連接墊與該第一銲墊、第二銲墊、第三銲墊及第四銲墊電性連接，並將該些銲墊彼此電性連接，以輸入或輸出信號。
在本發明之多晶片堆疊封裝結構中，藉由改變打線位置以提供較佳支撐，以及提供不經打線之間隔件以避免晶片受損，再者提供相同厚度的晶片以簡化製程步驟並控制製造成本。本發明可以堆疊複數晶片，可將不同功能的晶片整合在單一封裝結構中，不僅可減少多個晶片使用上所佔用的體積，更可提高整體的性能。
上述實施例僅係為了方便說明而舉例而已，本發明所主張之權利範圍自應以申請專利範圍所述為準，而非僅限於上述實施例。
10‧‧‧基板
101‧‧‧電性連接墊
2‧‧‧多晶片堆疊封裝結構
20‧‧‧第一晶片
201‧‧‧第一銲墊
30‧‧‧第二晶片
301‧‧‧第二銲墊
40‧‧‧間隔件
50‧‧‧第三晶片
501‧‧‧第三銲墊
60‧‧‧第四晶片
601‧‧‧第四銲墊
70‧‧‧導線
80‧‧‧黏膠層

Claims (15)

  1. 一種多晶片堆疊封裝結構，包括：一基板，包括複數個電性連接墊；一第一晶片，包括有一第一銲墊之一上表面及相對之一下表面，該第一晶片之該下表面黏貼於該基板上；一第二晶片，包括有一第二銲墊之一上表面及相對之一下表面，該第二晶片之該下表面以交叉錯位方式黏貼於該第一晶片之該上表面；一間隔件，包括有一上表面及相對之一下表面，並且以與該第二晶片交叉錯位方式設置於其上；以及一第三晶片，包括有一第三銲墊之一上表面及相對之一下表面，該第三晶片之該下表面設置於該間隔件上，使得該第三晶片之一端與該間隔件之一端形成一第一間距，該第一間距形成於該間隔件之該上表面上、且位於該第三晶片之設置有該第三焊墊之一端與該間隔件之一端之間。
  2. 如請求項1所述之多晶片堆疊封裝結構，更包括一第四晶片，該第四晶片包括有一第四銲墊之一上表面及相對之一下表面，該第四晶片以交叉錯位方式黏貼於該第三晶片之該上表面上。
  3. 如請求項2所述之多晶片堆疊封裝結構，其中，該第三銲墊係緊鄰於該第四晶片而設置。
  4. 如請求項1所述之多晶片堆疊封裝結構，更包括複數條導線，用於將該些電性連接墊與該第一銲墊、第二銲墊、第三銲墊及第四銲墊電性連接，或將該些銲墊彼此電性連接。
  5. 如請求項2所述之多晶片堆疊封裝結構，其中，該第四晶片之一端與該間隔件之一端形成一第二間距。
  6. 如請求項5所述之多晶片堆疊封裝結構，其中，該第二間距之距離係為該第一間距之距離的兩倍。
  7. 如請求項2所述之多晶片堆疊封裝結構，其中，該第一晶片、該第二晶片、該第三晶片及該第四晶片係藉由一黏膠層彼此黏貼。
  8. 一種多晶片堆疊封裝結構之製造方法，包括：提供一基板，該基板具有複數個電性連接墊；設置第一晶片於該基板上，該第一晶片包括有一第一銲墊之一上表面及相對之一下表面，該第一晶片之該下表面黏貼於該基板；設置一第二晶片於該第一晶片上，該第二晶片包括有一第二銲墊之一上表面及相對之一下表面，該第二晶片之該下表面以交叉錯位方式黏貼於該第一晶片之該上表面；設置一間隔件於該第二晶片上，該間隔件包括有一上表面及相對之一下表面，並且以與該第二晶片交叉錯位方式設置於其上；以及設置一第三晶片於該間隔件上，該第三晶片包括有一第三銲墊之一上表面及相對之一下表面，該第三晶片之該下表面設置於該間隔件上，使得該第三晶片之一端與該間隔件之一端形成一第一間距，其中該第一間距形成於該間隔件之該上表面上、且位於該第三晶片之設置有該第三焊墊之一端與該間隔件之一端之間。
  9. 如請求項8所述之製造方法，更包括設置一第四晶片於該第三晶片上，該第四晶片包括有一第四銲墊之一上表面及相對之一下表面，該第四晶片以交叉錯位方式黏貼於該第三晶片之該上表面上。
  10. 如請求項9所述之製造方法，其中，該第三銲墊係緊鄰於該第四晶片而設置。
  11. 如請求項9所述之製造方法，更包括形成複數條導線，該些導線將該些電性連接墊與該第一銲墊、該第二銲墊、該第三銲墊及該第四銲墊電性連接，或將該些銲墊彼此電性連接。
  12. 如請求項9所述之製造方法，其中，該第四晶片之一端與該間隔件之一端形成一第二間距。
  13. 如請求項12所述之製造方法，該第二間距之距離係為該第一間距之距離的兩倍。
  14. 如請求項9所述之製造方法，其中，該第一晶片、該第二晶片、該第三晶片及該第四晶片係藉由一黏膠層彼此黏貼。
  15. 如請求項8所述之製造方法，其中，該第一晶片之下表面係藉由一黏晶膠黏貼於該基板上。
TW105101003A 2015-02-12 2016-01-13 多晶片堆疊封裝結構及其製造方法 TWI585940B (zh)

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Citations (1)

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US20130093103A1 (en) * 2010-06-22 2013-04-18 Hana Micron Inc Layered Semiconductor Package

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US8242607B2 (en) * 2006-12-20 2012-08-14 Stats Chippac Ltd. Integrated circuit package system with offset stacked die and method of manufacture thereof
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US20130093103A1 (en) * 2010-06-22 2013-04-18 Hana Micron Inc Layered Semiconductor Package

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