TWI399845B - 無線弧之多晶片堆疊構造及其製造方法 - Google Patents

無線弧之多晶片堆疊構造及其製造方法 Download PDF

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TWI399845B
TWI399845B TW098132340A TW98132340A TWI399845B TW I399845 B TWI399845 B TW I399845B TW 098132340 A TW098132340 A TW 098132340A TW 98132340 A TW98132340 A TW 98132340A TW I399845 B TWI399845 B TW I399845B
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wafer
active surface
pads
substrate
stack structure
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TW201112384A (en
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Tsai Tsung Tsai
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Powertech Technology Inc
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Description

無線弧之多晶片堆疊構造及其製造方法
本發明係有關於半導體裝置,特別係有關於一種無線弧之多晶片堆疊構造及其製造方法。
為了符合現今對於半導體產業微小化與高處理速度的需求,半導體封裝結構已將多晶片模組化(Multi-Chip Module)作為一趨勢。藉由將兩個或兩個以上之半導體晶片組合在單一封裝結構中,以縮減整體封裝體積,並提升電性功能。近年來常使用多層堆疊方法來增加單一封裝結構中的晶片數量,其堆疊的方式必須按照本身晶片之設計與打線製程而有所不同,例如:階梯狀堆疊、Z字堆疊。
傳統的打線機在面對多層晶片或是單層晶片結構時,需要先在上下層晶片的鋁墊上打線方式種植金球(或稱結線凸塊),作為線頭,然後再依照不同的需求,將金線向後拉伸轉折做出理想的弧形。然而,傳統的打線方式,運用在產品上時常常會面臨許多問題。
如第1圖所示,一種習知的多晶片堆疊構造100,其係主要包含一基板110、一上晶片120、一下晶片130、複數個銲線151、152以及一封膠體170。以該下晶片130之背面黏合至該基板110之上表面,該上晶片120係設置於該下晶片130之主動面131上,而顯露該下晶片130之銲墊132,以形成階梯狀之多晶片堆疊結構。在一打線製程中,銲線151連接該上晶片120之銲墊122至該下晶片130之銲墊132。再以打線方式,使銲線152壓合至先形成銲線151在該下晶片120之銲墊122上之尾端至該基板110之接指111,以完成整體的電性連接。為了避免銲線151之尾端的沾不黏或者是銲墊122的破裂,在下晶片120之銲墊122上應預先打上一獨立金球153,以增加結合力與緩衝保護。該封膠體170係設置於該基板110之上表面,以包覆該上晶片120、該下晶片130與該些銲線140。然而,在形成該封膠體170時,必須要考慮到該些銲線140在該上晶片120之主動面121上所產生的懸空線弧之高度,故無法有效地降低整體的封裝高度。
由於傳統的多晶片之間與晶片與基板之間皆是利用該些銲線140達到電性連接,在後續的多晶片堆疊製程中會衍生出許多各種可能的封裝缺陷。例如,關於銲墊部分會有金球不黏(NSOP)、銲墊破裂(pad crack)問題,關於銲線部分會有頸傷(neck damage)、弧高不穩、甩線、弧高範圍受限、歪線(wire sweep after moding)等問題,關於接指部分,會有尾線不黏(NSOL)、接指太小導致在多層晶片堆疊無法打入太多銲線的問題。
為了解決上述之問題,本發明之主要目的係在於提供一種無線弧之多晶片堆疊構造,不會有超過上層晶片之主動面的懸空線弧,能消除習知線弧造成的封裝缺陷。
本發明之次一目的係在於提供一種無線弧之多晶片堆疊構造,在製造過程中皆不需要作拉線弧與植球的動作,除了可大幅地提升產能,亦無銲點不黏之情形,並能達到良好的晶片電性互連。
本發明之再一目的係在於提供一種無線弧之多晶片堆疊構造,金線筆可隨意依照不同的線圖需求而改變畫線路徑,亦能將金線換成其他任何金屬材質,以降低成本。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種無線弧之多晶片堆疊構造,主要包含一基板、一第一晶片、一第二晶片、一耐熱絕緣膠片以及複數個塗畫導線。該第一晶片係設置於該基板上,該第一晶片係具有一遠離該基板之第一主動面以及在該第一主動面上之複數個第一銲墊。該第二晶片係設置於該第一晶片之第一主動面上但不完全覆蓋該第一主動面,以顯露該些第一銲墊,該第二晶片係具有一遠離該基板之第二主動面以及在該第二主動面上之複數個第二銲墊。該耐熱絕緣膠片係彎曲地貼附至該第一主動面與該第二主動面,並在該第一主動面與該第二主動面之間提供一可塗畫斜坡。該些塗畫導線係熔附於該耐熱絕緣膠片上,該些塗畫導線係順著該可塗畫斜坡以連接該些第一銲墊與對應之該些第二銲墊。本發明另揭示該無線弧之多晶片堆疊構造之製造方法。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述之無線弧之多晶片堆疊構造中,該些塗畫導線係可由一金線筆塗畫形成。
在前述之無線弧之多晶片堆疊構造中,該耐熱絕緣膠片係可具有複數個第一開孔與第二開孔,以分別顯露該些第一銲墊與該些第二銲墊。
在前述之無線弧之多晶片堆疊構造中,該些塗畫導線係可延伸至該些第一開孔與該些第二開孔,以分別熔附於該些第一銲墊與該些第二銲墊。
在前述之無線弧之多晶片堆疊構造中,該耐熱絕緣膠片係可更延伸至該基板,並在該第一主動面與該基板之間提供一第二可塗畫斜坡。
在前述之無線弧之多晶片堆疊構造中,該些塗畫導線係可順著該第二可塗畫斜坡以連接該些第一銲墊與該基板之複數個接指。
在前述之無線弧之多晶片堆疊構造中,可另包含複數個打線形成之銲線,係電性連接該些第一銲墊與該基板之複數個接指。
在前述之無線弧之多晶片堆疊構造中,可另包含至少一打線形成之跨接銲線,係連接該些第一銲墊之其中之一與對應之第二銲墊,並在俯視圖中與該些塗畫導線之至少一個構成電絕緣性交錯。
在前述之無線弧之多晶片堆疊構造中,可另包含一填充材,係形成於該耐熱絕緣膠片與該第二晶片側的空隙內。
在前述之無線弧之多晶片堆疊構造中,可另包含一封裝體,係形成於該基板上,以密封該第一晶片與該第二晶片。
在前述之無線弧之多晶片堆疊構造中,可另包含至少一第三晶片,係設置於該第二晶片之第二主動面上但不完全覆蓋該第二主動面,以顯露該些第二銲墊,該第三晶片係具有一遠離該基板之第三主動面以及在該第三主動面上之複數個第三銲墊,並且該耐熱絕緣膠片係更延伸至該第三晶片之第三主動面,並在該第三主動面與該第二主動面之間提供另一可塗畫斜坡,並且該些塗畫導線係順著所述另一可塗畫斜坡以連接該些第二銲墊與該第三銲墊。
在前述之無線弧之多晶片堆疊構造中,該第一晶片、該第二晶片與該第三晶片係可為階梯狀堆疊。
在前述之無線弧之多晶片堆疊構造中,可另包含至少一晶片組,係設置於該第二晶片之第二主動面上,並局部壓附至該耐熱絕緣膠片,而與該第一晶片與該第二晶片為Z字堆疊。
由以上技術方案可以看出,本發明之無線弧之多晶片堆疊構造,有以下優點與功效:
一、可藉由耐熱絕緣膠片與塗畫導線之特定組合關係作為其中一技術手段,由於耐熱絕緣膠片係彎曲地貼附至第一主動面與第二主動面,以提供可塗畫斜坡,並且塗畫導線係順著可塗畫斜坡以連接第一銲墊與對應之第二銲墊。因此,不會有超過第二晶片之第二主動面的懸空線弧,能消除習知線弧造成的封裝缺陷。
二、可藉由耐熱絕緣膠片與塗畫導線之特定組合關係作為其中一技術手段,由於耐熱絕緣膠片係具有第一與第二開孔,以分別顯露第一與第二銲墊,並且塗畫導線係延伸至第一與第二開孔,分別熔附於第一與第二銲墊。因此,不會發生銲點不黏之情形,並能達到良好的晶片電性互連。
三、可藉由耐熱絕緣膠片與塗畫導線之特定組合關係作為其中一技術手段,由於塗畫導線係由金線筆塗畫形成,再藉由耐熱絕緣膠片之隔離,使得塗畫導線可隨意依照不同的線圖需求而改變畫線路徑。此外,更能將金線換成其他任何金屬材質,以降低成本。
四、可藉由耐熱絕緣膠片與塗畫導線之特定組合關係作為其中一技術手段,在製造過程中皆不需要作拉線弧與植球的動作,故能大幅地提升產能,更適用於多層晶片堆疊的結構。
五、可藉由耐熱絕緣膠片與銲線之特定組合關係作為其中一技術手段,藉由銲線電性連接第一銲墊與基板之接指,使得耐熱絕緣膠片可不必延伸至基板,減少塗畫導線的塗畫長度,並降低因晶片與基板間應力影響而導致耐熱絕緣膠片的坡度改變。
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例,一種無線弧之多晶片堆疊構造舉例說明於第2圖之截面示意圖與第3圖未封裝前之立體示意圖。該無線弧之多晶片堆疊構造200係主要包含一基板210、一第一晶片220、一第二晶片230、一耐熱絕緣膠片240以及複數個塗畫導線250。在本實施例中,該基板210係可具有複數個接指211。該些接指211係可設置於該基板210的上表面之同一側邊。詳細而言,通常該基板210係可為一印刷電路板、一電路薄膜或各種晶片載板。
請參閱第2圖所示,該第一晶片220係設置於該基板210上,該第一晶片220係具有一遠離該基板210之第一主動面221以及在該第一主動面221上之複數個第一銲墊222。也就是說,該第一晶片220之該第一主動面221並非貼附於該基板210之上表面,以使該些第一銲墊222朝上設置。此外,該第二晶片230係設置於該第一晶片220之第一主動面221上但不完全覆蓋該第一主動面221,以顯露該些第一銲墊222。該第二晶片230係具有一遠離該基板210之第二主動面231以及在該第二主動面231上之複數個第二銲墊232。在一較佳實施例中,該些第一銲墊222與該些第二銲墊232係鄰近於該基板210之該些接指211,以縮短晶片之間連接線路之長度而降低訊號延遲與存取時間。該第一晶片220與該第二晶片230可為實質相同之晶片,而具有相同積體電路功能、尺寸與銲墊分佈。該第一晶片220與該第二晶片230之間的堆疊可為階梯狀。
請再參閱第2與3圖所示,該耐熱絕緣膠片240係彎曲地貼附至該第一主動面221與該第二主動面231,並在該第一主動面221與該第二主動面231之間提供一可塗畫斜坡241。更進一步地,該耐熱絕緣膠片240係可更延伸至該基板210,並在該第一主動面221與該基板210之間提供一第二可塗畫斜坡244。在本實施例中,該耐熱絕緣膠片240係可具有複數個第一開孔242與第二開孔243,以分別顯露該些第一銲墊222與該些第二銲墊232。詳細而言,由於該耐熱絕緣膠片240提供了該可塗畫斜坡241,而非完全緊貼於該第二晶片230之側面,故會在該耐熱絕緣膠片240與該第二晶片230側之間會產生空隙。較佳地,可另包含一填充材260,係形成於該耐熱絕緣膠片240與該第二晶片230側的空隙內,能加強該耐熱絕緣膠片240與該第二晶片230之黏著強度,更可用以支撐該耐熱絕緣膠片240,以維持該可塗畫斜坡241之平整度與坡度。此外,倘若該耐熱絕緣膠片240與該第一晶片220側形成空隙,亦可在封裝前利用該填充材260填補,能強化整體結構,以避免該耐熱絕緣膠片240斷折或變形。在一較佳實施例中,該耐熱絕緣膠片240係可為預型片(preform),本身具有黏性,可省略一黏著層,並能依照不同需求而改變該耐熱絕緣膠片240之尺寸,以符合各種不同的晶片堆疊結構,例如:階梯狀堆疊、Z字堆疊。
再請參閱第2與3圖所示,該些塗畫導線250係熔附於該耐熱絕緣膠片240上,該些塗畫導線250係順著該可塗畫斜坡241以連接該些第一銲墊222與對應之該些第二銲墊232。在本實施例中,該些塗畫導線250係可由一金線筆50塗畫形成。在另一變化實施例中,可將該金線筆50更換為其他任何金屬材質,例如:鋁、銅等價格較為便宜之材質,以降低製造成本。詳細而言,該金線筆50係預先加熱至可使該些塗畫導線250成融熔態的溫度,其加熱方式可採用尖端加熱或放電方式,以減少能源消耗。在本實施例中,該些塗畫導線250係可延伸至該些第一開孔242與該些第二開孔243,以分別熔附於該些第一銲墊222與該些第二銲墊232。由於該些塗畫導線250係在融熔態時與該些銲墊結合,故在冷卻之後能達到最佳共晶狀態,而不會發生銲點不黏之情形。更進一步地,該些塗畫導線250係可順著該第二可塗畫斜坡244以連接該些第一銲墊222與該基板210之該些接指211。此外,可另包含一封裝體270,係形成於該基板210上,以密封該第一晶片220與該第二晶片230。由於該些塗畫導線250係平貼於該耐熱絕緣膠片240上,並不會形成線弧,故能有效地降低該封裝體270之高度。
在本發明中,利用該耐熱絕緣膠片240彎曲地貼附至該第一主動面221與該第二主動面231與該些塗畫導線250順著該可塗畫斜坡241以連接該第一銲墊222與對應之第二銲墊232之特定組合關係,故不會有超過該第二晶片230之該第二主動面231的懸空線弧,能消除習知線弧造成的封裝缺陷,例如晶片銲墊上金球不黏、銲墊破裂等問題、銲線的頸傷、弧高不穩、甩線、弧高範圍受限、歪線(或稱沖線)等問題、接指的尾線不黏、無法使連接多層晶片堆疊之多條銲線打在同一較小接指上等問題。並且,藉由該耐熱絕緣膠片240之隔離,使該金線筆50可隨意依照不同的線圖需求而改變該些塗畫導線250之路徑。因此,該無線弧之多晶片堆疊構造200毋須設置有習知的銲線,在製造過程中不需做線弧或植球的動作,能夠省略以往的打線製程,以大幅地提升產能(Unit Per Hour,UPH)與產品良率。
本發明還揭示該無線弧之多晶片堆疊構造之製造方法舉例說明於第4A至4H圖之元件截面示意圖。詳細步驟說明如下所示。
首先,如第4A圖所示,提供一基板210。該基板210係可具有複數個接指211,該些接指211係設置於該基板210的上表面之同一側邊。在本實施例中,通常該基板210係可為一印刷電路板、一電路薄膜或各種晶片載板。
再如第4B圖所示,設置一第一晶片220於該基板210上,該第一晶片220係具有一遠離該基板210之第一主動面221以及在該第一主動面221上之複數個第一銲墊222。也就是說,在設置該第一晶片220時,係將該第一主動面221朝上設置,並以該第一晶片220之背面貼附至該基板210之上表面。
接著,如第4C圖所示,設置一第二晶片230於該第一晶片220之第一主動面221上但不完全覆蓋該第一主動面221,以顯露該些第一銲墊222,該第二晶片230係具有一遠離該基板210之第二主動面231以及在該第二主動面231上之複數個第二銲墊232。更具體地,在設置該第一晶片220與該第二晶片230時,使該些第一銲墊222與該些第二銲墊232鄰近於該基板210之該些接指211,故能縮短晶片間連接線路之長度而降低訊號延遲與存取時間。
如第4D圖所示,提供一耐熱絕緣膠片240。在本實施例中,該耐熱絕緣膠片240係可具有複數個第一開孔242與第二開孔243。接著,如第4E圖所示,彎曲地貼附該耐熱絕緣膠片240至該第一主動面221與該第二主動面231,並在該第一主動面221與該第二主動面231之間提供一可塗畫斜坡241。此外,該耐熱絕緣膠片240係可更延伸至該基板210,並在該第一主動面221與該基板210之間提供一第二可塗畫斜坡244。較佳地,藉由該可塗畫斜坡241與該第二可塗畫斜坡244,使得該耐熱絕緣膠片240能更平順地貼附於所覆蓋的區域。在貼附該耐熱絕緣膠片240之後,該些第一開孔242與該些第二開孔243係分別顯露該些第一銲墊222與該些第二銲墊232,以利後續步驟之進行。
如第4F至4H圖所示,執行一畫線操作,以形成複數個塗畫導線250,其係熔附於該耐熱絕緣膠片240上。在本實施例中,該些塗畫導線250係可由一金線筆50提供,其材質可包含鋁、銅或其它可共晶化金屬。首先,如第4F圖所示,加熱該金線筆50,使其溫度提升至可使該些塗畫導線250轉化成融熔態,並填入對應的第二開孔243,以接合至對應第二銲墊232。在此步驟中,其加熱方式係可採尖端加熱或放電形式達成,以減少能源消耗。可利用少量能源消耗便能使電燈泡將中心鎢絲快速加熱至攝氏千度。接著,如第4G圖所示,移動該金線筆50,使該些塗畫導線250順著該可塗畫斜坡241以連接該些第一銲墊222與對應之該些第二銲墊232。在本實施例中,該些塗畫導線250係可延伸至該些第一開孔242與該些第二開孔243,以分別熔附於該些第一銲墊222與該些第二銲墊232。此外,由該金線筆50畫出導線路徑的該些塗畫導線250係平貼於該耐熱絕緣膠片240,故不會產生任何線弧。再如第4H圖所示,在本實施例中,可繼續移動該金線筆50,使該些塗畫導線250順著該第二可塗畫斜坡244以連接該些第一銲墊222與該基板210之該些接指211,以完成電性連接。在此步驟中,由於該些塗畫導線250係在融熔狀態下以塗畫方式與該些第一銲墊222、該些第二銲墊232以及該些接指211產生接合,在冷卻之後,能達到最佳共晶狀態,故不會發生習知打線銲點沾不黏與銲墊破裂之情形。在一較佳實施例中,可另形成一填充材260於該耐熱絕緣膠片240之底面與該第二晶片230的側面的空隙內,以填補前述之空隙。最後,可另形成一封裝體270於該基板210上,以密封該第一晶片220與該第二晶片230(如第2圖所示)。因為不會有突出該第二晶片230之該第二主動面231之懸空線弧,在形成該封裝體270時,能盡可能地貼近於該第二主動面231,以降低整體的封裝高度。
依據本發明之第二具體實施例,另一種無線弧之多晶片堆疊構造舉例說明於第5圖之截面示意圖。該無線弧之多晶片堆疊構造300係主要包含一基板310、一第一晶片220、一第二晶片230、一耐熱絕緣膠片240以及複數個塗畫導線250。其中與第一實施例相同的主要元件將以相同符號標示,不再詳予贅述。在本實施例中,可包含更多晶片。
請參閱第5圖所示,可另包含至少一第三晶片380,係設置於該第二晶片230之第二主動面231上但不完全覆蓋該第二主動面231,以顯露該些第二銲墊232,該第三晶片380係具有一遠離該基板310之第三主動面381以及在該第三主動面381上之複數個第三銲墊382,並且該耐熱絕緣膠片240係更延伸至該第三晶片380之第三主動面381,並在該第三主動面381與該第二主動面231之間提供另一可塗畫斜坡341,並且該些塗畫導線250係順著所述另一可塗畫斜坡341以連接該些第二銲墊232與該第三銲墊382。在本實施例中,該第一晶片220、該第二晶片230與該第三晶片380係可為階梯狀堆疊。在一變化實施例中,可依照產品需求增加該第三晶片380之堆疊數量,以增加整體的運作性能。此外,該基板310係可因應該第三晶片380之堆疊數量而適當改變尺寸,以提供足夠的封裝空間。由於該些塗畫導線250係平貼於該耐熱絕緣膠片240上,而不會產生有任何懸空線弧,即使在因應需求而增加該第三晶片380之堆疊數量之情況下,亦能完全排除以往打線製程後,習知的銲線所產生的線弧高度,以有效地降低整體封裝高度。
依據本發明之第三具體實施例,另一種多晶片堆疊構造舉例說明於第6圖之截面示意圖。該多晶片堆疊構造400係主要包含一基板210、一第一晶片220、一第二晶片230、一耐熱絕緣膠片240以及複數個塗畫導線250。其中與第一實施例相同的主要元件將以相同符號標示,不再詳予贅述。
請參閱第6圖所示,可另包含至少一晶片組490,係設置於該第二晶片230之第二主動面231上,並局部壓附至該耐熱絕緣膠片240,而與該第一晶片220與該第二晶片230為Z字堆疊。詳細而言,該晶片組490係由複數個晶片所組成,其中該些晶片、該第一晶片220與該第二晶片230係可為實質相同,而具有相同尺寸與功能之半導體晶片。該晶片組490的晶片堆疊方式可與該第一晶片220與該第二晶片230的階梯狀堆疊方式相同。在本實施例中,該耐熱絕緣膠片240係可彎曲地貼附至該些晶片之主動面,並藉由該些塗畫導線250完成該些晶片之間的電性連接。更進一步地,該晶片組490係可藉由一黏著層491黏合至該第二晶片230之該第二主動面231上。此外,可另包含複數個打線形成之銲線441與442,其中該些銲線441係電性連接該些第一銲墊222與該基板210之複數個接指211。該些銲線442係可電性連接該晶片組490之銲墊與該些接指211。因此,該耐熱絕緣膠片240可不必延伸至該基板210,能減少該些塗畫導線250的塗畫長度,每一晶片組所使用的耐熱絕緣膠片可具有相同長度,並且每一晶片組能先完成晶片堆疊與塗畫出導線之後,再電性連接至該基板210。此外,能避免因晶片與基板間應力影響而導致該耐熱絕緣膠片240的坡度改變。
依據本發明之第四具體實施例,另一種多晶片堆疊構造舉例說明於第7圖之截面示意圖。該多晶片堆疊構造500係主要包含一基板210、一第一晶片220、一第二晶片230、一耐熱絕緣膠片240以及複數個塗畫導線250。其中與第一實施例相同的主要元件將以相同符號標示,不再詳予贅述。
請參閱第7圖所示,可另包含至少一打線形成之跨接銲線541,係連接該些第一銲墊222之其中之一與對應之第二銲墊232,並在俯視圖中與該些塗畫導線250之至少一個構成電絕緣性交錯,無銲線沖線(wire sweep)的短路問題。因此,可提供雙(多)層式晶片間電性連接,不會產生以往銲線交錯而短路之問題。在一較佳實施例中,一銲線542係可電性連接該第二銲墊232與對應之接指211,當無跨越該些塗畫導線250的必要,則能以另一塗畫導線取代該銲線542。在另一變化實施例中,亦可利用該些塗畫導線250順著該第二可塗畫斜坡244以連接該第二銲墊232與對應之接指211。也就是說,在本實施例中,可藉由該跨接銲線541與該塗畫導線250之組合,依照實際產品需求而選擇與變更適當的電性連接方式,以達到最佳的電性連接品質。
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。
50...金線筆
100...習知的多晶片堆疊構造
110...基板
111...接指
120...上晶片
121...主動面
122...銲墊
130...下晶片
131...主動面
132...銲墊
151...銲線
152...銲線
153...獨立金球
170...封膠體
200...無線弧之多晶片堆疊構造
210...基板
211...接指
220...第一晶片
221...第一主動面
222...第一銲墊
230...第二晶片
231...第二主動面
232...第二銲墊
240...耐熱絕緣膠片
241...可塗畫斜坡
242...第一閉孔
243...第二開孔
244...第二可塗畫斜坡
250...塗畫導線
260...填充材
270...封裝體
300...無線弧之多晶片堆疊構造
310...基板
311...接指
341...可塗畫斜坡
380...第三晶片
381...第三主動面
382...第三銲墊
400...多晶片堆疊構造
441...銲線
442...銲線
490...晶片組
491...黏著層
500...多晶片堆疊構造
541...跨接銲線
542...銲線
第1圖:為習知的一種有線弧之多晶片堆疊構造之截面示意圖。
第2圖:依據本發明之第一具體實施例的一種無線弧之多晶片堆疊構造之截面示意圖。
第3圖:依據本發明之第一具體實施例的無線弧之多晶片堆疊構造未封裝前之立體示意圖。
第4A至4H圖:依據本發明之第一具體實施例的無線弧之多晶片堆疊構造在製造過程中之元件截面示意圖。
第5圖:依據本發明之第二具體實施例的另一種無線弧之多晶片堆疊構造之截面示意圖。
第6圖:依據本發明之第三具體實施例的另一種多晶片堆疊構造之截面示意圖。
第7圖:依據本發明之第四具體實施例的另一種多晶片堆疊構造之立體示意圖。
50‧‧‧金線筆
210‧‧‧基板
211‧‧‧接指
220‧‧‧第一晶片
221‧‧‧第一主動面
222‧‧‧第一銲墊
230‧‧‧第二晶片
231‧‧‧第二主動面
232‧‧‧第二銲墊
240‧‧‧耐熱絕緣膠片
241‧‧‧可塗畫斜坡
242‧‧‧第一開孔
243‧‧‧第二開孔
244‧‧‧第二可塗畫斜坡
250‧‧‧塗畫導線

Claims (21)

  1. 一種無線弧之多晶片堆疊構造,包含:一基板;一第一晶片,係設置於該基板上,該第一晶片係具有一遠離該基板之第一主動面以及在該第一主動面上之複數個第一銲墊;一第二晶片,係設置於該第一晶片之第一主動面上但不完全覆蓋該第一主動面,以顯露該些第一銲墊,該第二晶片係具有一遠離該基板之第二主動面以及在該第二主動面上之複數個第二銲墊;一耐熱絕緣膠片,係彎曲地貼附至該第一主動面與該第二主動面,並在該第一主動面與該第二主動面之間提供一可塗畫斜坡;以及複數個塗畫導線,係熔附於該耐熱絕緣膠片上,該些塗畫導線係順著該可塗畫斜坡以連接該些第一銲墊與對應之該些第二銲墊。
  2. 根據申請專利範圍第1項之無線弧之多晶片堆疊構造,其中該些塗畫導線係由一金線筆塗畫形成。
  3. 根據申請專利範圍第1項之無線弧之多晶片堆疊構造,其中該耐熱絕緣膠片係具有複數個第一開孔與第二開孔,以分別顯露該些第一銲墊與該些第二銲墊。
  4. 根據申請專利範圍第3項之無線弧之多晶片堆疊構造,其中該些塗畫導線係延伸至該些第一開孔與該些第二開孔,以分別熔附於該些第一銲墊與該些第二銲墊。
  5. 根據申請專利範圍第1項之無線弧之多晶片堆疊構造,其中該耐熱絕緣膠片係更延伸至該基板,並在該第一主動面與該基板之間提供一第二可塗畫斜坡。
  6. 根據申請專利範圍第5項之無線弧之多晶片堆疊構造,其中該些塗畫導線係順著該第二可塗畫斜坡以連接該些第一銲墊與該基板之複數個接指。
  7. 根據申請專利範圍第1項之無線弧之多晶片堆疊構造,另包含複數個打線形成之銲線,係電性連接該些第一銲墊與該基板之複數個接指。
  8. 根據申請專利範圍第1項之無線弧之多晶片堆疊構造,另包含至少一打線形成之跨接銲線,係連接該些第一銲墊之其中之一與對應之第二銲墊,並在俯視圖中與該些塗畫導線之至少一個構成電絕緣性交錯。
  9. 根據申請專利範圍第1項之無線弧之多晶片堆疊構造,另包含一填充材,係形成於該耐熱絕緣膠片與該第二晶片側的空隙內。
  10. 根據申請專利範圍第1或9項之無線弧之多晶片堆疊構造,另包含一封裝體,係形成於該基板上,以密封該第一晶片與該第二晶片。
  11. 根據申請專利範圍第1項之無線弧之多晶片堆疊構造,另包含至少一第三晶片,係設置於該第二晶片之第二主動面上但不完全覆蓋該第二主動面,以顯露該些第二銲墊,該第三晶片係具有一遠離該基板之第三主動面以及在該第三主動面上之複數個第三銲墊,並且該耐熱絕緣膠片係更延伸至該第三晶片之第三主動面,並在該第三主動面與該第二主動面之間提供另一可塗畫斜坡,並且該些塗畫導線係順著所述另一可塗畫斜坡以連接該些第二銲墊與該第三銲墊。
  12. 根據申請專利範圍第11項之無線弧之多晶片堆疊構造,其中該第一晶片、該第二晶片與該第三晶片係為階梯狀堆疊。
  13. 根據申請專利範圍第1項之無線弧之多晶片堆疊構造,另包含至少一晶片組,係設置於該第二晶片之第二主動面上,並局部壓附至該耐熱絕緣膠片,而與該第一晶片與該第二晶片為Z字堆疊。
  14. 一種無線弧之多晶片堆疊構造之製造方法,包含:提供一基板;設置一第一晶片於該基板上,該第一晶片係具有一遠離該基板之第一主動面以及在該第一主動面上之複數個第一銲墊;設置一第二晶片於該第一晶片之第一主動面上但不完全覆蓋該第一主動面,以顯露該些第一銲墊,該第二晶片係具有一遠離該基板之第二主動面以及在該第二主動面上之複數個第二銲墊;彎曲地貼附一耐熱絕緣膠片至該第一主動面與該第二主動面,並在該第一主動面與該第二主動面之間提供一可塗畫斜坡;以及形成複數個塗畫導線,其係熔附於該耐熱絕緣膠片上,該些塗畫導線係順著該可塗畫斜坡以連接該些第一銲墊與對應之該些第二銲墊。
  15. 根據申請專利範圍第14項之無線弧之多晶片堆疊構造之製造方法,其中該些塗畫導線係由一金線筆塗畫形成。
  16. 根據申請專利範圍第14項之無線弧之多晶片堆疊構造之製造方法,其中該耐熱絕緣膠片係具有複數個第一開孔與第二開孔,以分別顯露該些第一銲墊與該些第二銲墊。
  17. 根據申請專利範圍第16項之無線弧之多晶片堆疊構造之製造方法,其中該些塗畫導線係延伸至該些第一開孔與該些第二開孔,以分別熔附於該些第一銲墊與該些第二銲墊。
  18. 根據申請專利範圍第14項之無線弧之多晶片堆疊構造之製造方法,其中該耐熱絕緣膠片係更延伸至該基板,並在該第一主動面與該基板之間提供一第二可塗畫斜坡。
  19. 根據申請專利範圍第18項之無線弧之多晶片堆疊構造之製造方法,其中該些塗畫導線係順著該第二可塗畫斜坡以連接該些第一銲墊與該基板之複數個接指。
  20. 根據申請專利範圍第14項之無線弧之多晶片堆疊構造之製造方法,另包含之步驟為:形成一填充材於該耐熱絕緣膠片與該第二晶片側的空隙內。
  21. 根據申請專利範圍第20或21項之無線弧之多晶片堆疊構造之製造方法,另包含之步驟為:形成一封裝體於該基板上,以密封該第一晶片與該第二晶片。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109461715A (zh) * 2018-09-29 2019-03-12 南京中感微电子有限公司 一种多管芯封装体

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI467757B (zh) * 2013-08-02 2015-01-01 Chipbond Technology Corp 半導體結構
TWI467711B (zh) * 2013-09-10 2015-01-01 Chipbond Technology Corp 半導體結構
TWI582917B (zh) * 2015-07-29 2017-05-11 力成科技股份有限公司 以封膠體取代基板核心之多晶片封裝構造
CN107564877A (zh) 2016-06-30 2018-01-09 华邦电子股份有限公司 半导体元件封装体及半导体元件封装制程
TWI602250B (zh) * 2016-06-30 2017-10-11 華邦電子股份有限公司 半導體元件封裝製程
JP2021145084A (ja) 2020-03-13 2021-09-24 キオクシア株式会社 半導体装置
JP2021150567A (ja) * 2020-03-23 2021-09-27 キオクシア株式会社 半導体装置及びその製造方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637248A (ja) * 1992-05-26 1994-02-10 Motorola Inc 積み重ね半導体マルチチップモジュールおよびその製造方法
US5586006A (en) * 1993-08-12 1996-12-17 Fujitsu Limited Multi-chip module having a multi-layer circuit board with insulating layers and wiring conductors stacked together
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
JP2000269102A (ja) * 1999-03-15 2000-09-29 Rohm Co Ltd チップ型電子部品における焼成用治具の構造
TW411540B (en) * 1999-03-04 2000-11-11 Chipmos Technologies Inc Stacked MCM micro ball grid array package
US6207467B1 (en) * 1999-08-17 2001-03-27 Micron Technology, Inc. Multi-chip module with stacked dice
TW494554B (en) * 2001-07-16 2002-07-11 Taiwan Ic Packaging Corp Multi-chip stacking packaging method and the structure thereof
JP2004319775A (ja) * 2003-04-16 2004-11-11 Renesas Technology Corp 半導体実装構造および半導体パッケージ
TW200814260A (en) * 2006-09-15 2008-03-16 Powertech Technology Inc Micro BGA package having multi-chip stack
TW200905816A (en) * 2007-07-31 2009-02-01 Powertech Technology Inc Multi-chip stacked device with peripheral film-over-wire configuration
US7492039B2 (en) * 2004-08-19 2009-02-17 Micron Technology, Inc. Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637248A (ja) * 1992-05-26 1994-02-10 Motorola Inc 積み重ね半導体マルチチップモジュールおよびその製造方法
US5586006A (en) * 1993-08-12 1996-12-17 Fujitsu Limited Multi-chip module having a multi-layer circuit board with insulating layers and wiring conductors stacked together
US5899705A (en) * 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
TW411540B (en) * 1999-03-04 2000-11-11 Chipmos Technologies Inc Stacked MCM micro ball grid array package
JP2000269102A (ja) * 1999-03-15 2000-09-29 Rohm Co Ltd チップ型電子部品における焼成用治具の構造
US6207467B1 (en) * 1999-08-17 2001-03-27 Micron Technology, Inc. Multi-chip module with stacked dice
US6274930B1 (en) * 1999-08-17 2001-08-14 Micron Technology, Inc. Multi-chip module with stacked dice
TW494554B (en) * 2001-07-16 2002-07-11 Taiwan Ic Packaging Corp Multi-chip stacking packaging method and the structure thereof
JP2004319775A (ja) * 2003-04-16 2004-11-11 Renesas Technology Corp 半導体実装構造および半導体パッケージ
US7492039B2 (en) * 2004-08-19 2009-02-17 Micron Technology, Inc. Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
TW200814260A (en) * 2006-09-15 2008-03-16 Powertech Technology Inc Micro BGA package having multi-chip stack
TW200905816A (en) * 2007-07-31 2009-02-01 Powertech Technology Inc Multi-chip stacked device with peripheral film-over-wire configuration

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109461715A (zh) * 2018-09-29 2019-03-12 南京中感微电子有限公司 一种多管芯封装体

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