TW494554B - Multi-chip stacking packaging method and the structure thereof - Google Patents

Abstract

The present invention relates to a multi-chip stacking packaging method and the structure thereof, which includes the following steps: using the leadframe without the die and with attached film on single side to make the first chip adhering on the film or below the finger from one side of the leadframe; after electrically connecting the first chip with the leadframe, encapsulating the leadframe from one side; next, removing the film, and adhering the second chip on the back of the first chip or the encapsulation from the other side of the leadframe; after electrically connecting the second chip with the leadframe, conducting the single-side encapsulation for the other side of the leadframe to form a semiconductor device in a multi-chip stacking package. With this design, the thermal stress of the device during manufacturing can be reduced, and the adhesion can be increased to prevent from cracking or fracturing; and, with the design for encapsulating individual chips twice to prevent the problem of short circuit by metal wires contacting caused by reversing the device, so as to improve the product yield.

Description

A7 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (This invention relates to a multi-finger-type product that can effectively improve the product system: the method and structure of the car, the method of stacking tablets and its structure Material ^ 'Industrial Hunan Polycrystalline: Known multi-chip stacked packaging methods, such as:

What is not shown in the picture and the annex I. The princess + the sibling one Λ-C package "invention patent slaughter reveals the number 2392-" the stacking of wafers. The multi-chip stack is the most sealed / the third one in the case. The wafer shown in Figure C is taken from the first crystal. It is a wafer that is cut into a plurality of) a 之 ρ Γ 7 〇 6) with its backside adhered to the lead frame (7 〇) positive: upper = long 41 ) —Side side, the inner chip of the first chip (60 each pad and lead frame (70)) (metal link = ,: person: take the second chip (61) on the back with metal wires attached to the wire On the other side of the bracket (7 1), metal pads are used to connect the second wafer (Q ,, 1 on the front surface 1 with the pads (7) within the lead frame (70), continued with- The sub-double-side sealing method combines the first and second wafers (60) (6lf) on both sides of the lead frame (7Q) to form a -multi-chip stacking type semiconductor element structure. As for the wafer stacking that can not be uncovered in attachment one The package structure design generally includes two embodiments, one of which, as shown in the second figure of Annex I, uses a lead frame 51 in which the inner pin 500 is bent downward, and the pad is located in the middle. The first chip 310 is adhered to the inner lead 500 of the lead frame 51 in a face-down manner, and is connected to the first chip 31 with a first set of bonding wires 370a. Each pad of the lead chip 510 corresponds to the inner lead of the lead frame 510. Between 500 feet, the back of the first wafer 320 with the solder pads in the middle is adhered to the back of the first wafer 310, and then a second set of bonding wires 370b are connected to each pad 320 and the lead frame of the second wafer 320. Paper size applies to China National Standard (C, NS) A4 (210 X 297 mm)

-------- Order --------- Line »· (Please read the precautions on the back before filling this page) 494554 A7

(Please read the precautions on the back before filling this page) r -------- Order --------- line »· 5. Description of the invention (3) 2 Heli 'and the internal stacking The first and second wafers and components themselves are prone to turtles and cracks. ^ It is easy to produce shorts due to short-circuits between adjacent metal wires: front uncovered: multi-chip stacked package structure 'is used to adhere the chip to the lead frame, with metal:-connected, first: ¾ between the pad and the inner lead , And then flip the lead frame, stick the 7-Yue piece on it, and connect the solder pad to the inner pin with a metal wire,

The overall sealing process of Si, where 'because the metal wire has a small wire diameter and the gap between the f wires is small, the side chip metal wire is connected to the pin, and the side is bonded to the aa and the metal wire connection is reversed. In the process, the metal wires are likely to be biased and the metal wires are in contact with each other and short-circuited, causing the completed package to become scrap. Therefore, there is a known multi-chip stacked package design in the past. The poor bonding force and the problem of the metal wire's susceptible to off-center contact and short circuit provide effective solutions. The present inventors devised a "multi-chip stacked packaging method and structure", and hoped to fully solve the above problems. The problem of poor bonding force and easy short-circuit of metal wires, and the yield of 1 liter product are the main objects of the present invention. In order to achieve the purpose of the previous disclosure, the multi-chip stacked package design structure proposed by the present invention uses ^ spring wood without a chip holder and a single-sided adhesive film to provide a first chip adhered to the film from the lead frame side. Or internal lead: the next if a chip is electrically connected to the lead frame, 'single-sided sealing of the lead frame ^, one person', then remove the diaphragm, and adhere the second chip from the other side of the lead frame to the back of the first chip or the gel After the second chip is electrically connected to the lead frame, the other side of the lead frame is sealed on one side, and a multi-chip stacked package is formed. This paper size is applicable to China National Standard (CNS) A4 ii ^ · 297 mm) Fifth, the invention description (¥), the semiconductor element, by this design, to reduce the thermal stress of the element during manufacturing, improve its bonding force to avoid cracks, cracks, etc., at the same time by twice the design of the sealing of each wafer, Avoid the problem of metal wire contact short circuit due to component flipping during the process to improve its product yield. In order to enable your review committee to further understand the specific design and other purposes of the present invention, a detailed description is attached as follows: (I) Schematic part: The first A to D diagrams are schematic diagrams of the packaging process of the present invention. . FIG. 2 is a schematic cross-sectional view of an m-seal piece according to another embodiment of the present invention. The schematic diagram of the packaging process of the third K-mem multi-wafer stack structure. (2) Part of drawing number: (10) Lead frame (1 2) Adhesive diaphragm (1 4) Second side (2 0) First wafer (30) First absent body (4 0) Second wafer (50) The second gel (60) The first chip (70) The lead frame (72) The pins (80) The gel (III) Attachment part: Please read the notes on the back, and then fill in this page IIIII Order (1 1) Leads (1 3) The first side (1 5) The gap (21) The metal wire (41) The metal wire (61 (71 The second wafer holder sheet line I 6 This paper is suitable for 1+ five 、 Explanation of the invention (t), Announcement of the Announcement No. 439,924 Interest Case No. "Chip Stack Package" Invention 4 For the first embodiment of the multi-chip stack package of the present invention, please refer to the first method. In two specific implementations, you cut the wafer into multiple wafers. What D does not include includes providing the first side of the leadframe (10) with only multiple pins (the leadframe (1〇), the 2 ), And the inner pins (two sticky: there are adhesive membranes (1 space (1 5) · 4 openings ^ vacant area of the valley chip ηΓ a wafer (20) from the lead frame (10)) Two sides (1 4) are attached to the adhesive membrane ( 12), relative to the inner material section (15), such as _Αβ ^; connected by metal wires between each pad of the first chip (20) and its corresponding pin (1 1); to the lead frame (1) The second side surface (14) of the first wafer (1 3) is adhered for single-sided sealing, and the colloid (30) covers the first wafer (20), as shown in the first B picture. As shown in the figure;. Remove the diaphragm (12) of the lead frame (10); the second chip (40) is insulated from the first side (work 3) of the lead frame (10) and is bonded to the first chip (2) On the back, as shown in the first c figure, each pad of the second wafer (40) is connected with a corresponding wire (1 1) by a metal wire;. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Please read the note of S first printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

494554 A7

The first cross-section (1 3) of the lead frame (10) with the second chip (4Q) is sealed on one side, and the second chip ('0) is covered by the gel (50), as shown in the first One! ) As shown in the figure; Before the wafer is cut into a plurality of wafers, grinding may be performed on the back of the wafer to reduce the thickness of the wafer; the lead frame (10) is provided with the second side (1 4) of the first wafer (2) of the wafer; Sealing plastic | can be used to continue the straightening step of the body, with curvature to facilitate subsequent adhesion of the second crystal 4 (4 〇) and the second aforementioned adhesive film (i) adhered to the side of the lead frame (10) 2) Polyethylenimide film can be used. After the gel (30) (50) is fixed to the lead frame (10), it can be exposed to the gel (3 〇) before cutting and forming. ) (50) The outer pins (χ 丄) are plated. The semiconductor device structure manufactured by the aforementioned packaging method is shown in the first D diagram, and includes: a lead frame (10), which has only a plurality of pins (丄 丄), and corresponding inner pins ( 1 1) forms a gap (1 5); the first chip (20) has a plurality of pads on the front side, and is provided on the special wire frame (1 0) relative to the gap (区间 5) _ side, which Each pad on the front side is electrically connected by a lead (1 1) corresponding to metal, wire (2 1) and lead frame (work 0); the first gel (3 〇) is opposite to the lead frame (1 〇.) With the first 8 paper sizes applicable to China National Standard (CNS) A4 specifications (210 X 297 public love one

-------- Order ------ (Please read the notes on the back before filling this page) _ · Thread ^^ 54 A7 B7 V. Description of the invention (printed by the member of the Intellectual Property Bureau of the Ministry of Economic Affairs) The side of the piece (20) is covered with a single-sided sealant around the first chip (20), the front surface, and the metal wire (1 1) connected between the pad and the lead frame (丄 〇) pins (1 1). 2 1); a second wafer (40), which has a plurality of pads on its front surface, and is disposed on the lead frame (1 0) relative to the gap (区间 5), and its back surface is on the f-side of the first wafer (20) The relative bonding pads on the front face are electrically connected by metal wires (4 D corresponding to the lead frame (1Q) and the legs (11); and S-the second gel (50)) is the opposite lead frame ( 1〇) The side of the second chip (40) is covered with a single-side sealant on the second chip, " 〇) outside and connected between the pad and the lead frame (丄 Q) pins (丄 丄). Metal wire (41) 'and constitute a semiconductor element structure of a multi-chip stacked package;-The aforementioned-(20) and second (40) wafers can be of the same size, and can have the same function Wafers with different functions The aforementioned second wafer (4 ()) f surface is adhered to the back of the first wafer (20) with an insulating adhesive or a mucous membrane; the aforementioned first colloid (30) and osmium-thief oxygen resin; ㈡ And the first-the colloid (50) contains the lead wire (10), the outer pin (1 1) protruding from the outside of the colloid can be plated on both sides with silver, brocade, free, gold or other highly conductive metals物 Ϊ, This issue: The second embodiment of the multi-chip stacked packaging method, where you ... …… I · The example is the same, the difference is that the inner leads of the wire lead frame are bent sideways and the first One wafer under the wafer 9 paper standards are applicable to 1 home standard (CNS ^^^ ⑵Q χ 297 公 ^ 494554

The LEAD 0N CHIP (Loc) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs includes: cutting the wafer into a plurality of wafers; providing a lead frame with only complex feet, and the lead frame The first upper part is adhered with an adhesive membrane, and the inner bow 丨 Lianda Rifan Traveling Feet μ is bent laterally to the outside of the two sides of the younger brother, and there is a height difference between the lead frames; It is set on the bottom surface of the inner lead protruding from the second surface of the lead frame; it is connected between each welding pad of the first chip and its corresponding pin with a metal wire; The side sealant covers the first chip inside; removes the adhesive film on the first side of the lead frame, and glues the second chip to the gel from the first side of the lead frame; connects to the u through a metal wire Each material is connected to its pair of metal wires; | 1 π w # One side of the second wafer is bonded to the lead frame to seal the second wafer inside, and the second wafer is covered inside; Semiconductor devices in stacked packages. Before the wafer is cut into a plurality of wafers, the backside of the wafer may be ground first to reduce the thickness of the wafer. After the aforementioned sealing is performed on the outer side of the second side of the first wafer of the lead frame, a shape correction step may be performed. To reduce the warpage of the body to facilitate the adhesion of the next two wafers and the second sealing; only the aforementioned film can be a polyethylene film; the foregoing is relatively cut after the gel is fixed to the lead frame The size of the formed paper is applicable to China National Standard (CJMS) A4 (210 X 297 mm)

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, Can be exposed to the outside of the colloidal pins for electricity treatment. As shown in the second figure, the semiconductor device structure manufactured by the foregoing packaging method includes a lead frame (10), which has only a plurality of pins (丄 丄), and the inner pins (1 1) are formed toward It is bent down and has a low difference with the wire 帛 (丄 0). A first chip (20) is provided with a plurality of pads at the middle position on the front side and is adhered to the inner side of the lead frame (丄 〇) with the front side. The bottom surface of the chat (丄 丄), each pad on the front side is electrically connected with the corresponding pin (⑴) by a metal wire (2 1); a first gel (30), which is opposite to the lead frame (丄 〇); The side of a wafer (20) is covered with a single-side sealant on the outside of the first wafer (20); a second wafer (40) is provided with a plurality of solder pads on the front side, and the backside is adhered to a lead frame ( 1 〇) on the first colloid (30) at the middle position relative to the inner pin (i 丄), each of the fresh pimple on the front side is electrically connected by the metal wire (41) and the lead corresponding to the lead frame (1 0); And • a second colloid (50), which is covered with a second chip (40) on the side of the lead frame (丄 〇) by a single-side encapsulation on the second crystal (40) outside and the semiconductor elements constituting the structure of more than one chip stack package. The back of the second wafer (40) is adhered to the first gel (30) with an insulating adhesive or a mucous membrane; the first wafer (20) and the second wafer (40) may be equal in size or Different types, can also be the same or different functions of the chip; π paper size thorn + family standard (CNS) A4 specifications (21〇 \ 297 public love (please read the precautions on the back before filling in this (Page)-------- 1 --------- Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 494554 V. Invention Description (Production) Description Metals and wires connected between the first wafer (20) pads and the leads (1 1) in the lead frame (10), and connected to the second wafer (40) and the lead frame (10) The metal wire () between the inner pins (1 1) is a gold wire; the aforementioned first gel body (30) and the second gel body (50) contain epoxy resin; the aforementioned lead frame (10) extends out of the gel body (3) 〇) (50) The outer pins (1 1) on the outside can be silver, nickel, handle, gold or other conductive metal objects on both sides. Through the aforementioned packaging method and structure In the manufacturing process, the following advantages can be produced: 1. Reduce thermal stress and improve bonding force. The invention can make the chip not directly adhere to the lead frame or reduce the chip directly adhere to the lead frame, which can effectively improve the sealant. At the same time, due to the different thermal expansion coefficients of the various components, the thermal expansion and contraction ratios of the components are different. This reduces the internal thermal stress of the components, thereby increasing the bonding force between the components, and improving the cracking and cracking of the components. Yield rate 2. To avoid the formation of scraps due to short-circuiting of adjacent metal wires ... The present invention is to adhere the chip on one side of the lead frame and connect the metal wire, then perform the sealing on that side, and then adhere the other side of the lead frame. Chips, metal wires are connected and sealed. Therefore, the design of the two-sided single-side sealing method can avoid the habit of using a single sealing process. When the semi-finished product is turned over, the metal wires are offset and contact the adjacent metal wires. The short-circuit problem occurred to improve the product yield of the multi-chip stacked package structure. 12

-------- ^ --------- (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (qMS) A4 (210 X 297 public love) 494554 A7 V. INTRODUCTION OF THE INVENTION _ In summary, the innovative multi-chip stack design of the present invention can indeed improve the design of the _ * method and the use of the potential latent / / car-type chip stack package design is more "Zhutu Ming 'therefore" this invention complies with the requirements of the invention patent, | filed an application in accordance with the law. -------- Order --------- Line (Please read the notes on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 13 This paper size applies to Chinese national standards (CNS) A4 size (210 X 297 male)

Claims (1)

Sixth, the scope of application for patents 1. A multi-chip stacked packaging method, which includes: dicing a wafer into a plurality of wafers; providing a lead with only a plurality of pins plus m ^ Mk m ， Adhesive cymbals are attached on one side, and are relatively internally guided. 丨 A gap for receiving the wafer is formed between the feet. The first chip is from the lead frame to the gap between the inner pins. The on-chip phase is connected by metal wires between the pads of the first chip and its corresponding pins; the cage of the first chip is glued to the lead frame-the first chip is wrapped inside; the side is sealed on one side Glue, the film of the lead frame will be removed; the second chip will be insulated from the first side of the lead frame and adhered to the first chip; the solder pads on the second chip and the corresponding pins will be connected by metal wires; The first side of the day-to-day wafer of the first-chip Chu Lingdi is glued for single-sided sealing, covering the first wafer inside; and cutting and forming to complete a semiconductor device with a multi-chip stacked package. 2. If you apply for a special “Wait-like multi-chip stacking seal =”, where the adhesive film adhered to the side of the lead frame can be made of polyethylenimine I____ 14 This paper standard is applicable to the Tukazuka standard (CNSM1 2 regulations) Café 297 public housing CPlease read the notes on the back before filling this page) Order --------- line | _ 丨 ---- # 1 If so, please ask for the scope of patent! Or the multi-chip stacking method according to item 2, wherein the aforementioned step of applying shape correction is performed after sealing the outer side of the second side of the first wafer of the lead frame. Seal 2 The multi-chip stacked package method described in item 3 of the patent application 494554 and the patent application method, wherein after the colloid is sealed in the lead frame, it can be exposed to the outside of the colloid relative to the shape before cutting. The foot performs key processing. 5. The multi-chip stacking and packaging method described in item 4 of the scope of the patent application, wherein the wafer can be polished on the backside of the wafer before cutting the wafer into multiple wafers to reduce the thickness of the wafer. 6. A multi-chip stacked package structure, comprising: a lead frame having only a plurality of pins with a gap formed in the center; a first chip having a plurality of pads on the front side and a lead frame on the back side One side corresponds to the center of the empty section, and each pad on the front side is electrically connected with the corresponding pin by a metal wire; a first gel, which is packaged in a single side with respect to the side of the lead frame with the first chip The first wire covers the periphery of the first chip and the metal wires connected between the pads and the lead of the lead frame; the first one is a piece of film, the front side of which does not have a plurality of tees, and the back side is provided on the other side of the lead frame to correspond to the gap. In the center, the backside is bonded to the backside of the first chip with wires, and the corresponding pads on the front side are electrically connected with metal wires by a wire; and a second gel is provided with the second chip opposite the leadframe. The side surface is covered with a single-side sealant on the outside of the second chip and the metal wires connecting the solder pads and the lead frame pins to form a multi-chip stacked package semiconductor element. 7. The multi-chip stacked package structure described in item 6 of the scope of patent application, wherein the back surface of the second chip is adhered to the back of the first wafer with insulating adhesive 8. The multi-chip stack described in item 6 of the scope of patent application The size of the package paper is suitable for the National Standard (CNS) A4 specification (210 15 X 297 mm). Scope 6. Patent application structure 4 ”1 ^ The backing is adhered to the back of the chip with insulation '9. The 6th and 7th stacked package structure of the patent, in which the multi-wafer degreasing described in the aforementioned item No. == 8. The body and the first colloid contain the metal of epoxy resin before the outer lead of the colloid is drawn out by one line. A double-sided mineable conductive 11. A multi-chip stacked packaging method including: cutting a wafer into a plurality of wafers; an upper spot ΓΓ having only a lead frame with a plurality of pins, and the first side of the lead frame is adhered with adhesiveness Diaphragm, the inner pin is deaf. There is a difference in height between the lead frames. The side of the side is bent laterally, and the first chip is glued to the inner lead of the lead frame protruding from the second side. Bottom surface; connected to the first chip by a metal wire Between the solder pad and its corresponding pin; — One-side sealing of the second side of the lead frame with the first chip, printed by the member of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative, covering the first chip; Adhesive film on the first side of the frame. The second chip is glued to the gel from the first side of the lead frame. The metal chip is connected to each of the solder pads of the second chip and their corresponding pins with metal wires. The lead frame is bonded to the second side of the second chip for single-sided sealing, and the second chip is covered inside; and 16 paper sizes are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 494554 A8 B8 C8 D8 Scope of patent application Cutting and forming to complete the multi-chip stacked package of semiconductor components. (Please read the precautions on the back before filling this page) I2 is the multi-chip stacking and packaging method described in item 丄 1 of the patent application scope, where the adhesive film adhered to the side of the lead frame can be a polyethylene film. 13. The multi-chip stack packaging method as described in item 11 or 12 of the patent scope, wherein the aforementioned step of shape correction can be applied after sealing the outer side of the mth second side of the lead frame. 14. The multi-chip stacking and packaging method described in item 13 of the Chinese Patent Application, where “the wafer may be ground on the back surface of the wafer before being cut into multiple wafers” to reduce wafer thickness. 1 5 The multi-chip stacked packaging method described in item 4 of the Chinese Patent Application, wherein the lead can be exposed to the outside of the knee after the lead frame is closed before the cut and formed, as compared with the lead before cutting. Electro-forged. 16. A multi-chip stacked package structure, comprising: ¥ wire wood, which has only a plurality of pins, wherein the inner pins form a downward bent shape, and the height difference between the pins and the lead frame; a first chip, the front side A plurality of solder pads are arranged in the middle position, and the printed surface of the employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is glued to the bottom surface of the lead in the lead frame. Each pad on the front side is electrically connected to the corresponding pin by a metal wire; A first colloid is coated on the outside of the first wafer with a single-side sealing method on the side of the first wafer with respect to the lead frame; the first piece is provided with a plurality of pads on the front side, and the back side is adhered to the inner side of the lead frame. On the first gel at the middle position of the pins, each pad on the front side is electrically connected with the corresponding lead of the lead frame by a metal wire; and the 17 K paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 male) Fifth, the scope of the patent application of the first gel, is relative to the lead frame | encapsulation method to cover the second chip ^ side of the first chip with a single-sided semiconductor components. Form a multi-chip stack package 17 7. Such as Application The 6th structure of the scope of interest, in which the first and second films are stacked and sealed.… The surface is adhered to the first colloidal welder 18 with insulating dots, as described in item 16 of the scope of patent application. Polycrystalline m-packed structure, in which the first-day Hγ Yizhi day and day-chip pile is sealed vertically. The first-day moon surface is adhered to the first colloidal multi-chip 1 with an insulating mucosa. 92. The scope of patent application is 16th. , 17 or 1㈣ ㈣ structure, in which the first-colloid and the second "contains .20, the multi-chip stacked package structure as described in item 29 of the patent application scope, where the lead frame protrudes outside the colloid can be doubled. The surface is plated with a conductive metal. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs