1251887 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種無導線架之晶片封裝製程，特 指一種免用導線架即能使裸晶片具有可對外電性導接 功能，而可組裝於電路板等設備應用之晶片封裝製程設 計。 口又 【先前技術】 傳統的晶片封裝結構如第七圖所示，係具有一金屬 質導線架10，該導線架1 〇係為兩侧或四周採以沖壓出複 數片狀引腳101所排列構成，各個引腳1〇1下端沖設有 凸塊102 ’藉以该凸塊1 〇2端面1 〇3作為對外導電部位 ，而導線架10之引腳101上方係貼覆有一黏性膠帶2〇, 於該膠帶20固定有一裸晶片30,藉此，並於該裸晶片 3 0與各引腳101間設有一構成電性連接之金屬線4 〇，且 在金屬線40連接完成後，實施有一絕緣性封膠體密封 住晶片30周圍及導線架1〇底面，僅預留所述該引腳’ 〇1 之下端面103外露，可與電路板組裝形成電性連接應用 〇 上揭習知的晶片封裝結構之製程，通常包括（A)晶 圓切割（Die Saw)，將晶圓切割分離為複數裸晶片3〇 。（B)銲晶（Die Attach )，將切割完成的裸晶片3〇放置 在^^線架10上面’並使用黏性膠帶20加以黏著固定。（c) 打線（Wire Bond)，將裸晶片30上的訊號接點以金屬 線40連接到導線架10的引腳1〇1内端。（〇)封膠（ )，即實施一絕緣性封膠體50密封住晶片30周圍及導線 架10。（E)切單成型，即以機器將導線架10及封膠體50 多餘的材料切除，並成型為獨立的一顆封裝晶片。 1251887 塵成ΐ述晶片封裝製对，該導線架另需使用金屬片衝 屋成型’而㈣技術的困難點在於精密度控n欠， f知該金屬線40焊接完成後’必須經過封谬體5〇密封製 其注入半融化的封夥體5〇過程中，經常發生損毀金 嚴線40或其訊號接點情形，因而生產許多瑕疫品，必須 =續檢測時使用高貴的儀器探測；可見，習知晶片封 凌製転不利於封裝成本及品管成本的降低。 【發明内容】 本I明主要目的，係在提供__種無導線架之晶片封 广氣程’特別指-種免用導線架，且不需經過打線製程 ’即能使裸晶片具有可對外電性導接功能之晶片封裝製 程’以達成封裝程序簡易’以及成本降低等效益。 〜依上述目的，本發明料線架之晶片封裝製程，並 貫施内容包括： 、 —JA)覆膠’係於裸晶片之訊號接點該面覆設一層接 1層’該接著膠層設有對應晶片訊號接點之内接窗口 7裸B曰片成唬接點經由接著膠層之内接窗口外露； (+B)上片，將内面設有複數金屬導線之固定層覆設 二妾著膠層’該@定層設有對應電路板訊號接點之外接 =^使金屬導線外端延伸於外接f 口處，而金屬導線 端係與裸晶片之訊號接點構成電性連接； (C) 植入導電體，於該固定層之外接窗口植入金屬 電體，令該金屬導電體與金屬導線外端構成電性連接 ’並露出於外接窗口處； (D) 切單成型’將多餘的接著膠層及固定層材料切 示，並形成單一顆封裝晶片； 、〜藉此，組成裸晶片訊號接點面依序設有一接著膠層 複數金屬導線及一固定層之封裝晶片，令金屬導線内 1251887 端延伸於㈣窗口與晶片訊號接轉觸，而外端延伸於 外接窗口與窗口中之導雪f垃網 π 囡Υ之蜍電體接觸，可利用該導電體盥雷 路板等設備作電性連接。 电蔽〃电 【實施方式】 茲依附圖實施例將本發明之結構特徵及其他之作 用、目的詳細說明如下·· 請參考第一圖至第三圖所示，本發明所為一盔 導線架之晶片封裝製程』，其結構係為一裸晶片丄之额^ 號接點11該面依序設有一接著膠層2、複數金屬導線3 及一固定層4等所組成，主要製程方法包括： (Α)覆膠，參閱第二圖及第三圖所示，係於裸晶片 1之訊號接點11該面覆設一層接著膠層2，該接著膠層 2設有對應裸晶片i訊號接點彳彳之内接窗口 21(如第二 圖所示），令裸晶片1訊號接點彳彳經由接著膠層2之内 接窗口 21外露；其中，所述覆設接著膠層2步驟，係可 於該裸晶片1切單後各別實施（參閱第四圖所示），或 可於該裸晶片1切單後，將數裸晶片1連續貼覆於一膠 帶材料之接著膠層2上實施完成（參閱第五圖所示）， 或可在該裸晶片1切單前，即於晶圓彳〇狀態時預先覆設 所述該接著膠層2 (參閱第六圖所示）；另者，該接著 膠層2構成方式係包括可應用膠帶材料之貼覆方式，或 以树脂、矽膠等材料之塗設方式達成，其塗設方式包括 可為網屏印刷法（Screen )、點膠法（Dispe )、薄膜製 程（film)及模型塑造法（M〇|d)等，並可經過烘烤程 序，使該接著膠層2凝固； (B)上片，參閱第二圖及第三圖所示，將内面設有 複數金屬導線3之固定層4覆設於接著膠層2外面，該 固定層4係預設有對應電路板接點之外接窗口 4彳，使金 1251887 屬導線3之外端32延伸於外接窗口 41處，而金屬導線3 之内端31係與裸晶片1之訊號接點μ構 2，所述覆設固定層4步驟，係可於該裸晶片1切單狀 悲f別實施（參閱第四圖所示），或可於複數裸晶片丄 連續貼覆於-膝帶材料之接著勝層2之後實施完成（參 閱第，圖所示），或可在該裸晶片2切單前，即於晶圓 1〇狀態覆設所述該接著膠層2之後實施完成（參閱第六 圖所示”另者’該固定層4構成方式包括可為一樹脂 膜内面黏設有複數金料線3,再令該樹脂膜黏著於接 者膠層2外面，其後並可經過供烤程序，使該固定層4 植入導電體，參閱第 圃至第四圖所示，即於 之外接窗口 41植人金屬材f導電體5,令該 2體5與金屬導線3之外端32部構成電性連接，並令 :連於外接窗口 41處，可與電路板等設備作電 為所述該導電體5之構成方式，係包括可 為植入錫球或注入錫膏方式達成； 材料：刀單成型’即將多餘的接著膠層2及固定層4 材枓切除，並形成個別獨立的單-顆封裝曰片. 藉上述（A)覆膠、（B)上片 導aa ’ =型等製程步驟，即組成本發明：二 之成唬接點11面依序設有一拣荽 3及一固定層4之封裝:二=及=屬導線 :令該金屬導線3内端31延伸於内-？不) 導線3外端32係延伸= 口41與自口中之導電體5接觸， 因 路板等設備作f性連接。 μ t體5與電 請參閱第四圖所示，本創作該固㈣4亦可於對應 1251887 接著層2之内接窗口 21處預開設有内接窗口42,藉此可 於該内接窗口 42中實施上揭（C)植入導電體製程，俾使 複數導線3之内端31與裸晶片1訊號接點彳彳構成穩固 電性連接狀態。 ~ 運用本發明所揭無導線架之晶片封裝製程技術，其 明顯已免除傳統導線架結構，故可避免傳統導線架衝壓 、裁切等製程中品質難以難精確掌控等缺憾，以降低使 用導線架之材料成本以及品管成本等；並因本發明晶片 封裝製程不需使用導線架，即可使整體晶片封裝結構更 臻輕薄，以符合時下電子產品精巧化設計趨勢，^拎進 ，一晶圓所能切割出的裸晶片丄產量。其次，本發^該 複數導，3係可預先黏著於固定層4，再令固^層4貼 覆於接著層2使複數導線3固定，該複數導線3於製程 中不必承受傳統封膠體灌注之壓力及衝擊力等，不僅 改善傳統打線後封膠體封裝程序所造成的損害，進一牛匕 有效提升aa片構I之良品率，並能因此簡化晶片封 ===步驟)，俾有效降低封裝成本及後續 已確：本發明『無導線架之晶片封裝製程』， f性與創作性，其手段之運用亦出於新穎益疑 :且功效舁設計目的誠然符合，已稱合理 此，依法提出發明專利申請，惟懇請釣局惠予^為 並賜准專利為禱，至感德便。 【圖式簡單說明】 ί:=ίΓί片封裝製程之實施步驟示意圖。 第-θ為太Γ月晶片封裝狀態之縱向斷面示意圖。 =二=本發明晶片封裝狀態之橫向斷面示咅二 弟四圖為本發明裸晶片切單後之封裝結;;解圖示 1251887 意圖。 第五圖為本發明複數裸晶片切單後之封裝結構分 解示意圖。 第六圖為本發明裸晶片於晶圓狀態之封裝結構分 解示意圖。 第七圖為習知晶片封裝結構之斷面示意圖。 【主要元件符號說明】 覆膠（A); 植入導電體（C); 裸晶片1 ; 訊號接點11 ; 内接窗口 21 ; 内端31 ; 固定層4 ; 内接窗口42 ; 上片（B); 切單成型（D); 晶圓1 0， 接著膠層2 ; 金屬導線3 ; 外端32 ; 外接窗口 41 ; 導電體5 ;1251887 IX. Description of the Invention: [Technical Field] The present invention relates to a chip packaging process for a leadless frame, and particularly relates to a free lead frame which enables the bare chip to have an external electrical conduction function and can be assembled. Chip package process design for device applications such as circuit boards. [Background] The conventional chip package structure, as shown in the seventh figure, has a metal lead frame 10, which is arranged on both sides or all sides by punching out a plurality of chip pins 101. The upper end of each pin 1〇1 is punched with a bump 102' by which the end face 1 〇3 of the bump 1 〇2 is used as an external conductive portion, and the pin 101 of the lead frame 10 is pasted with an adhesive tape 2〇. A bare die 30 is fixed on the tape 20, and a metal wire 4 构成 electrically connected between the bare die 30 and each of the leads 101 is disposed, and after the metal wire 40 is connected, The insulating sealing body seals around the wafer 30 and the bottom surface of the lead frame 1 , and only the end surface 103 of the lead ' 〇 1 is exposed, and can be assembled with the circuit board to form an electrical connection. The process of packaging structure usually includes (A) Die Saw, which separates the wafer into a plurality of bare wafers. (B) Die Attach, the cut bare wafer 3 is placed on the top of the wire frame 10 and adhered using an adhesive tape 20. (c) Wire Bond, connecting the signal contacts on the bare chip 30 to the inner end of the lead 1? of the lead frame 10 by a metal wire 40. (〇) Sealing ( ), that is, an insulating sealing body 50 is implemented to seal around the wafer 30 and the lead frame 10. (E) Cutting and forming, that is, the machine removes the excess material of the lead frame 10 and the sealing body 50, and forms a separate package wafer. 1251887 Dust into a wafer package, the lead frame needs to be formed by metal sheeting, and (4) The technical difficulty lies in the precision control n owing, f know that the metal wire 40 must be sealed after the welding is completed. 5〇 Sealing the process of injecting the semi-melted slab 5 〇 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The conventional chip sealing system is not conducive to the reduction of packaging cost and quality control cost. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a radiant wafer holder with a wide range of lead-free lead frames, and to provide a lead-free process without the need for a wire-drawing process. The electrical packaging function of the chip packaging process 'to achieve a simple packaging process' and cost reduction and other benefits. According to the above purpose, the wafer packaging process of the wire rack of the present invention includes: -, JA) is coated on the signal contact of the bare chip, and the surface is covered with a layer of 1 layer. There is an internal window corresponding to the chip signal contact. The bare B-shaped contact is exposed through the inner window of the adhesive layer. (+B) The upper piece is covered with a fixed layer of a plurality of metal wires on the inner surface. The adhesive layer 'the @ fixed layer is provided with the corresponding circuit board signal contact external connection = ^ so that the outer end of the metal wire extends to the external f port, and the metal wire end is electrically connected with the bare chip signal contact; C) implanting an electrical conductor, and inserting a metal electric body into the window outside the fixed layer, so that the metal electrical conductor forms an electrical connection with the outer end of the metal wire and is exposed at the external window; (D) singulation molding The excess adhesive layer and the fixed layer material are cut and formed into a single package wafer; and thereby, the bare chip signal contact surface is sequentially provided with a plurality of metal layers and a fixed layer of the package wafer. The 1251887 end of the metal wire extends to the (four) window and Nan Υ π toad electrode signal then switch contact of the sheet, the outer end extending external of the window and the window guide web contacting snow f refuse, the device can be used as the electrically conductive plate connected to the gray mine passage. EMBODIMENT OF THE INVENTION The structural features and other functions and purposes of the present invention are described in detail below with reference to the accompanying drawings. Referring to the first to third figures, the present invention is a helmet lead frame. The chip packaging process, the structure is a bare chip ^ ^ ^ 接 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 Α), according to the second and third figures, the surface of the signal contact 11 of the bare wafer 1 is covered with a layer of adhesive layer 2, and the adhesive layer 2 is provided with a corresponding bare chip i signal contact. The inner window 21 (shown in the second figure) is such that the bare chip 1 signal contact is exposed through the inner window 21 of the adhesive layer 2; wherein the step of applying the adhesive layer 2 is The bare wafer 1 can be separately implemented after singulation (see the fourth figure), or after the bare wafer 1 is singulated, the bare dies 1 are successively pasted on the adhesive layer 2 of a tape material. The implementation is completed (refer to the fifth figure), or before the bare die 1 is cut, that is, in the wafer In the state, the adhesive layer 2 is pre-coated (refer to the sixth figure); in addition, the adhesive layer 2 is formed by means of a tape material, or a resin, silicone or the like. The coating method is achieved, and the coating method includes screen printing method, Dispe method, film processing method and model molding method (M〇|d), and can be subjected to baking process. (B) the upper sheet, as shown in the second and third figures, the fixed layer 4 having the plurality of metal wires 3 on the inner surface is disposed on the outer surface of the adhesive layer 2, the fixed layer The 4 series is pre-configured with a corresponding circuit board contact external window 4彳, so that the gold 1251887 is the outer end 32 of the wire 3 extending from the external window 41, and the inner end 31 of the metal wire 3 is connected to the bare chip 1 signal. The structure of the fixed layer 4 can be performed on the bare wafer 1 (see the fourth figure), or the plurality of bare wafers can be continuously attached to the knee band. The material is then completed after the layer 2 is completed (see the figure, as shown in the figure), or before the bare wafer 2 is cut, That is, after the wafer 1 is covered with the adhesive layer 2, the implementation is completed (refer to the sixth figure). The other embodiment of the fixed layer 4 includes a plurality of gold wires bonded to the inner surface of a resin film. 3. The resin film is adhered to the outside of the adhesive layer 2, and then the fixing layer 4 is implanted into the electrical conductor through a baking process, as shown in the fourth to fourth figures, that is, the external window 41 implanting a metal material f-conductor 5, so that the two-body 5 is electrically connected to the outer end 32 of the metal wire 3, and is connected to the external window 41, and can be electrically connected to equipment such as a circuit board. The structure of the electric conductor 5 can be achieved by inserting a solder ball or injecting a solder paste; the material: the single forming of the knife is to cut off the excess adhesive layer 2 and the fixed layer 4, and form an individual single sheet. - packaged cymbal. By the above (A) laminating, (B) upper film guide aa ' = type and other process steps, the invention is composed of: the second splicing point 11 faces are sequentially provided with a picking 3 and a The package of the fixed layer 4: two = and = is a wire: the inner end 31 of the metal wire 3 extends inside -? No) The outer end 32 of the wire 3 is extended = the port 41 is in contact with the electrical conductor 5 in the mouth, and the device such as the road plate is f-connected. Please refer to the fourth figure. The solid (4) 4 can also be pre-opened with an inscribed window 42 at the inner window 21 corresponding to the layer 2, which can be used in the inner window 42. The implementation of the above (C) implants the conductive process, so that the inner end 31 of the plurality of wires 3 and the bare chip 1 signal contacts 彳彳 constitute a stable electrical connection state. ~ The chip packaging process technology of the leadless frame disclosed by the invention has obviously eliminated the traditional lead frame structure, thereby avoiding the defects such as the difficulty in accurately controlling the quality of the conventional lead frame stamping and cutting, etc., so as to reduce the use of the lead frame. Material cost and quality control cost, etc.; and because the wafer packaging process of the present invention does not require the use of a lead frame, the overall chip package structure can be made thinner and lighter, in order to meet the current trend of electronic product compact design, ^ Jinjin, a crystal The output of bare wafers that can be cut by the circle. Secondly, in the present invention, the third series can be pre-adhered to the fixed layer 4, and then the fixing layer 4 is attached to the adhesive layer 2 to fix the plurality of wires 3, and the plurality of wires 3 do not have to withstand the traditional encapsulation in the process. The pressure and impact force, etc., not only improve the damage caused by the traditional sealing process after the sealing, but also improve the yield of the aa sheet I, and thus simplify the wafer sealing === step), effectively reducing the package Cost and follow-up have been confirmed: the invention of the "film-free package process without lead frame", f-type and creative, the use of its means is also novel and suspicious: and the effect, design purpose is true, it has been said to be reasonable, according to law Inventor patent application, but please ask the fishing bureau to give it a ^ and grant the patent as a prayer, to the sense of virtue. [Simple description of the diagram] ί:=ίΓί Schematic diagram of the implementation steps of the package process. The first-θ is a schematic longitudinal sectional view of the package state of the wafer. = two = the transverse section of the wafer package state of the present invention is shown in Fig. 2, which is the package of the bare wafer after the singulation of the invention; The fifth figure is a schematic diagram of the encapsulation structure of the package after the singulation of the plurality of bare wafers of the present invention. The sixth figure is a schematic diagram of the package structure of the bare wafer in the wafer state of the present invention. The seventh figure is a schematic cross-sectional view of a conventional chip package structure. [Main component symbol description] Laminating (A); Implanted conductor (C); Bare wafer 1; Signal contact 11; Inscribed window 21; Inner end 31; Fixed layer 4; Inscribed window 42; B); singulation (D); wafer 10, then glue layer 2; metal wire 3; outer end 32; external window 41;