1324377 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種堆疊式晶片封裝結構，特別一種利用導 電線路取代金屬銲線之堆疊式晶片封裝結構。 【先前技術】 按，半導體科技隨著電腦與網路通訊等產品功能急速提 昇，必需具備多元化、可攜性與輕薄微小化之需求，使晶片封 裝業必須朝高功率、高密度、輕'薄與微小化等高精密度製程 發展。 隨著微小化以及高運作速度需求的增加，多晶片封裝構裝 在許多電子裝置越來越常見。多晶片構造可藉由將兩個或兩個 以上之晶片組合在單一封裝結構中，來使系統運作速度之限制 最小化。常見之多晶片封裝結構為並列式（side-by-side)，其係 將兩個或以上之晶片彼此並排安裝於同一基板上。晶片與基板 上之線路一般藉由打線方式（wire bonding)來完成。然而並排式 多晶片封裝結構之缺點為封裝效率太低，因為基板之面積會隨 著晶>{數目增加而增加。 一種習知作法如第1A圖所示，第一晶片110設置於一基 板100上，並利用金屬銲線120與基板100電性連接，而一第 二晶片112利用一膠層130堆疊固定於第一晶片110上並利用 金屬銲線122與基板100電性連接。然，此種結構第一晶片 110之打線製程必須在第二晶片112堆疊前完成，亦即，每一 晶片之黏晶製程（die bonding)及打線製程都必須要分別進行， 因此將增加額外製程步驟。又，由於相鄰兩晶片（例第一晶片 110及第二晶片112)之間的空隙相當緊密，因此也限制了打線 作業的空間，因而影響銲線(bonding wires)的可靠度。 5 1324377 因此，另一種習知作法，請參考第1B圖，係在兩晶片（第 一晶片110及第二晶片112)之間設置間隔材料（spacer)l4〇且此 間隔材料140之高度需高於金屬銲線12〇線弧(the i〇〇ps 〇f the ponding wires)所需高度’此外，此間隔材料〗4〇需在打線作業 前預先設置於第一晶片110上，並避開第一晶片11〇之打線 區’但因此此種作法料成其後㈣模製財銲線線弧沖線 (wlre sweeping)f折；又’此種多晶片封裝結構之間隔材料⑽ 必須具有相當厚度才可改善第一晶片u◦打線問題，故在預定1324377 IX. Description of the Invention: [Technical Field] The present invention relates to a stacked chip package structure, and more particularly to a stacked chip package structure in which a metal wire is replaced by a conductive line. [Prior Art] According to the rapid advancement of products such as computer and network communication, the need for diversification, portability, and miniaturization of semiconductor technology must make the chip packaging industry have to be high-power, high-density, and light. High-precision processes such as thin and miniaturization. Multi-chip package fabrication is becoming more common in many electronic devices as miniaturization and increased operational speed requirements increase. Multi-wafer construction minimizes system operating speed limitations by combining two or more wafers in a single package. A common multi-chip package structure is side-by-side, in which two or more wafers are mounted side by side on the same substrate. The wiring on the wafer and substrate is typically accomplished by wire bonding. However, the side-by-side multi-chip package structure has the disadvantage that the package efficiency is too low because the area of the substrate increases as the number of crystals increases. As shown in FIG. 1A, the first wafer 110 is disposed on a substrate 100 and electrically connected to the substrate 100 by using a metal bonding wire 120, and a second wafer 112 is stacked and fixed by a bonding layer 130. A wafer 110 is electrically connected to the substrate 100 by a metal bonding wire 122. However, the wire bonding process of the first wafer 110 of such a structure must be completed before the second wafer 112 is stacked, that is, the die bonding and the wire bonding process of each wafer must be separately performed, thereby adding an additional process. step. Moreover, since the gap between the adjacent two wafers (e.g., the first wafer 110 and the second wafer 112) is relatively tight, the space for the wire bonding operation is also limited, thereby affecting the reliability of the bonding wires. 5 1324377 Therefore, another conventional method, please refer to FIG. 1B, in which a spacer l4 is disposed between two wafers (the first wafer 110 and the second wafer 112) and the height of the spacer material 140 is high. The height required for the i焊ps 〇f the ponding wires is 'in addition, the spacer material 〇4 is pre-set on the first wafer 110 before the wire bonding operation, and avoids the first a wafer 11 打 打 区 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Can improve the problem of the first chip u◦, so it is scheduled
封褒厚度内可堆疊之晶片數量有限或相同晶片數量時導致封 裝厚度較大。 請參考第⑴目，為另—種習知改良之多晶片堆疊結構， 如圖所示，間隔材料140係完全覆蓋第一晶片11〇 固定金屬銲線12G之-端（結球端）以減少發生 = 線120之線尾端仍有可能發生沖線問題，每= 均需要重複形成間隔材料14。，步驟較為；冗 且夕個晶片時，其打線位置與間隔材料M : 控制，故其訊號傳導信賴度有待考量。水+度越不谷易The limited number of wafers that can be stacked within the seal thickness or the same number of wafers results in a larger package thickness. Please refer to the item (1) for another conventionally modified multi-wafer stack structure. As shown, the spacer material 140 completely covers the end of the first wafer 11〇 fixed metal bonding wire 12G (the ball end) to reduce occurrence. = There is still the possibility of a line problem at the end of the line 120, and the spacer material 14 needs to be repeatedly formed every =. The steps are relatively; when the chip is redundant and the chip is placed, the position of the wire and the spacer material M are controlled, so the signal transmission reliability is to be considered. Water + degree is not easy
【發明内容】 本發明目的之-係提供一種堆疊式晶 電線路取代金屬鋅線，以大幅減少封裝結構厚^構，利用¥ 本發明目的之一係提供—種堆叠式a 電線路取代金屬銲線，以解決灌模時金屬Be 、=構’利用導 沖線問題。 v’了成發生的線弧 本發明目的之-係提供-種堆疊式晶 屬銲線的取代’致使傳輪路徑變短以加快，、·。構’藉由金 號品質與強度得以較完整的保存。 &傳輪速度，且訊 6 本發明目的之一係提供一種堆疊式晶片封裝結構，藉由訊 號傳遞路徑的變短，以減少訊號的遲延進而提高傳導信賴度。 為了達到上述目的，本發明一實施例之一種堆疊式晶片封 裝結構，包含：一基板；一第一晶片，設置於基板之一上表面， 且其主動面朝上；一絕緣層，設置於第一晶片側壁；一第一導 電線路，電性連接第一晶片及基板並部分覆蓋絕緣層；以及一 第二晶片，設置於第一晶片上，並利用一導電連接結構與基板 電性連接β 底下藉由具體實施例配合所附的圖式詳加說明，當更容易 瞭解本發明之目的、技術内容、特點及其所達成之功效。 【實施方式】 其詳細說明如下，所述較佳實施例僅做一說明非用以限定 本發明。 第2Α圖、第2Β圖、第2C圖、第2D圖、第2Ε圖、第 2F圖、第2G圖及第2Η圖所示為根據本發明堆疊式晶片封裝 結構第一實施例之製作流程各步驟結構剖視圖。首先’請參考 2Α圖及帛2Β ffl ’提供一基板1〇 ;接著，以適當方式設置一 第一晶片20於基板10上表面u之適當位置，例如晶片之承 載區内，其中第-晶片2G之主動面21朝上’且主動面21上 具有複數個導電連接點22設置於周緣。接著，請參閱第2C 圖，形成-絕緣層30於第—晶片2G之側壁，其中絕緣層3〇 可以是利用喷墨方式(inkjetway)所形成，但$限於此。之後， 如第2D圖所$矛ij用如喷墨方式开》成—第一導電線路仙於 基板10上’纟t第-導電線路4〇係用以電性連接第一晶片 20上之導電連接.點22與基板10上表φ u之例如由銅(Cu)材 質所形成之線路’且第—導電線路4G係部分覆蓋絕緣層3〇。 1324377 •再來，請參考第2E圖，如圖所示，設置一第二晶片24於第一 • 晶片20上，其中第二晶片24之主動面25亦朝上，且主動面 ·. 25上具有複數個導電連接點26設置於周緣以方便後續電性連 接基板10。接著，利用一導電連接結構，電性連接第二晶片 ' 24上之導電連接點26與基板10上之線路，如第2F圖所示， • 此實施例係利用銲線50以打線方式電性連接第二晶片24與基 . 板10。再利用一封裝體60包覆基板10、第一晶片20、第二 晶片24、第一導電線路40與導電連接結構，如第2G圖所示。 最後，於此實施例中，如2H圖所示，更包括設置複數導電球 φ 70於基板10之下表面12以跟外界裝置電性連接。 接續上述說明，形成導電球70前之堆疊式晶片封裝結構 如第2G圖所示，包括：一基板10，其材質由金屬、玻璃、陶 瓷或高分子材質其中之任一所構成；一第一晶片20,設置於 基板10之一上表面11，且第一晶片20之主動面21朝上；一 ' 絕緣層30，設置於第一晶片20側壁，其中絕緣層30可以是 由塑膠或高分子材質所構成，但其並不限於此；一第一導電線 路40,電性連接第一晶片20及基板10並部分覆蓋絕緣層30, 其中第一導電線路40係由銀(Ag)、金(Au)與鉑（Pt)其中之任一 • 所構成；以及一第二晶片24，設置於第一晶片20上，並利用 一導電連接結構，如銲線50，與基板10電性連接。 於一實施例中，第一晶片20與第二晶片24係分別利用一 黏著結構80與黏著結構82固著設置於基板10及第一晶片20 上，其中黏著結構80與黏著結構82可以是黏著薄膜（die attach film)與黏著劑（die attach paste)其中之任一，但並不限於此， 只要能將第一晶片20固著於基板10或將第二晶片24固著於 第一晶片20上皆包含於本發明之範圍内。於此封裝結構中， 更包括一封裝體60包覆第一晶片20、第二晶片24、第一導電 線路40及導電連接結構。例如由環氧樹脂（epoxy)構成之封裝 8 1324377 體60可避免上述被包覆元件因外力或外物侵人而毀損。此 外’為與外^裝置電性連接，维疊式晶片封裝結構更包括複數 導電球7G β又置於基板1G之下表面12，其中導電球可以是 由錫所構成’例如第2H圖所示。 第3A圖、第3B圖、第3C圖、第3D圖、第3E圖、第 3F圖及第3G圖所示為根據本發明堆疊式晶片封裝結構第二實 施例之製作流程各步驟結構剖視圖。其中第3a圖、第3B圖、、 第3C圖、第3D圖至第3E圖為設置第二晶片24於第一晶片 2〇上之各步驟流程，此部份與第-實施例之第2A ®至第2E 圖相同’此處便不再贅述。接著，請參考第3F圖，利用由一 第二導電線路42形成之導電連接結構，電性連接第二晶片24 主動面25上之導電連接點26與基板1〇，其中第二導電線路 42可以是利用喷墨方式形成。藉由第一導電線路仙與第二導 電線路42取代習知之金屬銲線來電性連接晶片與基板，可縮 短傳輸路徑以加快訊號傳輸速度，此外，藉由訊號傳遞路經的 縮紐可減少訊號的遲延，進而提高傳導信賴度。接著，再利用 一封裝體60包覆基板10、第一晶片20、第二晶片24、第一 導電線路40與第二導電線路42，如第3G圖所示。最後，如 3H圖所示，於此實施例中，更包括設置複數導電球川於基板 W之下表面12以跟外界裝置電性連接。 土 接續上述說明，形成導電球70前之堆疊式晶片封裝結構 如第3G圖所示’包括：一基板1〇，其材質由金屬、玻璃 陶 瓷或高分子材質其中之任一所構成；一第一晶# 2〇,設置於 基板10之一上表面11，且第一晶片20之主動面21朝上；二 絕緣層30 ’設置於第一晶月20側壁；一第一導電線路4〇 :電 性連接第一晶片20及基板10並部分覆蓋絕緣層3〇，其中^ "'導電線路40係由銀(Ag)、金(Au)與鉑（pt)其申之任一所構 成；以及一第二晶片24，設置於第一晶片20上，並利用由第 9 1324377 • 二導電線路42形成之導電連接結構與基板10電性連接。於此 • 實施例中，第二導電線路42不僅負責電性連接第二晶片24與 ·_ 基板10，更電性接觸第一導電線路40以形成短路設計。於此 封裝結構中，更包括一封裝體60，包覆第一晶片20、第二晶 ' 片24、第一導電線路40及第二導電線路42,以避免上述被包 • 覆元件因外力或外物侵入而毀損。此外，為與外界裝置電性連 . 接，堆疊式晶片封裝結構更包括複數導電球70設置於基板10 之下表面12，其中導電球70可以是由錫（Sn)所構成，例如第 3H圖所示。 • 於又一實施例中，請參考第4圖，於形成第二導電線路 42前，更包括利用噴墨方式或微影製程方式形成一絕緣結構， 例如絕緣層32，以電性隔絕第一導電線路40與第二導電線路 - 42，方便於堆疊結構中製作複雜的連接線路。因此，利用導電 線路取代金屬銲線可大幅減少堆疊結構之封裝厚度。 依據上述，本發明的特徵之一係利用喷墨方式形成絕緣層 或導電線路，製程上相當方便；又，在不影響封裝體厚度的前 提下，導電線路與絕緣層除可搭配使用外亦可再配合銲線使 用，所以結構設計與製程相當彈性；更者，導電線路之間亦可 ® 電性接觸以形成所須之短路設計；此外，本發明的特徵之一係 不限定運用於雙晶片之堆疊結構，亦適用於堆疊式系統級構裝 (system in package, SIP)或多晶片封裝（multi-chip package, MCP)之設計，另，藉由導電線路取代金屬銲線亦可減少灌模 時金屬銲線毁損之機率。 综合上述，本發明係提供一種堆疊式晶片封裝結構，利用 導電線路取代金屬銲線，除了可以大幅減少封裝結構厚度外， 更可解決灌模時金屬銲線可能發生的線弧沖線問題。又，藉由 金屬銲線的取代，致使傳輸路徑縮短以加快訊號傳輸速度，且 10 1324377 •訊號品質與強度得以較完整的保存。除此之外，訊號傳遞路徑 • 縮短可減少訊號的遲延，進而提高傳導信賴度。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容並 據以實施，當不能以之限定本發明之專利範圍，即大凡依本發 • 明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之 . 專利範圍内。 【圖式簡單說明】 • 第1A圖、第1B圖及第1C圖為習知多晶片堆疊封裝結構剖視圖。 第2A圖、第2B圖、第2C圖、第2D圖、第2E圖、第2F圖、第2G 圖及第2H圖所示為根據本發明堆疊式晶片封裝結構第一實施例 '之製作流程各步驟結構剖視圖。SUMMARY OF THE INVENTION The object of the present invention is to provide a stacked crystal electric circuit instead of a metal zinc wire to greatly reduce the thickness of the package structure, and one of the objects of the present invention is to provide a stacked type a electric circuit instead of metal welding. Line to solve the problem of using the lead line in the metal Be and = structure when filling the mold. The arc of the occurrence of the line arc is achieved by the fact that the replacement of the stacked crystal bond wires is provided to cause the transfer path to be shortened to speed up. The structure is preserved more completely by the quality and strength of the gold. & Transfer speed, and 6 is one of the objects of the present invention to provide a stacked chip package structure, which reduces the delay of the signal and thereby improves the conduction reliability by shortening the signal transmission path. In order to achieve the above object, a stacked chip package structure according to an embodiment of the invention includes: a substrate; a first wafer disposed on an upper surface of the substrate and having an active surface facing upward; and an insulating layer disposed on the first a first conductive line electrically connecting the first wafer and the substrate and partially covering the insulating layer; and a second wafer disposed on the first wafer and electrically connected to the substrate by using a conductive connection structure The purpose, technical content, features, and effects achieved by the present invention will become more apparent from the detailed description of the embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed description is not intended to limit the invention. 2D, 2D, 2C, 2D, 2D, 2F, 2G, and 2D are diagrams showing the manufacturing process of the first embodiment of the stacked chip package structure according to the present invention. Step structure cross-sectional view. First, please refer to FIG. 2 and FIG. 2 to provide a substrate 1 〇; then, a first wafer 20 is disposed in an appropriate position on the upper surface u of the substrate 10, such as a carrier region of the wafer, wherein the first wafer 2G The active surface 21 faces upwards and the active surface 21 has a plurality of conductive connection points 22 disposed on the periphery. Next, referring to FIG. 2C, the insulating layer 30 is formed on the sidewall of the first wafer 2G, wherein the insulating layer 3 is formed by an inkjet method, but is limited thereto. Then, as shown in FIG. 2D, the spear ij is opened by the inkjet method, and the first conductive trace is used on the substrate 10 to electrically connect the conductive on the first wafer 20. The point 22 is connected to the surface φ u of the substrate φ u, for example, a copper (Cu) material, and the first conductive line 4G partially covers the insulating layer 3 〇. 1324377 • Again, please refer to FIG. 2E. As shown, a second wafer 24 is disposed on the first wafer 20, wherein the active surface 25 of the second wafer 24 is also facing upward, and the active surface is on the 25th. A plurality of conductive connection points 26 are disposed on the periphery to facilitate subsequent electrical connection of the substrate 10. Then, a conductive connection structure is electrically connected to the conductive connection point 26 on the second wafer '24 and the line on the substrate 10, as shown in FIG. 2F. · This embodiment utilizes the bonding wire 50 to be electrically wired. The second wafer 24 is connected to the base plate 10. The package 10, the first wafer 20, the second wafer 24, the first conductive line 40 and the conductive connection structure are covered by a package 60, as shown in Fig. 2G. Finally, in this embodiment, as shown in FIG. 2H, a plurality of conductive balls φ 70 are further disposed on the lower surface 12 of the substrate 10 to be electrically connected to the external device. Following the above description, the stacked chip package structure before forming the conductive ball 70 is as shown in FIG. 2G, and includes: a substrate 10 made of any one of metal, glass, ceramic or polymer material; The wafer 20 is disposed on an upper surface 11 of the substrate 10, and the active surface 21 of the first wafer 20 faces upward; an 'insulating layer 30 is disposed on the sidewall of the first wafer 20, wherein the insulating layer 30 may be made of plastic or polymer. The first conductive circuit 40 is electrically connected to the first wafer 20 and the substrate 10 and partially covers the insulating layer 30, wherein the first conductive line 40 is made of silver (Ag) or gold ( And a second wafer 24 is disposed on the first wafer 20 and electrically connected to the substrate 10 by a conductive connection structure such as a bonding wire 50. In one embodiment, the first wafer 20 and the second wafer 24 are respectively fixed on the substrate 10 and the first wafer 20 by using an adhesive structure 80 and an adhesive structure 82. The adhesive structure 80 and the adhesive structure 82 may be adhered. Any one of a die attach film and a die attach paste, but is not limited thereto, as long as the first wafer 20 can be fixed to the substrate 10 or the second wafer 24 can be fixed to the first wafer 20 All are included in the scope of the present invention. In the package structure, a package 60 is further included to cover the first wafer 20, the second wafer 24, the first conductive line 40, and the conductive connection structure. For example, a package made of epoxy resin 8 1324377 body 60 can prevent the above-mentioned coated component from being damaged by external force or foreign object intrusion. In addition, in order to electrically connect to the device, the stacked chip package structure further includes a plurality of conductive balls 7G β which are placed on the lower surface 12 of the substrate 1G, wherein the conductive balls may be composed of tin, for example, as shown in FIG. 2H. . 3A, 3B, 3C, 3D, 3E, 3F, and 3G are cross-sectional views showing the steps of the manufacturing process of the second embodiment of the stacked wafer package structure according to the present invention. 3A, 3B, 3C, 3D to 3E are flow paths of the second wafer 24 on the first wafer 2, and the portion is the second embodiment of the first embodiment. ® to 2E are the same 'will not be repeated here. Next, referring to FIG. 3F, the conductive connection structure formed by a second conductive line 42 is electrically connected to the conductive connection point 26 on the active surface 25 of the second wafer 24 and the substrate 1 〇, wherein the second conductive line 42 can be It is formed by an inkjet method. By replacing the conventional metal bonding wire with the first conductive line and the second conductive line 42 to electrically connect the wafer and the substrate, the transmission path can be shortened to speed up the signal transmission speed, and the signal can be reduced by the signal transmission path. The delay, which in turn increases the reliability of conduction. Next, the substrate 10, the first wafer 20, the second wafer 24, the first conductive line 40 and the second conductive line 42 are covered by a package 60, as shown in Fig. 3G. Finally, as shown in FIG. 3H, in this embodiment, a plurality of conductive balls are disposed on the lower surface 12 of the substrate W to be electrically connected to the external device. In the above description, the stacked chip package structure before forming the conductive ball 70 is as shown in FIG. 3G' including: a substrate 1 〇, the material of which is composed of any one of metal, glass ceramic or polymer material; a first surface 11 of the substrate 10, and the active surface 21 of the first wafer 20 faces upward; the second insulating layer 30' is disposed on the sidewall of the first crystal 20; a first conductive line 4: Electrically connecting the first wafer 20 and the substrate 10 and partially covering the insulating layer 3〇, wherein the conductive line 40 is composed of any one of silver (Ag), gold (Au) and platinum (pt); And a second wafer 24 disposed on the first wafer 20 and electrically connected to the substrate 10 by a conductive connection formed by the ninth 1324377 ii conductive line 42. In this embodiment, the second conductive line 42 is not only responsible for electrically connecting the second wafer 24 and the substrate 10, but also electrically contacting the first conductive line 40 to form a short circuit design. The package structure further includes a package body 60 covering the first wafer 20, the second crystal chip 24, the first conductive line 40 and the second conductive line 42 to prevent the above-mentioned packaged component from being externally applied or Foreign objects invade and are damaged. In addition, in order to electrically connect with the external device, the stacked chip package structure further includes a plurality of conductive balls 70 disposed on the lower surface 12 of the substrate 10, wherein the conductive balls 70 may be composed of tin (Sn), for example, FIG. Shown. In another embodiment, referring to FIG. 4, before forming the second conductive line 42, the method further comprises forming an insulating structure, such as an insulating layer 32, by using an inkjet method or a lithography process to electrically isolate the first. The conductive line 40 and the second conductive line - 42, facilitate the fabrication of complex connection lines in the stacked structure. Therefore, the use of conductive traces instead of metal bond wires can significantly reduce the package thickness of the stacked structure. According to the above, one of the features of the present invention is that the insulating layer or the conductive line is formed by the inkjet method, which is quite convenient in the process; and the conductive line and the insulating layer can be used in addition to the thickness of the package without affecting the thickness of the package. In combination with the wire bonding, the structural design and the process are quite flexible; moreover, the conductive lines can also be electrically contacted to form the required short circuit design; further, one of the features of the present invention is not limited to the use of the dual chip. The stack structure is also applicable to the design of a stacked system-in-package (SIP) or multi-chip package (MCP). In addition, the metal wire can be replaced by a conductive line to reduce the filling. The probability of metal wire damage. In summary, the present invention provides a stacked chip package structure, in which a metal wire is replaced by a conductive line, in addition to greatly reducing the thickness of the package structure, the wire arc line problem that may occur in the metal wire during filling is further solved. Moreover, by replacing the metal wire, the transmission path is shortened to speed up the signal transmission speed, and 10 1324377 • The signal quality and intensity are completely preserved. In addition, the signal transmission path • shortens the signal delay, which improves the conduction reliability. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent changes or modifications made by the public in accordance with the spirit of this disclosure should still be covered by the patent of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS: FIGS. 1A, 1B, and 1C are cross-sectional views of a conventional multi-wafer stacked package structure. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H are diagrams showing the manufacturing process of the first embodiment of the stacked wafer package structure according to the present invention A cross-sectional view of each step structure.
. 第3A圖、第3B圖、第3C圖、第3D圖、第3E圖、第3F圖、第3G 圖及第3H圖所示為根據本發明堆疊式晶片封裝結構第二實施例 之製作流程各步驟結構剖視圖。 第4圖為根據本發明堆疊式晶片封裝結構之第三實施例之結構剖面 A 示意圖。 【主要元件符號說明】 10,100 基板 11 上表面 12 下表面 20,24, 110,112 晶片 21，25 主動面 11 1324377 22,26 導電連接點 30,32 絕緣層 40,42 導電線路 50 銲線 60 封裝體 70 導電球 80,82 黏著結構 120, 122 金屬銲線 130 膠層 140 間隔材料 123A, 3B, 3C, 3D, 3E, 3F, 3G, and 3H are diagrams showing a second embodiment of the stacked wafer package structure according to the present invention A cross-sectional view of each step structure. Figure 4 is a schematic cross-sectional view showing a structure of a third embodiment of a stacked wafer package structure in accordance with the present invention. [Main component symbol description] 10,100 substrate 11 upper surface 12 lower surface 20, 24, 110, 112 wafer 21, 25 active surface 11 1324377 22, 26 conductive connection point 30, 32 insulating layer 40, 42 conductive line 50 bonding wire 60 package 70 Conductive ball 80, 82 adhesive structure 120, 122 metal wire 130 glue layer 140 spacer material 12