JP2007043065A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2007043065A JP2007043065A JP2006061759A JP2006061759A JP2007043065A JP 2007043065 A JP2007043065 A JP 2007043065A JP 2006061759 A JP2006061759 A JP 2006061759A JP 2006061759 A JP2006061759 A JP 2006061759A JP 2007043065 A JP2007043065 A JP 2007043065A
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- external connection
- connection terminal
- convex
- convex external
- semiconductor element
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Abstract
【解決手段】半導体基板101の一方の主面に複数個の外部接続端子パッド102が配設され、当該外部接続パッド102上に複数個の凸状外部接続端子103A、103Bが配設される。凸状外部接続端子を複数個配設することにより、半導体素子の凸状外部接続端子と支持基板上の導電層との間に介在される接続部材との接触面積が増加することから、前記昇温・降温の際に生じるストレスはより広い範囲に分散される。
【選択図】図1
Description
尚、外部接続用パッド102に於いて、凸状外部接続端子103A及び凸状外部接続端子103Bは、半導体素子100の縁部の延びる方向に対して直角方向に並んで配設されている。
(付記1) 半導体基板の一方の主面に外部接続用端子パッドを具備する半導体素子が、前記外部接続用端子パッド上に配設された凸状外部接続端子及び接続部材を介して、支持基板上の導電層に接続される半導体装置であって、
前記外部接続用端子パッドは複数個の凸状外部接続端子を具備し、前記接続部材は当該複数個の凸状外部接続端子を共通に被覆してなることを特徴とする半導体装置。
(付記2) 半導体基板、前記半導体基板の一方の主面に配設された外部接続用端子パッド、及び前記外部接続用端子パッド上に複数個配設された凸状外部接続端子を具備する半導体素子と、
絶縁性基板、前記絶縁基板の一方の主面に配設された導電層、及び前記絶縁基板の前記一方の主面上に配設されて前記導電層を選択的に被覆する絶縁層を具備する支持基板と、
前記絶縁層に被覆されない前記導電層に、前記複数個の凸状外部接続端子を共通に被覆して固着する接続部材と、を具備することを特徴とする半導体装置。
(付記3) 半導体基板の一方の主面に複数個の外部接続用端子パッドが配設され、当該外部接続用端子パッド上に少なくとも一つの第1の凸状外部接続端子が配設されてなる半導体素子と、
前記外部接続用端子パッドに対応した複数個の導電層が配設され、当該導電層上に少なくとも一つの第2の凸状外部接続端子が配設されてなる支持基板と、を具備し、
前記第1の凸状外部接続端子が接続部材を介して前記導電層に接続されるとともに、前記第2の凸状外部接続端子が当該接続部材を介して前記外部接続用端子パッドに接続されてなることを特徴とする半導体装置。
(付記4) 付記3記載の半導体装置であって、
前記外部接続用端子パッドにおける前記第1の凸状外部接続端子の配設箇所と、前記導電層における前記第2の凸状外部接続端子の配設箇所とは、当該半導体装置の幅方向において位置が異なっており、
前記第1の凸状外部接続端子の先端面の位置と、前記第2の凸状外部接続端子の先端面の位置は、当該半導体装置の厚さ方向において相違している、ことを特徴とする半導体装置。
(付記5) 付記4記載の半導体装置であって、
前記第1の凸状外部接続端子又は前記第2の凸状外部接続端子の少なくとも一方は複数個配設されており、
隣り合う前記第1の凸状外部接続端子の間に前記第2の凸状外部接続端子が、又は隣り合う前記第2の凸状外部接続端子の間に前記前記第1の凸状外部接続端子が配設されていることを特徴とする半導体装置。
(付記6) 付記1乃至5いずれか一項記載の半導体装置であって、
前記半導体素子は第1の半導体素子として機能し、
前記第1の半導体素子の上に第2の半導体素子が接着固定されていることを特徴とする半導体装置。
(付記7) 付記1乃至6いずれか一項記載の半導体装置であって、
前記複数個の外部接続端子パッドは、前記半導体基板の略中央において列を形成して配設されえていることを特徴とする半導体装置。
(付記8) 付記6及び7記載の半導体装置であって、
前記第1の半導体素子、前記第2の半導体素子及び前記支持基板は封止樹脂により封止されていることを特徴とする半導体装置。
(付記9) 支持基板と、
前記支持基板の上に実装された配線基板を介して前記支持基板に接続され、前記配線基板の上に実装された半導体素子と、を備えた半導体装置であって、
前記半導体素子の半導体基板の主面のうち、前記配線基板に面した側の面に複数個の半導体素子外部接続用端子パッドが配設され、当該半導体素子外部接続用端子パッド上に少なくとも一つの第1の凸状外部接続端子が配設され、
前記配線基板の主面のうち、前記半導体素子に面した側の面に複数個の配線基板外部接続用端子パッドが配設され、当該配線基板外部接続用端子パッド上に少なくとも一つの第2の凸状外部接続端子が配設され、
前記第1の凸状外部接続端子が接続部材を介して前記配線基板外部接続用端子パッドに接続されるとともに、前記第2の凸状外部接続端子が当該接続部材を介して前記半導体素子外部接続用端子パッドに接続されてなることを特徴とする半導体装置。
(付記10) 付記9記載の半導体装置であって、
前記半導体素子外部接続用端子パッドにおける前記第1の凸状外部接続端子の配設箇所と、前記配線基板外部接続用端子パッドにおける前記第2の凸状外部接続端子の配設箇所とは、当該半導体装置の幅方向において位置が異なっており、
前記第1の凸状外部接続端子の先端面の位置と、前記第2の凸状外部接続端子の先端面の位置は、当該半導体装置の厚さ方向において相違している、ことを特徴とする半導体装置。
(付記11) 付記10記載の半導体装置であって、
前記第1の凸状外部接続端子又は前記第2の凸状外部接続端子の少なくとも一方は複数個配設されており、
隣り合う前記第1の凸状外部接続端子の間に前記第2の凸状外部接続端子が、又は隣り合う前記第2の凸状外部接続端子の間に前記前記第1の凸状外部接続端子が配設されていることを特徴とする半導体装置。
(付記12) 付記9乃至11いずれか一項記載の半導体装置であって、
前記配線基板は、有機材料、セラミック、又はガラスから選択される材料から構成されていることを特徴とする半導体装置。
(付記13) 付記9乃至11いずれか一項記載の半導体装置であって、
前記配線基板は、シリコンから成ることを特徴とする半導体装置。
(付記14) 付記13記載の半導体装置であって、
前記配線基板に、半導体集積回路が形成されていることを特徴とする半導体装置。
(付記15) 付記9及び14記載の半導体装置であって、
前記半導体素子、前記配線基板及び前記支持基板は封止樹脂により封止されていることを特徴とする半導体装置。
12 導電層
13 ソルダーレジスト
14 接続部材
15 アンダーフィル材
19、103、119、153、503、603 凸状外部接続端子
100、150、160、500 半導体素子
101、151、161、501 半導体基板
102、152、502、612B 外部接続用パッド
200 接続領域
301 台座部
302 突出する部位
401 ボンディングステージ
402 吸着用治具
600 配線基板
Claims (10)
- 半導体基板の一方の主面に外部接続用端子パッドを具備する半導体素子が、前記外部接続用端子パッド上に配設された凸状外部接続端子及び接続部材を介して、支持基板上の導電層に接続される半導体装置であって、
前記外部接続用端子パッドは複数個の凸状外部接続端子を具備し、前記接続部材は当該複数個の凸状外部接続端子を共通に被覆してなることを特徴とする半導体装置。 - 半導体基板、前記半導体基板の一方の主面に配設された外部接続用端子パッド、及び前記外部接続用端子パッド上に複数個配設された凸状外部接続端子を具備する半導体素子と、
絶縁性基板、前記絶縁基板の一方の主面に配設された導電層、及び前記絶縁基板の前記一方の主面上に配設されて前記導電層を選択的に被覆する絶縁層を具備する支持基板と、
前記絶縁層に被覆されない前記導電層に、前記複数個の凸状外部接続端子を共通に被覆して固着する接続部材と、を具備することを特徴とする半導体装置。 - 半導体基板の一方の主面に複数個の外部接続用端子パッドが配設され、当該外部接続用端子パッド上に少なくとも一つの第1の凸状外部接続端子が配設されてなる半導体素子と、
前記外部接続用端子パッドに対応した複数個の導電層が配設され、当該導電層上に少なくとも一つの第2の凸状外部接続端子が配設されてなる支持基板と、を具備し、
前記第1の凸状外部接続端子が接続部材を介して前記導電層に接続されるとともに、前記第2の凸状外部接続端子が当該接続部材を介して前記外部接続用端子パッドに接続されてなることを特徴とする半導体装置。 - 請求項3記載の半導体装置であって、
前記外部接続用端子パッドにおける前記第1の凸状外部接続端子の配設箇所と、前記導電層における前記第2の凸状外部接続端子の配設箇所とは、当該半導体装置の幅方向において位置が異なっており、
前記第1の凸状外部接続端子の先端面の位置と、前記第2の凸状外部接続端子の先端面の位置は、当該半導体装置の厚さ方向において相違している、ことを特徴とする半導体装置。 - 請求項4記載の半導体装置であって、
前記第1の凸状外部接続端子又は前記第2の凸状外部接続端子の少なくとも一方は複数個配設されており、
隣り合う前記第1の凸状外部接続端子の間に前記第2の凸状外部接続端子が、又は隣り合う前記第2の凸状外部接続端子の間に前記前記第1の凸状外部接続端子が配設されていることを特徴とする半導体装置。 - 請求項1乃至5いずれか一項記載の半導体装置であって、
前記半導体素子は第1の半導体素子として機能し、
前記第1の半導体素子の上に第2の半導体素子が接着固定されていることを特徴とする半導体装置。 - 支持基板と、
前記支持基板の上に実装された配線基板を介して前記支持基板に接続され、前記配線基板の上に実装された半導体素子と、を備えた半導体装置であって、
前記半導体素子の半導体基板の主面のうち、前記配線基板に面した側の面に複数個の半導体素子外部接続用端子パッドが配設され、当該半導体素子外部接続用端子パッド上に少なくとも一つの第1の凸状外部接続端子が配設され、
前記配線基板の主面のうち、前記半導体素子に面した側の面に複数個の配線基板外部接続用端子パッドが配設され、当該配線基板外部接続用端子パッド上に少なくとも一つの第2の凸状外部接続端子が配設され、
前記第1の凸状外部接続端子が接続部材を介して前記配線基板外部接続用端子パッドに接続されるとともに、前記第2の凸状外部接続端子が当該接続部材を介して前記半導体素子外部接続用端子パッドに接続されてなることを特徴とする半導体装置。 - 請求項7記載の半導体装置であって、
前記半導体素子外部接続用端子パッドにおける前記第1の凸状外部接続端子の配設箇所と、前記配線基板外部接続用端子パッドにおける前記第2の凸状外部接続端子の配設箇所とは、当該半導体装置の幅方向において位置が異なっており、
前記第1の凸状外部接続端子の先端面の位置と、前記第2の凸状外部接続端子の先端面の位置は、当該半導体装置の厚さ方向において相違している、ことを特徴とする半導体装置。 - 請求項8記載の半導体装置であって、
前記第1の凸状外部接続端子又は前記第2の凸状外部接続端子の少なくとも一方は複数個配設されており、
隣り合う前記第1の凸状外部接続端子の間に前記第2の凸状外部接続端子が、又は隣り合う前記第2の凸状外部接続端子の間に前記前記第1の凸状外部接続端子が配設されていることを特徴とする半導体装置。 - 請求項7乃至9いずれか一項記載の半導体装置であって、
前記配線基板は、シリコンから成ることを特徴とする半導体装置。
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JP4817892B2 (ja) | 2011-11-16 |
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US8810043B2 (en) | 2014-08-19 |
CN1893051A (zh) | 2007-01-10 |
US8076785B2 (en) | 2011-12-13 |
KR20070001003A (ko) | 2007-01-03 |
US20110278723A1 (en) | 2011-11-17 |
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CN100495694C (zh) | 2009-06-03 |
US20060289972A1 (en) | 2006-12-28 |
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