KR101083663B1 - 오버행 다이 스택 구조를 이용한 반도체 패키지 - Google Patents
오버행 다이 스택 구조를 이용한 반도체 패키지 Download PDFInfo
- Publication number
- KR101083663B1 KR101083663B1 KR1020090070456A KR20090070456A KR101083663B1 KR 101083663 B1 KR101083663 B1 KR 101083663B1 KR 1020090070456 A KR1020090070456 A KR 1020090070456A KR 20090070456 A KR20090070456 A KR 20090070456A KR 101083663 B1 KR101083663 B1 KR 101083663B1
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- KR
- South Korea
- Prior art keywords
- die
- adhesive
- semiconductor package
- substrate
- overhang
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
Description
Claims (5)
- 다수의 본딩패드를 상면에 구성하고 있는 기판과, 다수 칩패드를 상면에 구성하며 상기 기판에 적층되는 다이와, 상기 본딩패드와 칩패드를 전기적으로 접속시키는 본딩와이어로 전기적 접속시키는 반도체 패키지에 있어서,상기 기판과 다이를 접착시키는 접착층 사이에 50 내지 100 um 두께의 스페이서를 적층시키고, 상기 스페이서는 상기 다이보다 단면 크기를 작게 하고 상기 접착층을 구성하는 접착물질의 단면 크기와 동일하게 하여 구성하는 것을 특징으로 하는 오버행(overhang) 다이 스택 구조를 이용한 반도체 패키지.
- 제 1항에 있어서,상기 접착층을 구성하는 접착물질은 액체 형태의 에폭시 접착제이거나 필름 타입의 접착제인 것을 특징으로 하는 오버행(overhang) 다이 스택 구조를 이용한 반도체 패키지.
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090070456A KR101083663B1 (ko) | 2009-07-31 | 2009-07-31 | 오버행 다이 스택 구조를 이용한 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090070456A KR101083663B1 (ko) | 2009-07-31 | 2009-07-31 | 오버행 다이 스택 구조를 이용한 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20110012647A KR20110012647A (ko) | 2011-02-09 |
KR101083663B1 true KR101083663B1 (ko) | 2011-11-16 |
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KR1020090070456A KR101083663B1 (ko) | 2009-07-31 | 2009-07-31 | 오버행 다이 스택 구조를 이용한 반도체 패키지 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101333398B1 (ko) * | 2012-02-14 | 2013-11-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102205044B1 (ko) * | 2014-01-06 | 2021-01-19 | 에스케이하이닉스 주식회사 | 칩 적층 패키지 및 그 제조방법 |
KR101696638B1 (ko) * | 2015-06-25 | 2017-01-16 | 크루셜텍 (주) | 센서 패키지 및 이의 제조방법 |
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- 2009-07-31 KR KR1020090070456A patent/KR101083663B1/ko active IP Right Grant
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101333398B1 (ko) * | 2012-02-14 | 2013-11-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
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KR20110012647A (ko) | 2011-02-09 |
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