CN109564905A - Ic封装 - Google Patents

Ic封装 Download PDF

Info

Publication number
CN109564905A
CN109564905A CN201880002334.9A CN201880002334A CN109564905A CN 109564905 A CN109564905 A CN 109564905A CN 201880002334 A CN201880002334 A CN 201880002334A CN 109564905 A CN109564905 A CN 109564905A
Authority
CN
China
Prior art keywords
marking plate
chips
package
main surface
plastic construction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201880002334.9A
Other languages
English (en)
Inventor
周厚德
陈鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Publication of CN109564905A publication Critical patent/CN109564905A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54433Marks applied to semiconductor devices or parts containing identification or tracking information
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92162Sequential connecting processes the first connecting process involving a wire connector
    • H01L2224/92165Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Laser Beam Processing (AREA)

Abstract

本公开的各个方面提供了一种集成电路(IC)封装。所述IC封装包括封装衬底、一个或多个IC芯片、标记板和塑料结构。所述一个或多个IC芯片与所述封装衬底互连。所述标记板具有第一主表面和第二主表面。将所述标记板叠置在所述一个或多个IC芯片上使得所述第一主表面面向所述一个或多个IC芯片。所述塑料结构被配置为包封所述一个或多个IC芯片和所述标记板,其中所述标记板的第二主表面是所述IC封装的外表面的部分。

Description

IC封装
背景技术
在半导体制造当中,集成电路(IC)封装是在半导体器件制造中将集成电路的一个或多个半导体管芯(又称为IC芯片)包封到用于防止物理损伤、腐蚀等的支撑壳体当中的步骤。具有经包封的半导体管芯的支撑壳体被称为IC封装。可以对IC封装进行激光标记,以便于识别和溯源。
发明内容
本公开的各个方面提供了一种集成电路(IC)封装。所述IC封装包括封装衬底、一个或多个IC芯片、标记板以及塑料结构。所述一个或多个IC芯片与所述封装衬底互连。所述标记板具有第一主表面和第二主表面。所述标记板叠置在所述一个或多个IC芯片上,其中所述第一主表面面向所述一个或多个IC芯片。所述塑料结构被配置为包封所述一个或多个IC芯片和所述标记板,其中所述标记板的第二主表面是所述IC封装的外表面的部分。
在一些示例中,所述标记板由半导体材料、陶瓷材料、金属材料和金属合金材料中的至少其中之一形成。在示例中,所述标记板被配置为具有阶梯结构,并且所述第一主表面具有不同于(例如,小于)所述第二主表面的表面积。在另一示例中,所述标记板被配置为具有长方体形状,其中所述第一主表面和所述第二主表面具有相同的表面积。
在实施例中,所述IC封装包括被配置为对所述一个或多个IC芯片与所述封装衬底进行互连的多条接合线。所述塑料结构被配置为包封所述多条接合线。
应注意,所述IC封装是球栅阵列(BGA)封装、四边扁平封装(QFP)、四边扁平无引线(QFN)封装、焊盘栅格阵列(LGA)封装和引脚栅格阵列(PGA)之一。
在一些实施例中,使相邻IC芯片错开,并且所述IC封装中的多个IC芯片是按照之字形图案叠置的。
根据本公开的一个方面,所述标记板具有比所述塑料结构更好的抗激光穿透特性。例如,所述标记板中的激光穿透深度短于所述塑料结构中的激光穿透深度。在一些示例中,所述标记板具有比所述塑料结构更高的刚度。根据本公开的另一方面,所述标记板具有与所述一个或多个IC芯片基本相等的热膨胀系数(CTE)。根据本公开的另一方面,所述标记板具有比所述塑料结构更好的热导率。因此,所述标记板能够将IC芯片在操作过程中生成的热传导至IC封装的外表面。
本公开的各个方面提供了一种用于制造集成电路(IC)封装的方法。所述方法包括在封装衬底上叠置一个或多个IC芯片;在所述一个或多个IC芯片上叠置具有面向所述一个或多个IC芯片的第一主表面的标记板;以及形成包封所述一个或多个IC芯片以及所述标记板的塑料结构,其中所述标记板的第二主表面是所述IC封装的外表面的部分。
在示例中,所述方法包括将所述标记板和所述一个或多个IC芯片包封到所述塑料结构中,并且对所述塑料结构进行研磨,以暴露所述标记板的第二主表面。此外,所述方法还包括在所述标记板的第二主表面上进行激光标记。
附图说明
当结合附图阅读下述详细描述时,本公开的各个方面将得到最佳的理解。应当指出,根据本行业的惯例,各种特征并非是按比例绘制的。实际上,为了讨论的清楚起见,可以任意增大或者缩小各种特征的尺寸。
图1示出了根据一些实施例的集成电路(IC)封装100的截面图。
图2示出了根据一些实施例的另一IC封装200的截面图。
图3示出了概括根据本公开的实施例的过程示例300的流程图。
图4-6示出了根据一些实施例的处于制造过程当中的IC封装100的截面图。
具体实施方式
下文的公开内容提供了用于实施所提供的主题的不同特征的很多不同实施例或示例。下文描述了部件和布置的具体示例以简化本公开。当然,这些只是示例,并非意在构成限制。例如,下文的描述当中出现的在第二特征上或之上形成第一特征可以包括将所述第一特征和第二特征形成为直接接触的实施例,还可以包括可以在所述第一特征和第二特征之间形成额外的特征从而使得所述第一特征和第二特征可能不直接接触的实施例。此外,本公开可以在各个示例中重复使用作为附图标记的数字和/或字母。这种重复的目的是为了简化和清楚的目的,其本身并不指示所讨论的各种实施例和/或配置之间的关系。
此外,文中为了便于说明可以采用空间相对术语,例如,“下面”、“之下”、“下方”、“之上”、“上方”等,以描述一个元件或特征与其他元件或特征的如图所示的关系。空间相对术语意在包含除了附图所示的取向之外的处于使用或操作中的装置的不同取向。所述设备可以具有其他取向(旋转90度或者处于其他取向上),并可以照样相应地解释文中采用的空间相对描述词。
本公开的各个方面提供了一种具有嵌入到塑料结构当中的标记板的集成电路(IC)封装。所述标记板具有比所述塑料结构的模制材料更高的刚度,并且具有比模制材料更好的抗激光穿透特性。因为更高的刚度的原因,能够降低由于高温处理(例如,焊接过程)导致的IC封装变形。此外,由于更好的抗激光穿透特性,允许标记板相对更薄。因而,所述IC封装可以具有相对更小的厚度或者能够包封更多的IC芯片而不增大封装厚度。
图1示出了根据一些实施例的集成电路(IC)封装100的截面图。IC封装100包括封装衬底110、多个IC芯片120(例如,包括图1示例中的IC芯片120A-120H)和标记板150。IC芯片120叠置在封装衬底110上并且被包封到塑料结构140内。标记板150叠置在IC芯片120上并且嵌入到塑料结构140内。标记板150的表面155是IC封装100的外表面的部分,并且可以用激光对表面155进行标记,以便于识别和溯源。
封装衬底110是由(例如)适当的绝缘材料(又称为电介质材料)构成的,例如,基于环氧树脂的层压衬底、基于树脂的双马来酰亚胺三嗪(BT)衬底等。封装衬底110相对呈刚性,从而为IC芯片120提供机械支撑。封装衬底110具有第一表面111和第二表面112。IC芯片120设置在表面上,例如,设置在封装衬底110的第二表面112上。
封装衬底110还为IC芯片120提供电气支撑。在一些示例中,封装衬底110包括多层金属迹线(例如,铜线等),其中绝缘材料位于金属迹线其间。不同层上的金属迹线可以通过通孔连接。此外,接触结构既形成于第一表面111上又形成于第二表面112上,从而将IC封装100中的IC芯片120电连接至IC封装100外的部件。
IC芯片120可以是任何适当的芯片。IC芯片120包括用于提供存储功能、计算功能和/或处理功能的各种电路。
封装衬底110提供从IC芯片120的输入/输出到形成于IC封装100的第一表面111和第二表面112上的接触结构的互连。在示例中,IC芯片120包括电连接至形成于IC芯片120上的内部电路的输入/输出(I/O)焊盘(未示出)。接合用以连接IC芯片120上的I/O焊盘以及封装衬底110的第二表面112上的接触结构的接合线130(例如,铝线、铜线、银线、金线等),从而在IC芯片120和封装衬底110之间形成电连接。在图1的示例中,使IC芯片120中的相邻IC芯片错开布置,以提供允许将接合线130接合到I/O焊盘上并且避免短路的接合空间。此外,各IC芯片120是按照之字形图案叠置的,从而为接合线130提供空间。
封装衬底110还包括位于第一表面111上的适当接触结构160。在图1的示例中,IC封装100是球栅阵列(BGA)封装,并且接触结构160中的每一个包括焊盘以及设置在焊盘上的焊球。注意,在一些示例中,不在封装衬底110上形成焊球。在示例中,IC封装是四边扁平(QFP)封装。在另一示例中,IC封装100是四边扁平无引线(QFN)封装。在另一个示例中,IC封装100是焊盘栅格阵列(LGA)封装,并且接触结构中的每一个包括焊盘。在另一个示例中,IC封装100是引脚栅格阵列(PGA)封装,并且接触结构中的每一个包括引脚。
在图1的示例中,封装衬底110、塑料结构140和标记板150形成了IC封装100的将IC芯片120包封在内的外侧部分。具体而言,标记板150叠置在IC芯片120上。之后,通过塑料结构140包封封装衬底110的第二表面112、IC芯片120和接合线130。标记板150被嵌入到塑料结构140内,其表面155露出以便于用激光做标记。
塑料结构140由任何适当材料形成,例如,硅氧化物填充物和树脂等。在示例中,塑料结构140包括环氧树脂模制化合物(EMC)。塑料结构140和IC芯片120具有不同的热膨胀系数(CTE)(又称为CTE失配)并且具有不同热导率。
根据本公开的一个方面,标记板150由刚度高于塑料结构140的材料形成。在图1的示例中,IC封装100从上表面(例如,标记板150的表面155)到底表面(例如,封装衬底110的第一表面111)包括标记板150、IC芯片120和封装衬底110。与塑料结构140相比,标记板150、IC芯片和封装衬底110具有相对较高的刚度。在常规示例中,相关IC封装的上部也由EMC构成,并且用于进行激光标记。与常规示例相比,IC封装100具有更低的体积百分比的EMC,因而与常规示例相比具有更高的封装刚度。
根据本公开的另一方面,标记板150具有与IC芯片120大致相同的CTE(即,匹配的CTE)。因而,IC封装110在热处理期间具有降低的翘曲。例如,CTE失配可能在模制之后的热处理期间引起封装翘曲。例如,可以使用表面安装工艺将所述IC封装安装到印刷电路板(PCB)上。所述表面安装工艺包括焊料回流步骤,其使得处理温度升高到(例如)200℃以上。在处理温度返回到示例性的室温时,由于从上表面到底表面的匹配CTE的原因,IC封装100与常规示例相比具有降低的翘曲。
此外,根据本公开的一个方面,标记板150具有比塑料结构140更好的抗激光穿透特性,以防止激光穿透。例如,标记板150中的激光穿透深度短于塑料结构140中的激光穿透深度。因而,IC封装100具有降低的厚度,或者可以包括更多的IC芯片120。例如,在常规示例中,由于是在EMC上进行激光标记,为了防止对IC芯片120上的电路或者对接合线130造成激光损伤,因而所述塑料结构的处于IC芯片之上的顶部必须相对较厚,例如,约为150μm。标记板150具有比塑料结构140更好的抗激光穿透特性,并且30μm的厚度就足以防止对IC芯片120上的电路和接合线130造成激光损伤。
根据本公开的另一方面,标记板150具有比塑料结构140更好的热导率。例如,与塑料结构140相比,标记板150可以更快地将IC芯片在操作过程中生成的热传导至IC封装100的外表面。快速的热传递能够为IC芯片120提供合适的热环境,降低操作期间的芯片温度,并且允许IC芯片120在操作器件正确工作。
在实施例中,标记板150是由硅(例如,纯硅)形成的,因而在示例中被称为镜面管芯(由于光亮的表面155的原因)。因而,标记板150具有与IC芯片120大致相同的CTE(例如,匹配CTE),并且与塑料结构140相比具有更高的刚度和更优的抗激光穿透特性。
应注意,其他适当的材料,例如,陶瓷、金属、金属合金也可以用于形成标记板150。在示例中,标记板150由陶瓷材料形成。在另一示例中,标记板150由金属合金形成。对标记板150进行适当处理,从而使标记板150的面对IC芯片120的底表面是不导电的,从而避免与接合线130短路。
在图1的示例中,标记板150被配置为在截面图当中具有阶梯形状。因而,标记板150的面对IC芯片120H的表面157小于标记板150的表面155。较小的表面157在IC芯片120H上提供了更多的用于引线接合的空间。较大的表面155允许有更多的面积进行激光标记。
应注意,尽管在图1的示例中IC芯片120被示为具有相同的芯片尺寸,但是在其他示例中,IC芯片120可以具有不同的芯片尺寸。
还要注意,在叠置IC芯片120和标记板150时,可以在IC芯片120和标记板150之间采用中间层170(例如,粘合膜、聚合物膜和间隔体膜等)。
图2示出了根据一些实施例的另一IC封装200的截面图。与IC封装100类似,IC封装200包括封装衬底210、多个IC芯片220和标记板250。IC芯片220叠置在封装衬底210上并且被包封到塑料结构240中。标记板250叠置在IC芯片220上并且嵌入到塑料结构240内。标记板250的表面255是IC封装200的外表面的部分,并且可以对表面255进行激光标记,以用于识别和溯源。
IC封装200采用某些与IC封装100中采用的等同、等价或类似的部件。例如,IC芯片220与IC芯片120等价或类似。接合线230与接合线130等价或类似。塑料结构240与塑料结构140等价或类似。封装衬底210与封装衬底110等价或类似。上文已经提供了对这些部件的描述,这里为了清楚起见将省略这样的描述。
在图2的示例中,标记板250被配置为具有长方体形状,并且从截面图来看具有矩形形状,因而面对IC芯片220H的表面257与作为IC封装200的外表面的部分的表面255具有相同的表面积。
此外,在图2的示例中,IC封装200可以是没有焊球的LGA封装。封装衬底210包括第一表面211上的平接触结构。
图3示出了概况根据本公开的一些实施例的制造过程300的流程图。在示例中,过程300用于制造IC封装,例如,IC封装100、IC封装200等。
图4-6示出了根据一些实施例处于制造过程300的各个中间阶段的IC封装100的各个截面图。应注意,对于其他IC封装(例如,IC封装200)而言,可以对图4-6做出适当修改。
参考图3和图4,所述过程开始于S301,并且进行至S310。
在S310中,将IC芯片叠置到封装衬底上。如图4所示,多个IC芯片120被叠置到封装衬底110上。IC芯片120是按照错开的方式叠置的,从而为引线接合提供更多的空间。例如,使IC芯片120中的相邻IC芯片错开,从而为引线接合提供空间。各IC芯片120可以是按照之字形图案叠置的。使用接合线130进行接合,从而使IC芯片120与封装衬底110互连。在图4的示例中,在相邻的IC芯片120之间使用粘合膜170。
在S320中,将初始标记板叠置到IC芯片上。如图4所示,初始标记板450叠置在IC芯片120上。应注意,初始标记板450比IC封装100中的标记板150更厚。在图4的示例中,在初始标记板450和IC芯片120的顶部之间使用粘合膜170。
在S330中,初始标记板和IC芯片被包封到初始塑料结构当中。如图5所示,对诸如EMC等的塑料材料进行模制,以形成包封IC芯片120和初始标记板450的初始塑料结构540。
在S340中,对初始塑料结构进行研磨。如图5所示,对初始塑料结构540进行研磨,以露出初始标记板450,并且对其做进一步研磨,以形成塑料结构140和标记板150。图6示出了所述研磨过程之后的IC封装。
在S350中,在所述标记板上对所述IC封装进行激光标记。例如,可以在标记板150上执行激光标记,以用于识别和溯源。
在S360中,可以对IC封装执行进一步的处理。在示例中,将诸如焊球160的焊球附接到封装衬底110上。在示例中,以封装矩阵阵列的形式执行IC封装操作。可以对封装的矩阵阵列划片,以形成各个IC封装。之后,对单独的IC封装进行测试和分类。之后,过程进行至S399并结束。
前文概述了几个实施例的特征,从而使本领域技术人员可以更好地理解本公开的各个方面。本领域技术人员应当认识到他们可以容易地使用本公开作为基础来设计或者修改其他的工艺过程或结构,以达到与文中介绍的实施例相同的目的和/或实现与之相同的优点。本领域技术人员还应当认识到这样的等价设计不脱离本公开的实质和范围,而且在这里可以对它们做出各种变化、替换和更改,而不脱离本公开的实质和范围。

Claims (20)

1.一种集成电路(IC)封装,包括:
封装衬底;
一个或多个IC芯片,所述一个或多个IC芯片与所述封装衬底互连;
标记板,所述标记板具有第一主表面和第二主表面,所述标记板叠置在所述一个或多个IC芯片上,其中所述第一主表面面向所述一个或多个IC芯片;
塑料结构,所述塑料结构被配置为包封所述一个或多个IC芯片和所述标记板,其中所述标记板的所述第二主表面是所述IC封装的外表面的部分。
2.根据权利要求1所述的IC封装,其中:
所述标记板由半导体材料、陶瓷材料、金属材料和金属合金材料中的至少一种形成。
3.根据权利要求1所述的IC封装,其中所述标记板被配置为具有阶梯结构,并且所述第一主表面具有不同于所述第二主表面的表面积。
4.根据权利要求1所述的IC封装,其中:
多条接合线被配置为对所述一个或多个IC芯片与所述封装衬底进行互连;并且
所述塑料结构被配置为包封所述多条接合线。
5.根据权利要求1所述的IC封装,其中:
所述IC封装是球栅阵列(BGA)封装、四边扁平封装(QFP)、四边扁平无引线(QFN)封装、焊盘栅格阵列(LGA)封装和引脚栅格阵列(PGA)中的一种。
6.根据权利要求1所述的IC封装,其中:
使所述一个或多个IC芯片中的相邻IC芯片错开,从而为接合线提供空间。
7.根据权利要求1所述的IC封装,其中:
所述标记板被配置为具有长方体形状,使得所述第一主表面和所述第二主表面具有基本相同的表面积。
8.根据权利要求7所述的IC封装,其中:
所述标记板中的激光穿透深度短于所述塑料结构中的激光穿透深度。
9.根据权利要求1所述的IC封装,其中:
所述标记板具有比所述塑料结构更高的刚度。
10.根据权利要求1所述的IC封装,其中:
所述标记板具有与所述一个或多个IC芯片基本相等的热膨胀系数(CTE)。
11.一种用于制造集成电路(IC)封装的方法,包括:
在封装衬底上叠置一个或多个IC芯片;
在所述一个或多个IC芯片上形成具有面向所述一个或多个IC芯片的第一主表面的标记板;以及
形成包封所述一个或多个IC芯片以及所述标记板的塑料结构,其中所述标记板的第二主表面是所述IC封装的外表面的部分。
12.根据权利要求11所述的方法,其中形成所述标记板和所述塑料结构进一步包括:
将初始标记板和所述一个或多个IC芯片包封到初始塑料结构中;以及
对所述初始塑料结构和所述初始标记板进行研磨,以露出所述标记板的所述第二主表面。
13.根据权利要求11所述的方法,进一步包括:
在所述标记板的所述第二主表面上进行激光标记。
14.根据权利要求11所述的方法,其中在所述一个或多个IC芯片上形成所述标记板进一步包括:
将所述标记板形成为具有小于所述第二主表面且面向所述一个或多个IC芯片的所述第一主表面。
15.根据权利要求11所述的方法,进一步包括:
接合用于将所述一个或多个IC芯片与所述封装衬底互连的线;以及
形成包封所接合的线的所述塑料结构。
16.根据权利要求11所述的方法,其中在所述封装衬底上叠置所述一个或多个IC芯片进一步包括:
使所述一个或多个IC芯片中的相邻IC芯片错开,从而为接合线提供空间。
17.根据权利要求11所述的方法,其中在所述一个或多个IC芯片上形成所述标记板进一步包括:
将所述标记板形成为具有长方体形状,使得所述第一主表面和所述第二主表面具有基本相同的表面积。
18.根据权利要求17所述的方法,其中:
所述标记板中的激光穿透深度短于所述塑料结构中的激光穿透深度。
19.根据权利要求11所述的方法,其中:
所述标记板具有比所述塑料结构更高的刚度。
20.根据权利要求11所述的方法,其中:
所述标记板具有与所述一个或多个IC芯片基本相等的热膨胀系数(CTE)。
CN201880002334.9A 2018-10-30 2018-10-30 Ic封装 Pending CN109564905A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/112567 WO2020087253A1 (en) 2018-10-30 2018-10-30 Ic package

Publications (1)

Publication Number Publication Date
CN109564905A true CN109564905A (zh) 2019-04-02

Family

ID=65872658

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880002334.9A Pending CN109564905A (zh) 2018-10-30 2018-10-30 Ic封装

Country Status (7)

Country Link
US (2) US20200135656A1 (zh)
EP (1) EP3834227A4 (zh)
JP (1) JP7303294B2 (zh)
KR (1) KR20210033010A (zh)
CN (1) CN109564905A (zh)
TW (1) TWI754785B (zh)
WO (1) WO2020087253A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112397486A (zh) * 2019-08-12 2021-02-23 爱思开海力士有限公司 包括层叠的半导体芯片的半导体封装
CN114361115A (zh) * 2021-12-31 2022-04-15 中山市木林森微电子有限公司 一种多芯片埋入式封装模块结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220070877A (ko) 2020-11-23 2022-05-31 삼성전자주식회사 반도체 패키지
EP4270476A1 (en) * 2022-04-29 2023-11-01 Infineon Technologies Austria AG Semiconductor package and method for marking a semiconductor package

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010045644A1 (en) * 2000-01-13 2001-11-29 Chien-Ping Huang Semiconductor package having heat sink at the outer surface
US20040082103A1 (en) * 2002-10-24 2004-04-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with marking film and manufacturing method thereof
US20050133905A1 (en) * 2000-12-22 2005-06-23 Broadcom Corporation Method of assembling a ball grid array package with patterned stiffener layer
CN1702689A (zh) * 2004-05-27 2005-11-30 因芬尼昂技术股份公司 接触性芯片卡、其制造方法及其应用
US20070170573A1 (en) * 2006-01-20 2007-07-26 Kuroda Soshi Semiconductor device, interposer chip and manufacturing method of semiconductor device
CN101926001A (zh) * 2008-10-15 2010-12-22 德州仪器公司 具有标记层的半导体封装
US20140077352A1 (en) * 2012-09-14 2014-03-20 George R. Leal Matrix Lid Heatspreader for Flip Chip Package
CN104064528A (zh) * 2013-03-22 2014-09-24 株式会社东芝 半导体装置及其制造方法
CN108630669A (zh) * 2017-03-22 2018-10-09 东芝存储器株式会社 半导体装置

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788627A (en) * 1986-06-06 1988-11-29 Tektronix, Inc. Heat sink device using composite metal alloy
JPH0563113A (ja) * 1991-09-04 1993-03-12 Sony Corp 樹脂封止型半導体装置
US5461257A (en) * 1994-03-31 1995-10-24 Sgs-Thomson Microelectronics, Inc. Integrated circuit package with flat-topped heat sink
US6238954B1 (en) * 1999-09-28 2001-05-29 Intel Corporation COF packaged semiconductor
TW452956B (en) * 2000-01-04 2001-09-01 Siliconware Precision Industries Co Ltd Heat dissipation structure of BGA semiconductor package
JP2001217340A (ja) * 2000-02-01 2001-08-10 Nec Corp 半導体装置及びその製造方法
JP3904934B2 (ja) 2002-01-29 2007-04-11 京セラ株式会社 半導体装置
JP2005117009A (ja) * 2003-09-17 2005-04-28 Denso Corp 半導体装置およびその製造方法
TWI235473B (en) * 2004-04-22 2005-07-01 Advanced Semiconductor Eng Ball grid array package structure, heat slug structure, and laser mark rework method
US7361986B2 (en) * 2004-12-01 2008-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Heat stud for stacked chip package
TW200636954A (en) * 2005-04-15 2006-10-16 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package and fabrication method thereof
EP2111636B1 (en) 2006-12-21 2021-08-04 Bell Semiconductor, LLC High thermal performance packaging for circuit dies
US20080157342A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package with a marking structure and method of the same
JP2009141147A (ja) * 2007-12-06 2009-06-25 Nec Electronics Corp 半導体装置の製造方法
JP4995764B2 (ja) 2008-04-25 2012-08-08 力成科技股▲分▼有限公司 リード支持型半導体パッケージ
TWM357702U (en) * 2009-01-15 2009-05-21 Domintech Co Ltd Chip package with colored pattern
JP5115594B2 (ja) 2010-06-23 2013-01-09 株式会社デンソー 半導体モジュール
CN102004940B (zh) * 2010-11-30 2013-01-09 天水华天科技股份有限公司 一种高密度sim卡封装件的生产方法
JP5740995B2 (ja) 2011-01-17 2015-07-01 富士通株式会社 半導体装置及びその製造方法
JP2013211407A (ja) * 2012-03-30 2013-10-10 J Devices:Kk 半導体モジュール
JP5959097B2 (ja) * 2012-07-03 2016-08-02 ルネサスエレクトロニクス株式会社 半導体装置
KR20140009732A (ko) 2012-07-12 2014-01-23 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
JP5918664B2 (ja) 2012-09-10 2016-05-18 株式会社東芝 積層型半導体装置の製造方法
US9570405B2 (en) * 2013-02-21 2017-02-14 Ps4 Luxco S.A.R.L. Semiconductor device and method for manufacturing same
WO2014181766A1 (ja) * 2013-05-07 2014-11-13 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及び半導体装置の製造方法
US9508653B2 (en) * 2013-09-18 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Die-tracing in integrated circuit manufacturing and packaging
US9318450B1 (en) * 2014-11-24 2016-04-19 Raytheon Company Patterned conductive epoxy heat-sink attachment in a monolithic microwave integrated circuit (MMIC)
CN107112250B (zh) * 2014-12-16 2019-11-05 德卡技术股份有限公司 标记半导体封装的方法
US9412722B1 (en) * 2015-02-12 2016-08-09 Dawning Leading Technology Inc. Multichip stacking package structure and method for manufacturing the same
US9779940B2 (en) * 2015-07-01 2017-10-03 Zhuahai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Chip package
JP6524003B2 (ja) 2016-03-17 2019-06-05 東芝メモリ株式会社 半導体装置
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
US10418341B2 (en) * 2016-08-31 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming SIP with electrical component terminals extending out from encapsulant
JP6821008B2 (ja) 2017-03-13 2021-01-27 三菱電機株式会社 マイクロ波デバイス及び空中線

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010045644A1 (en) * 2000-01-13 2001-11-29 Chien-Ping Huang Semiconductor package having heat sink at the outer surface
US20050133905A1 (en) * 2000-12-22 2005-06-23 Broadcom Corporation Method of assembling a ball grid array package with patterned stiffener layer
US20040082103A1 (en) * 2002-10-24 2004-04-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with marking film and manufacturing method thereof
CN1702689A (zh) * 2004-05-27 2005-11-30 因芬尼昂技术股份公司 接触性芯片卡、其制造方法及其应用
US20070170573A1 (en) * 2006-01-20 2007-07-26 Kuroda Soshi Semiconductor device, interposer chip and manufacturing method of semiconductor device
CN101926001A (zh) * 2008-10-15 2010-12-22 德州仪器公司 具有标记层的半导体封装
US20140077352A1 (en) * 2012-09-14 2014-03-20 George R. Leal Matrix Lid Heatspreader for Flip Chip Package
CN104064528A (zh) * 2013-03-22 2014-09-24 株式会社东芝 半导体装置及其制造方法
CN108630669A (zh) * 2017-03-22 2018-10-09 东芝存储器株式会社 半导体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112397486A (zh) * 2019-08-12 2021-02-23 爱思开海力士有限公司 包括层叠的半导体芯片的半导体封装
CN112397486B (zh) * 2019-08-12 2024-01-30 爱思开海力士有限公司 包括层叠的半导体芯片的半导体封装
CN114361115A (zh) * 2021-12-31 2022-04-15 中山市木林森微电子有限公司 一种多芯片埋入式封装模块结构

Also Published As

Publication number Publication date
JP2022505927A (ja) 2022-01-14
EP3834227A4 (en) 2022-03-30
US20220013471A1 (en) 2022-01-13
JP7303294B2 (ja) 2023-07-04
TW202017134A (zh) 2020-05-01
TWI754785B (zh) 2022-02-11
KR20210033010A (ko) 2021-03-25
US20200135656A1 (en) 2020-04-30
WO2020087253A1 (en) 2020-05-07
EP3834227A1 (en) 2021-06-16

Similar Documents

Publication Publication Date Title
US6744125B2 (en) Super thin/super thermal ball grid array package
CN109564905A (zh) Ic封装
US10475752B2 (en) Semiconductor package structure and method of making the same
US20190279925A1 (en) Semiconductor package structure and method of making the same
US20080211083A1 (en) Electronic package and manufacturing method thereof
US8994168B2 (en) Semiconductor package including radiation plate
KR102228461B1 (ko) 반도체 패키지 장치
TW201735293A (zh) 晶片埋入式印刷電路板及應用印刷電路板之半導體封裝及其製造方法
US9147600B2 (en) Packages for multiple semiconductor chips
US7696618B2 (en) POP (package-on-package) semiconductor device
US6032355A (en) Method of forming thermal conductive structure on printed circuit board
JP2012015225A (ja) 半導体装置
US20060076694A1 (en) Semiconductor device package with concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency
US20080305576A1 (en) Method of reducing warpage in semiconductor molded panel
JP2014107554A (ja) 積層型半導体パッケージ
US20080305306A1 (en) Semiconductor molded panel having reduced warpage
KR100829613B1 (ko) 반도체 칩 패키지 및 그 제조 방법
US20060189120A1 (en) Method of making reinforced semiconductor package
KR20080024492A (ko) 오버 몰딩된 ic 패키지의 휨을 줄이는 방법
CN112490223A (zh) 半导体装置
JP2005259860A (ja) 電子回路装置
JP2007287820A (ja) 電子装置及びその製造方法
TWI817496B (zh) 一種具絕緣板之整合封裝
TWI843813B (zh) 半導體裝置
US20060091567A1 (en) Cavity-down Package and Method for Fabricating the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190402

RJ01 Rejection of invention patent application after publication